1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_query_hw.h"
39 #include "freedreno_util.h"
42 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
43 * inside the GPU. All rendering happens to GMEM. Larger render targets
44 * are split into tiles that are small enough for the color (and depth and/or
45 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
46 * if there was not a clear invalidating the previous tile contents, we need
47 * to restore the previous tiles contents (system mem -> GMEM), and after all
48 * the draw calls, before moving to the next tile, we need to save the tile
49 * contents (GMEM -> system mem).
51 * The code in this file handles dealing with GMEM and tiling.
53 * The structure of the ringbuffer ends up being:
55 * +--<---<-- IB ---<---+---<---+---<---<---<--+
58 * ------------------------------------------------------
59 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
60 * ------------------------------------------------------
63 * address submitted in issueibcmds
65 * Where the per-tile section handles scissor setup, mem2gmem restore (if
66 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
70 static uint32_t bin_width(struct fd_context
*ctx
)
72 if (ctx
->screen
->gpu_id
>= 300)
78 calculate_tiles(struct fd_context
*ctx
)
80 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
81 struct pipe_scissor_state
*scissor
= &ctx
->max_scissor
;
82 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
83 uint32_t gmem_size
= ctx
->screen
->gmemsize_bytes
;
84 uint32_t minx
, miny
, width
, height
;
85 uint32_t nbins_x
= 1, nbins_y
= 1;
86 uint32_t bin_w
, bin_h
;
87 uint32_t max_width
= bin_width(ctx
);
89 uint32_t i
, j
, t
, xoff
, yoff
;
90 uint32_t tpp_x
, tpp_y
;
91 bool has_zs
= !!(ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
));
94 cpp
= util_format_get_blocksize(pfb
->cbufs
[0]->format
);
96 if ((gmem
->cpp
== cpp
) && (gmem
->has_zs
== has_zs
) &&
97 !memcmp(&gmem
->scissor
, scissor
, sizeof(gmem
->scissor
))) {
98 /* everything is up-to-date */
102 /* if have depth/stencil, we need to leave room: */
108 if (fd_mesa_debug
& FD_DBG_DSCIS
) {
112 height
= pfb
->height
;
114 minx
= scissor
->minx
& ~31; /* round down to multiple of 32 */
115 miny
= scissor
->miny
& ~31;
116 width
= scissor
->maxx
- minx
;
117 height
= scissor
->maxy
- miny
;
120 bin_w
= align(width
, 32);
121 bin_h
= align(height
, 32);
123 /* first, find a bin width that satisfies the maximum width
126 while (bin_w
> max_width
) {
128 bin_w
= align(width
/ nbins_x
, 32);
131 /* then find a bin height that satisfies the memory constraints:
133 while ((bin_w
* bin_h
* cpp
) > gmem_size
) {
135 bin_h
= align(height
/ nbins_y
, 32);
138 DBG("using %d bins of size %dx%d", nbins_x
*nbins_y
, bin_w
, bin_h
);
140 gmem
->scissor
= *scissor
;
142 gmem
->has_zs
= has_zs
;
145 gmem
->nbins_x
= nbins_x
;
146 gmem
->nbins_y
= nbins_y
;
150 gmem
->height
= height
;
153 * Assign tiles and pipes:
155 * At some point it might be worth playing with different
156 * strategies and seeing if that makes much impact on
160 #define div_round_up(v, a) (((v) + (a) - 1) / (a))
161 /* figure out number of tiles per pipe: */
163 while (div_round_up(nbins_y
, tpp_y
) > 8)
165 while ((div_round_up(nbins_y
, tpp_y
) *
166 div_round_up(nbins_x
, tpp_x
)) > 8)
169 /* configure pipes: */
171 for (i
= 0; i
< ARRAY_SIZE(ctx
->pipe
); i
++) {
172 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
174 if (xoff
>= nbins_x
) {
179 if (yoff
>= nbins_y
) {
185 pipe
->w
= MIN2(tpp_x
, nbins_x
- xoff
);
186 pipe
->h
= MIN2(tpp_y
, nbins_y
- yoff
);
191 for (; i
< ARRAY_SIZE(ctx
->pipe
); i
++) {
192 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
193 pipe
->x
= pipe
->y
= pipe
->w
= pipe
->h
= 0;
197 printf("%dx%d ... tpp=%dx%d\n", nbins_x
, nbins_y
, tpp_x
, tpp_y
);
198 for (i
= 0; i
< 8; i
++) {
199 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
200 printf("pipe[%d]: %ux%u @ %u,%u\n", i
,
201 pipe
->w
, pipe
->h
, pipe
->x
, pipe
->y
);
205 /* configure tiles: */
208 for (i
= 0; i
< nbins_y
; i
++) {
213 /* clip bin height: */
214 bh
= MIN2(bin_h
, miny
+ height
- yoff
);
216 for (j
= 0; j
< nbins_x
; j
++) {
217 struct fd_tile
*tile
= &ctx
->tile
[t
];
220 assert(t
< ARRAY_SIZE(ctx
->tile
));
223 p
= ((i
/ tpp_y
) * div_round_up(nbins_x
, tpp_x
)) + (j
/ tpp_x
);
226 n
= ((i
% tpp_y
) * tpp_x
) + (j
% tpp_x
);
228 /* clip bin width: */
229 bw
= MIN2(bin_w
, minx
+ width
- xoff
);
248 for (i
= 0; i
< nbins_y
; i
++) {
249 for (j
= 0; j
< nbins_x
; j
++) {
250 struct fd_tile
*tile
= &ctx
->tile
[t
++];
251 printf("|p:%u n:%u|", tile
->p
, tile
->n
);
259 render_tiles(struct fd_context
*ctx
)
261 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
264 ctx
->emit_tile_init(ctx
);
267 ctx
->stats
.batch_restore
++;
269 for (i
= 0; i
< (gmem
->nbins_x
* gmem
->nbins_y
); i
++) {
270 struct fd_tile
*tile
= &ctx
->tile
[i
];
272 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
273 tile
->bin_h
, tile
->yoff
, tile
->bin_w
, tile
->xoff
);
275 ctx
->emit_tile_prep(ctx
, tile
);
278 fd_hw_query_set_stage(ctx
, ctx
->ring
, FD_STAGE_MEM2GMEM
);
279 ctx
->emit_tile_mem2gmem(ctx
, tile
);
280 fd_hw_query_set_stage(ctx
, ctx
->ring
, FD_STAGE_NULL
);
283 ctx
->emit_tile_renderprep(ctx
, tile
);
285 fd_hw_query_prepare_tile(ctx
, i
, ctx
->ring
);
287 /* emit IB to drawcmds: */
288 OUT_IB(ctx
->ring
, ctx
->draw_start
, ctx
->draw_end
);
291 /* emit gmem2mem to transfer tile back to system memory: */
292 fd_hw_query_set_stage(ctx
, ctx
->ring
, FD_STAGE_GMEM2MEM
);
293 ctx
->emit_tile_gmem2mem(ctx
, tile
);
294 fd_hw_query_set_stage(ctx
, ctx
->ring
, FD_STAGE_NULL
);
299 render_sysmem(struct fd_context
*ctx
)
301 ctx
->emit_sysmem_prep(ctx
);
303 fd_hw_query_prepare_tile(ctx
, 0, ctx
->ring
);
305 /* emit IB to drawcmds: */
306 OUT_IB(ctx
->ring
, ctx
->draw_start
, ctx
->draw_end
);
311 fd_gmem_render_tiles(struct pipe_context
*pctx
)
313 struct fd_context
*ctx
= fd_context(pctx
);
314 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
315 uint32_t timestamp
= 0;
318 if (ctx
->emit_sysmem_prep
) {
319 if (ctx
->cleared
|| ctx
->gmem_reason
|| (ctx
->num_draws
> 5)) {
320 DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
321 ctx
->cleared
, ctx
->gmem_reason
, ctx
->num_draws
);
322 } else if (!(fd_mesa_debug
& FD_DBG_DBYPASS
)) {
327 /* close out the draw cmds by making sure any active queries are
330 fd_hw_query_set_stage(ctx
, ctx
->ring
, FD_STAGE_NULL
);
332 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
333 fd_ringmarker_mark(ctx
->draw_end
);
334 fd_ringmarker_mark(ctx
->binning_end
);
338 ctx
->stats
.batch_total
++;
341 DBG("rendering sysmem (%s/%s)",
342 util_format_short_name(pipe_surface_format(pfb
->cbufs
[0])),
343 util_format_short_name(pipe_surface_format(pfb
->zsbuf
)));
344 fd_hw_query_prepare(ctx
, 1);
346 ctx
->stats
.batch_sysmem
++;
348 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
349 calculate_tiles(ctx
);
350 DBG("rendering %dx%d tiles (%s/%s)", gmem
->nbins_x
, gmem
->nbins_y
,
351 util_format_short_name(pipe_surface_format(pfb
->cbufs
[0])),
352 util_format_short_name(pipe_surface_format(pfb
->zsbuf
)));
353 fd_hw_query_prepare(ctx
, gmem
->nbins_x
* gmem
->nbins_y
);
355 ctx
->stats
.batch_gmem
++;
358 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
359 fd_ringmarker_flush(ctx
->draw_end
);
361 /* mark start for next draw/binning cmds: */
362 fd_ringmarker_mark(ctx
->draw_start
);
363 fd_ringmarker_mark(ctx
->binning_start
);
367 /* update timestamps on render targets: */
368 timestamp
= fd_ringbuffer_timestamp(ctx
->ring
);
370 fd_resource(pfb
->cbufs
[0]->texture
)->timestamp
= timestamp
;
372 fd_resource(pfb
->zsbuf
->texture
)->timestamp
= timestamp
;
374 /* reset maximal bounds: */
375 ctx
->max_scissor
.minx
= ctx
->max_scissor
.miny
= ~0;
376 ctx
->max_scissor
.maxx
= ctx
->max_scissor
.maxy
= 0;
378 /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
379 * after the draw/clear calls, but executed before, we need to preemptively
380 * flag some state as dirty before the first draw/clear call.
382 * TODO maybe we need to mark all state as dirty to not worry about state
383 * being clobbered by other contexts?
385 ctx
->dirty
|= FD_DIRTY_ZSA
|
386 FD_DIRTY_RASTERIZER
|
387 FD_DIRTY_FRAMEBUFFER
|
388 FD_DIRTY_SAMPLE_MASK
|
393 /* probably only needed if we need to mem2gmem on the next
394 * draw.. but not sure if there is a good way to know?
400 if (fd_mesa_debug
& FD_DBG_DGMEM
)
401 ctx
->dirty
= 0xffffffff;