src/gallium/drivers/freedreno/freedreno_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_pack_color.h"
  34
  35 #include "freedreno_gmem.h"
  36 #include "freedreno_context.h"
  37 #include "freedreno_state.h"
  38 #include "freedreno_program.h"
  39 #include "freedreno_resource.h"
  40 #include "freedreno_zsa.h"
  41 #include "freedreno_util.h"
  42
  43 /*
  44  * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
  45  * inside the GPU.  All rendering happens to GMEM.  Larger render targets
  46  * are split into tiles that are small enough for the color (and depth and/or
  47  * stencil, if enabled) buffers to fit within GMEM.  Before rendering a tile,
  48  * if there was not a clear invalidating the previous tile contents, we need
  49  * to restore the previous tiles contents (system mem -> GMEM), and after all
  50  * the draw calls, before moving to the next tile, we need to save the tile
  51  * contents (GMEM -> system mem).
  52  *
  53  * The code in this file handles dealing with GMEM and tiling.
  54  *
  55  * The structure of the ringbuffer ends up being:
  56  *
  57  *     +--<---<-- IB ---<---+---<---+---<---<---<--+
  58  *     |                    |       |              |
  59  *     v                    ^       ^              ^
  60  *   ------------------------------------------------------
  61  *     | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
  62  *   ------------------------------------------------------
  63  *                       ^
  64  *                       |
  65  *                       address submitted in issueibcmds
  66  *
  67  * Where the per-tile section handles scissor setup, mem2gmem restore (if
  68  * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
  69  * resolve.
  70  */
  71
  72 /* transfer from gmem to system memory (ie. normal RAM) */
  73
  74 static void
  75 emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
  76                 struct pipe_surface *psurf)
  77 {
  78         struct fd_resource *rsc = fd_resource(psurf->texture);
  79
  80         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  81         OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
  82         OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) |
  83                         RB_COLOR_INFO_COLOR_BASE(base / 1024) |
  84                         RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format)));
  85
  86         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
  87         OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
  88         OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
  89         OUT_RELOC(ring, rsc->bo, 0, 0);         /* RB_COPY_DEST_BASE */
  90         OUT_RING(ring, rsc->pitch >> 5);        /* RB_COPY_DEST_PITCH */
  91         OUT_RING(ring, RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) |
  92                         RB_COPY_DEST_INFO_LINEAR |      /* RB_COPY_DEST_INFO */
  93                         RB_COPY_DEST_INFO_SWAP(swap) |
  94                         RB_COPY_DEST_INFO_WRITE_RED |
  95                         RB_COPY_DEST_INFO_WRITE_GREEN |
  96                         RB_COPY_DEST_INFO_WRITE_BLUE |
  97                         RB_COPY_DEST_INFO_WRITE_ALPHA);
  98
  99         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 100         OUT_RING(ring, 0x0000000);
 101
 102         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 103         OUT_RING(ring, 0x00000000);
 104         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
 105                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 106         OUT_RING(ring, 3);                                      /* NumIndices */
 107 }
 108
 109 static void
 110 emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring,
 111                 uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
 112 {
 113         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 114
 115         fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
 116                         { .prsc = ctx->solid_vertexbuf, .size = 48 },
 117                 }, 1);
 118
 119         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 120         OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
 121         OUT_RING(ring, 0);
 122
 123         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 124         OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
 125         OUT_RING(ring, 0x0000028f);
 126
 127         fd_program_emit(ring, &ctx->solid_prog);
 128
 129         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 130         OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
 131         OUT_RING(ring, 0x0000ffff);
 132
 133         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 134         OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
 135         OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 136
 137         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 138         OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL));
 139         OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 140                         PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
 141                         PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
 142
 143         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 144         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
 145         OUT_RING(ring, xy2d(0, 0));                       /* PA_SC_WINDOW_SCISSOR_TL */
 146         OUT_RING(ring, xy2d(pfb->width, pfb->height));    /* PA_SC_WINDOW_SCISSOR_BR */
 147
 148         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 149         OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
 150         OUT_RING(ring, PA_CL_VTE_CNTL_VTX_W0_FMT |
 151                         PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 152                         PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 153                         PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 154                         PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 155
 156         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 157         OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
 158         OUT_RING(ring, 0x00000000);
 159
 160         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 161         OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
 162         OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
 163
 164         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 165         OUT_RING(ring, CP_REG(REG_RB_COPY_DEST_OFFSET));
 166         OUT_RING(ring, RB_COPY_DEST_OFFSET_X(xoff) | RB_COPY_DEST_OFFSET_Y(yoff));
 167
 168         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 169                 emit_gmem2mem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
 170
 171         if (ctx->resolve & FD_BUFFER_COLOR)
 172                 emit_gmem2mem_surf(ring, 1, 0, pfb->cbufs[0]);
 173
 174         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 175         OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
 176         OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 177 }
 178
 179 /* transfer from system memory to gmem */
 180
 181 static void
 182 emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
 183                 struct pipe_surface *psurf)
 184 {
 185         struct fd_resource *rsc = fd_resource(psurf->texture);
 186         uint32_t swiz;
 187
 188         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 189         OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
 190         OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) |
 191                         RB_COLOR_INFO_COLOR_BASE(base / 1024) |
 192                         RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format)));
 193
 194         swiz = fd_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
 195                         PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA);
 196
 197         /* emit fb as a texture: */
 198         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 199         OUT_RING(ring, 0x00010000);
 200         OUT_RING(ring, SQ_TEX0_CLAMP_X(SQ_TEX_WRAP) |
 201                         SQ_TEX0_CLAMP_Y(SQ_TEX_WRAP) |
 202                         SQ_TEX0_CLAMP_Z(SQ_TEX_WRAP) |
 203                         SQ_TEX0_PITCH(rsc->pitch));
 204         OUT_RELOC(ring, rsc->bo, 0,
 205                         fd_pipe2surface(psurf->format) | 0x800);
 206         OUT_RING(ring, SQ_TEX2_WIDTH(psurf->width) |
 207                         SQ_TEX2_HEIGHT(psurf->height));
 208         OUT_RING(ring, 0x01000000 | // XXX
 209                         swiz |
 210                         SQ_TEX3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
 211                         SQ_TEX3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
 212         OUT_RING(ring, 0x00000000);
 213         OUT_RING(ring, 0x00000200);
 214
 215         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 216         OUT_RING(ring, 0x00000000);
 217         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
 218                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 219         OUT_RING(ring, 3);                                      /* NumIndices */
 220 }
 221
 222 static void
 223 emit_mem2gmem(struct fd_context *ctx, struct fd_ringbuffer *ring,
 224                 uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
 225 {
 226         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 227         float x0, y0, x1, y1;
 228
 229         fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
 230                         { .prsc = ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
 231                         { .prsc = ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
 232                 }, 2);
 233
 234         /* write texture coordinates to vertexbuf: */
 235         x0 = ((float)xoff) / ((float)pfb->width);
 236         x1 = ((float)xoff + bin_w) / ((float)pfb->width);
 237         y0 = ((float)yoff) / ((float)pfb->height);
 238         y1 = ((float)yoff + bin_h) / ((float)pfb->height);
 239         OUT_PKT3(ring, CP_MEM_WRITE, 9);
 240         OUT_RELOC(ring, fd_resource(ctx->solid_vertexbuf)->bo, 0x60, 0);
 241         OUT_RING(ring, f2d(x0));
 242         OUT_RING(ring, f2d(y0));
 243         OUT_RING(ring, f2d(x1));
 244         OUT_RING(ring, f2d(y0));
 245         OUT_RING(ring, f2d(x0));
 246         OUT_RING(ring, f2d(y1));
 247         OUT_RING(ring, f2d(x1));
 248         OUT_RING(ring, f2d(y1));
 249
 250         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 251         OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
 252         OUT_RING(ring, 0);
 253
 254         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 255         OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
 256         OUT_RING(ring, 0x0000003b);
 257
 258         fd_program_emit(ring, &ctx->blit_prog);
 259
 260         OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1);
 261         OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE);
 262
 263         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 264         OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
 265         OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 266
 267         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 268         OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL));
 269         OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
 270                         PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
 271                         PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
 272
 273         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 274         OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
 275         OUT_RING(ring, 0x0000ffff);
 276
 277         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 278         OUT_RING(ring, CP_REG(REG_RB_COLORCONTROL));
 279         OUT_RING(ring, RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
 280                         RB_COLORCONTROL_BLEND_DISABLE |
 281                         RB_COLORCONTROL_ROP_CODE(12) |
 282                         RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 283                         RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 284
 285         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 286         OUT_RING(ring, CP_REG(REG_RB_BLEND_CONTROL));
 287         OUT_RING(ring, RB_BLENDCONTROL_COLOR_SRCBLEND(RB_BLEND_ONE) |
 288                         RB_BLENDCONTROL_COLOR_COMB_FCN(COMB_DST_PLUS_SRC) |
 289                         RB_BLENDCONTROL_COLOR_DESTBLEND(RB_BLEND_ZERO) |
 290                         RB_BLENDCONTROL_ALPHA_SRCBLEND(RB_BLEND_ONE) |
 291                         RB_BLENDCONTROL_ALPHA_COMB_FCN(COMB_DST_PLUS_SRC) |
 292                         RB_BLENDCONTROL_ALPHA_DESTBLEND(RB_BLEND_ZERO));
 293
 294         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 295         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
 296         OUT_RING(ring, PA_SC_WINDOW_OFFSET_DISABLE |
 297                         xy2d(0,0));                     /* PA_SC_WINDOW_SCISSOR_TL */
 298         OUT_RING(ring, xy2d(bin_w, bin_h));     /* PA_SC_WINDOW_SCISSOR_BR */
 299
 300         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 301         OUT_RING(ring, CP_REG(REG_PA_CL_VPORT_XSCALE));
 302         OUT_RING(ring, f2d((float)bin_w/2.0));  /* PA_CL_VPORT_XSCALE */
 303         OUT_RING(ring, f2d((float)bin_w/2.0));  /* PA_CL_VPORT_XOFFSET */
 304         OUT_RING(ring, f2d(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
 305         OUT_RING(ring, f2d((float)bin_h/2.0));  /* PA_CL_VPORT_YOFFSET */
 306
 307         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 308         OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
 309         OUT_RING(ring, PA_CL_VTE_CNTL_VTX_XY_FMT |
 310                         PA_CL_VTE_CNTL_VTX_Z_FMT |       // XXX check this???
 311                         PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 312                         PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 313                         PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 314                         PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 315
 316         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 317         OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
 318         OUT_RING(ring, 0x00000000);
 319
 320         if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 321                 emit_mem2gmem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
 322
 323         if (ctx->restore & FD_BUFFER_COLOR)
 324                 emit_mem2gmem_surf(ring, 1, 0, pfb->cbufs[0]);
 325
 326         /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
 327 }
 328
 329 static void
 330 calculate_tiles(struct fd_context *ctx)
 331 {
 332         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 333         struct pipe_scissor_state *scissor = &ctx->max_scissor;
 334         uint32_t cpp = util_format_get_blocksize(ctx->framebuffer.cbufs[0]->format);
 335         uint32_t gmem_size = ctx->screen->gmemsize_bytes;
 336         uint32_t minx, miny, width, height;
 337         uint32_t nbins_x = 1, nbins_y = 1;
 338         uint32_t bin_w, bin_h;
 339         uint32_t max_width = 992;
 340
 341         if ((gmem->cpp == cpp) &&
 342                         !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
 343                 /* everything is up-to-date */
 344                 return;
 345         }
 346
 347         minx = scissor->minx & ~31; /* round down to multiple of 32 */
 348         miny = scissor->miny & ~31;
 349         width = scissor->maxx - minx;
 350         height = scissor->maxy - miny;
 351
 352 // TODO we probably could optimize this a bit if we know that
 353 // Z or stencil is not enabled for any of the draw calls..
 354 //      if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
 355                 gmem_size /= 2;
 356                 max_width = 256;
 357 //      }
 358
 359         bin_w = ALIGN(width, 32);
 360         bin_h = ALIGN(height, 32);
 361
 362         /* first, find a bin width that satisfies the maximum width
 363          * restrictions:
 364          */
 365         while (bin_w > max_width) {
 366                 nbins_x++;
 367                 bin_w = ALIGN(width / nbins_x, 32);
 368         }
 369
 370         /* then find a bin height that satisfies the memory constraints:
 371          */
 372         while ((bin_w * bin_h * cpp) > gmem_size) {
 373                 nbins_y++;
 374                 bin_h = ALIGN(height / nbins_y, 32);
 375         }
 376
 377         DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
 378
 379         gmem->scissor = *scissor;
 380         gmem->cpp = cpp;
 381         gmem->minx = minx;
 382         gmem->miny = miny;
 383         gmem->bin_h = bin_h;
 384         gmem->bin_w = bin_w;
 385         gmem->nbins_x = nbins_x;
 386         gmem->nbins_y = nbins_y;
 387         gmem->width = width;
 388         gmem->height = height;
 389 }
 390
 391 void
 392 fd_gmem_render_tiles(struct pipe_context *pctx)
 393 {
 394         struct fd_context *ctx = fd_context(pctx);
 395         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 396         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 397         struct fd_ringbuffer *ring = ctx->ring;
 398         enum rb_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format);
 399         uint32_t i, timestamp, yoff = 0;
 400         uint32_t base, reg;
 401
 402         calculate_tiles(ctx);
 403
 404         /* this should be true because bin_w/bin_h should be multiples of 32: */
 405         assert(((gmem->bin_w * gmem->bin_h) % 1024) == 0);
 406
 407         /* depth/stencil starts after color buffer in GMEM: */
 408         base = (gmem->bin_w * gmem->bin_h) / 1024;
 409
 410         DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
 411                         util_format_name(pfb->cbufs[0]->format),
 412                         pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
 413
 414         /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
 415         fd_ringmarker_mark(ctx->draw_end);
 416
 417         /* RB_SURFACE_INFO / RB_DEPTH_INFO can be emitted once per tile pass,
 418          * but RB_COLOR_INFO gets overwritten by gmem2mem and mem2gmem and so
 419          * needs to be emitted for each tile:
 420          */
 421         OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 422         OUT_RING(ring, CP_REG(REG_RB_SURFACE_INFO));
 423         OUT_RING(ring, gmem->bin_w);                 /* RB_SURFACE_INFO */
 424         OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(1) | /* RB_COLOR_INFO */
 425                         RB_COLOR_INFO_COLOR_FORMAT(colorformatx));
 426         reg = RB_DEPTH_INFO_DEPTH_BASE(ALIGN(base, 4));
 427         if (pfb->zsbuf)
 428                 reg |= RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 429         OUT_RING(ring, reg);                         /* RB_DEPTH_INFO */
 430
 431         yoff= gmem->miny;
 432         for (i = 0; i < gmem->nbins_y; i++) {
 433                 uint32_t j, xoff = gmem->minx;
 434                 uint32_t bh = gmem->bin_h;
 435
 436                 /* clip bin height: */
 437                 bh = min(bh, gmem->height - yoff);
 438
 439                 for (j = 0; j < gmem->nbins_x; j++) {
 440                         uint32_t bw = gmem->bin_w;
 441
 442                         /* clip bin width: */
 443                         bw = min(bw, gmem->width - xoff);
 444
 445                         DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 446                                         bh, yoff, bw, xoff);
 447
 448                         if ((i == 0) && (j == 0)) {
 449                                 uint32_t reg;
 450
 451
 452                         } else {
 453
 454                         }
 455
 456                         /* setup screen scissor for current tile (same for mem2gmem): */
 457                         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 458                         OUT_RING(ring, CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL));
 459                         OUT_RING(ring, xy2d(0,0));           /* PA_SC_SCREEN_SCISSOR_TL */
 460                         OUT_RING(ring, xy2d(bw, bh));        /* PA_SC_SCREEN_SCISSOR_BR */
 461
 462                         if (ctx->restore)
 463                                 emit_mem2gmem(ctx, ring, xoff, yoff, bw, bh);
 464
 465                         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 466                         OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
 467                         OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(1) | /* RB_COLOR_INFO */
 468                                         RB_COLOR_INFO_COLOR_FORMAT(colorformatx));
 469
 470                         /* setup window scissor and offset for current tile (different
 471                          * from mem2gmem):
 472                          */
 473                         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 474                         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
 475                         OUT_RING(ring, PA_SC_WINDOW_OFFSET_X(-xoff) |
 476                                         PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */
 477
 478                         /* emit IB to drawcmds: */
 479                         OUT_IB  (ring, ctx->draw_start, ctx->draw_end);
 480
 481                         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 482                         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
 483                         OUT_RING(ring, 0x00000000);          /* PA_SC_WINDOW_OFFSET */
 484
 485                         /* emit gmem2mem to transfer tile back to system memory: */
 486                         emit_gmem2mem(ctx, ring, xoff, yoff, bw, bh);
 487
 488                         xoff += bw;
 489                 }
 490
 491                 yoff += bh;
 492         }
 493
 494         /* GPU executes starting from tile cmds, which IB back to draw cmds: */
 495         fd_ringmarker_flush(ctx->draw_end);
 496
 497         /* mark start for next draw cmds: */
 498         fd_ringmarker_mark(ctx->draw_start);
 499
 500         /* update timestamps on render targets: */
 501         fd_pipe_timestamp(ctx->screen->pipe, &timestamp);
 502         fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
 503         if (pfb->zsbuf)
 504                 fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
 505
 506         /* reset maximal bounds: */
 507         ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
 508         ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
 509
 510         /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
 511          * after the draw/clear calls, but executed before, we need to preemptively
 512          * flag some state as dirty before the first draw/clear call.
 513          *
 514          * TODO maybe we need to mark all state as dirty to not worry about state
 515          * being clobbered by other contexts?
 516          */
 517         ctx->dirty |= FD_DIRTY_ZSA |
 518                         FD_DIRTY_RASTERIZER |
 519                         FD_DIRTY_FRAMEBUFFER |
 520                         FD_DIRTY_SAMPLE_MASK |
 521                         FD_DIRTY_VIEWPORT |
 522                         FD_DIRTY_CONSTBUF |
 523                         FD_DIRTY_PROG |
 524                         FD_DIRTY_SCISSOR |
 525                         /* probably only needed if we need to mem2gmem on the next
 526                          * draw..  but not sure if there is a good way to know?
 527                          */
 528                         FD_DIRTY_VERTTEX |
 529                         FD_DIRTY_FRAGTEX |
 530                         FD_DIRTY_BLEND;
 531 }