src/gallium/drivers/freedreno/freedreno_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_gmem.h"
  36 #include "freedreno_context.h"
  37 #include "freedreno_resource.h"
  38 #include "freedreno_query_hw.h"
  39 #include "freedreno_util.h"
  40
  41 /*
  42  * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
  43  * inside the GPU.  All rendering happens to GMEM.  Larger render targets
  44  * are split into tiles that are small enough for the color (and depth and/or
  45  * stencil, if enabled) buffers to fit within GMEM.  Before rendering a tile,
  46  * if there was not a clear invalidating the previous tile contents, we need
  47  * to restore the previous tiles contents (system mem -> GMEM), and after all
  48  * the draw calls, before moving to the next tile, we need to save the tile
  49  * contents (GMEM -> system mem).
  50  *
  51  * The code in this file handles dealing with GMEM and tiling.
  52  *
  53  * The structure of the ringbuffer ends up being:
  54  *
  55  *     +--<---<-- IB ---<---+---<---+---<---<---<--+
  56  *     |                    |       |              |
  57  *     v                    ^       ^              ^
  58  *   ------------------------------------------------------
  59  *     | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
  60  *   ------------------------------------------------------
  61  *                       ^
  62  *                       |
  63  *                       address submitted in issueibcmds
  64  *
  65  * Where the per-tile section handles scissor setup, mem2gmem restore (if
  66  * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
  67  * resolve.
  68  */
  69
  70 static uint32_t bin_width(struct fd_context *ctx)
  71 {
  72         if (is_a4xx(ctx->screen))
  73                 return 1024;
  74         if (is_a3xx(ctx->screen))
  75                 return 992;
  76         return 512;
  77 }
  78
  79 static void
  80 calculate_tiles(struct fd_context *ctx)
  81 {
  82         struct fd_gmem_stateobj *gmem = &ctx->gmem;
  83         struct pipe_scissor_state *scissor = &ctx->max_scissor;
  84         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
  85         uint32_t gmem_size = ctx->screen->gmemsize_bytes;
  86         uint32_t minx, miny, width, height;
  87         uint32_t nbins_x = 1, nbins_y = 1;
  88         uint32_t bin_w, bin_h;
  89         uint32_t max_width = bin_width(ctx);
  90         uint32_t cpp = 4;
  91         uint32_t i, j, t, xoff, yoff;
  92         uint32_t tpp_x, tpp_y;
  93         bool has_zs = !!(ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
  94
  95         if (pfb->cbufs[0])
  96                 cpp = util_format_get_blocksize(pfb->cbufs[0]->format);
  97
  98         if ((gmem->cpp == cpp) && (gmem->has_zs == has_zs) &&
  99                         !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
 100                 /* everything is up-to-date */
 101                 return;
 102         }
 103
 104         /* if have depth/stencil, we need to leave room: */
 105         if (has_zs) {
 106                 gmem_size /= 2;
 107                 max_width /= 2;
 108         }
 109
 110         if (fd_mesa_debug & FD_DBG_NOSCIS) {
 111                 minx = 0;
 112                 miny = 0;
 113                 width = pfb->width;
 114                 height = pfb->height;
 115         } else {
 116                 minx = scissor->minx & ~31; /* round down to multiple of 32 */
 117                 miny = scissor->miny & ~31;
 118                 width = scissor->maxx - minx;
 119                 height = scissor->maxy - miny;
 120         }
 121
 122         bin_w = align(width, 32);
 123         bin_h = align(height, 32);
 124
 125         /* first, find a bin width that satisfies the maximum width
 126          * restrictions:
 127          */
 128         while (bin_w > max_width) {
 129                 nbins_x++;
 130                 bin_w = align(width / nbins_x, 32);
 131         }
 132
 133         /* then find a bin width/height that satisfies the memory
 134          * constraints:
 135          */
 136         while ((bin_w * bin_h * cpp) > gmem_size) {
 137                 if (bin_w > bin_h) {
 138                         nbins_x++;
 139                         bin_w = align(width / nbins_x, 32);
 140                 } else {
 141                         nbins_y++;
 142                         bin_h = align(height / nbins_y, 32);
 143                 }
 144         }
 145
 146         DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
 147
 148         gmem->scissor = *scissor;
 149         gmem->cpp = cpp;
 150         gmem->has_zs = has_zs;
 151         gmem->bin_h = bin_h;
 152         gmem->bin_w = bin_w;
 153         gmem->nbins_x = nbins_x;
 154         gmem->nbins_y = nbins_y;
 155         gmem->minx = minx;
 156         gmem->miny = miny;
 157         gmem->width = width;
 158         gmem->height = height;
 159
 160         /*
 161          * Assign tiles and pipes:
 162          *
 163          * At some point it might be worth playing with different
 164          * strategies and seeing if that makes much impact on
 165          * performance.
 166          */
 167
 168 #define div_round_up(v, a)  (((v) + (a) - 1) / (a))
 169         /* figure out number of tiles per pipe: */
 170         tpp_x = tpp_y = 1;
 171         while (div_round_up(nbins_y, tpp_y) > 8)
 172                 tpp_y += 2;
 173         while ((div_round_up(nbins_y, tpp_y) *
 174                         div_round_up(nbins_x, tpp_x)) > 8)
 175                 tpp_x += 1;
 176
 177         /* configure pipes: */
 178         xoff = yoff = 0;
 179         for (i = 0; i < ARRAY_SIZE(ctx->pipe); i++) {
 180                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 181
 182                 if (xoff >= nbins_x) {
 183                         xoff = 0;
 184                         yoff += tpp_y;
 185                 }
 186
 187                 if (yoff >= nbins_y) {
 188                         break;
 189                 }
 190
 191                 pipe->x = xoff;
 192                 pipe->y = yoff;
 193                 pipe->w = MIN2(tpp_x, nbins_x - xoff);
 194                 pipe->h = MIN2(tpp_y, nbins_y - yoff);
 195
 196                 xoff += tpp_x;
 197         }
 198
 199         for (; i < ARRAY_SIZE(ctx->pipe); i++) {
 200                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 201                 pipe->x = pipe->y = pipe->w = pipe->h = 0;
 202         }
 203
 204 #if 0 /* debug */
 205         printf("%dx%d ... tpp=%dx%d\n", nbins_x, nbins_y, tpp_x, tpp_y);
 206         for (i = 0; i < 8; i++) {
 207                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 208                 printf("pipe[%d]: %ux%u @ %u,%u\n", i,
 209                                 pipe->w, pipe->h, pipe->x, pipe->y);
 210         }
 211 #endif
 212
 213         /* configure tiles: */
 214         t = 0;
 215         yoff = miny;
 216         for (i = 0; i < nbins_y; i++) {
 217                 uint32_t bw, bh;
 218
 219                 xoff = minx;
 220
 221                 /* clip bin height: */
 222                 bh = MIN2(bin_h, miny + height - yoff);
 223
 224                 for (j = 0; j < nbins_x; j++) {
 225                         struct fd_tile *tile = &ctx->tile[t];
 226                         uint32_t n, p;
 227
 228                         assert(t < ARRAY_SIZE(ctx->tile));
 229
 230                         /* pipe number: */
 231                         p = ((i / tpp_y) * div_round_up(nbins_x, tpp_x)) + (j / tpp_x);
 232
 233                         /* slot number: */
 234                         n = ((i % tpp_y) * tpp_x) + (j % tpp_x);
 235
 236                         /* clip bin width: */
 237                         bw = MIN2(bin_w, minx + width - xoff);
 238
 239                         tile->n = n;
 240                         tile->p = p;
 241                         tile->bin_w = bw;
 242                         tile->bin_h = bh;
 243                         tile->xoff = xoff;
 244                         tile->yoff = yoff;
 245
 246                         t++;
 247
 248                         xoff += bw;
 249                 }
 250
 251                 yoff += bh;
 252         }
 253
 254 #if 0 /* debug */
 255         t = 0;
 256         for (i = 0; i < nbins_y; i++) {
 257                 for (j = 0; j < nbins_x; j++) {
 258                         struct fd_tile *tile = &ctx->tile[t++];
 259                         printf("|p:%u n:%u|", tile->p, tile->n);
 260                 }
 261                 printf("\n");
 262         }
 263 #endif
 264 }
 265
 266 static void
 267 render_tiles(struct fd_context *ctx)
 268 {
 269         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 270         int i;
 271
 272         ctx->emit_tile_init(ctx);
 273
 274         if (ctx->restore)
 275                 ctx->stats.batch_restore++;
 276
 277         for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
 278                 struct fd_tile *tile = &ctx->tile[i];
 279
 280                 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 281                         tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
 282
 283                 ctx->emit_tile_prep(ctx, tile);
 284
 285                 if (ctx->restore) {
 286                         fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_MEM2GMEM);
 287                         ctx->emit_tile_mem2gmem(ctx, tile);
 288                         fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 289                 }
 290
 291                 ctx->emit_tile_renderprep(ctx, tile);
 292
 293                 fd_hw_query_prepare_tile(ctx, i, ctx->ring);
 294
 295                 /* emit IB to drawcmds: */
 296                 OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 297                 fd_reset_wfi(ctx);
 298
 299                 /* emit gmem2mem to transfer tile back to system memory: */
 300                 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_GMEM2MEM);
 301                 ctx->emit_tile_gmem2mem(ctx, tile);
 302                 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 303         }
 304 }
 305
 306 static void
 307 render_sysmem(struct fd_context *ctx)
 308 {
 309         ctx->emit_sysmem_prep(ctx);
 310
 311         fd_hw_query_prepare_tile(ctx, 0, ctx->ring);
 312
 313         /* emit IB to drawcmds: */
 314         OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 315         fd_reset_wfi(ctx);
 316 }
 317
 318 void
 319 fd_gmem_render_tiles(struct fd_context *ctx)
 320 {
 321         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 322         uint32_t i, timestamp = 0;
 323         bool sysmem = false;
 324
 325         if (ctx->emit_sysmem_prep) {
 326                 if (ctx->cleared || ctx->gmem_reason || (ctx->num_draws > 5)) {
 327                         DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
 328                                 ctx->cleared, ctx->gmem_reason, ctx->num_draws);
 329                 } else if (!(fd_mesa_debug & FD_DBG_NOBYPASS)) {
 330                         sysmem = true;
 331                 }
 332         }
 333
 334         /* close out the draw cmds by making sure any active queries are
 335          * paused:
 336          */
 337         fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 338
 339         /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
 340         fd_ringmarker_mark(ctx->draw_end);
 341         fd_ringmarker_mark(ctx->binning_end);
 342
 343         fd_reset_wfi(ctx);
 344
 345         ctx->stats.batch_total++;
 346
 347         if (sysmem) {
 348                 DBG("rendering sysmem (%s/%s)",
 349                         util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 350                         util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 351                 fd_hw_query_prepare(ctx, 1);
 352                 render_sysmem(ctx);
 353                 ctx->stats.batch_sysmem++;
 354         } else {
 355                 struct fd_gmem_stateobj *gmem = &ctx->gmem;
 356                 calculate_tiles(ctx);
 357                 DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
 358                         util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 359                         util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 360                 fd_hw_query_prepare(ctx, gmem->nbins_x * gmem->nbins_y);
 361                 render_tiles(ctx);
 362                 ctx->stats.batch_gmem++;
 363         }
 364
 365         /* GPU executes starting from tile cmds, which IB back to draw cmds: */
 366         fd_ringmarker_flush(ctx->draw_end);
 367
 368         /* mark start for next draw/binning cmds: */
 369         fd_ringmarker_mark(ctx->draw_start);
 370         fd_ringmarker_mark(ctx->binning_start);
 371
 372         fd_reset_wfi(ctx);
 373
 374         /* update timestamps on render targets: */
 375         timestamp = fd_ringbuffer_timestamp(ctx->ring);
 376         for (i = 0; i < pfb->nr_cbufs; i++)
 377                 if (pfb->cbufs[i])
 378                         fd_resource(pfb->cbufs[i]->texture)->timestamp = timestamp;
 379         if (pfb->zsbuf)
 380                 fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
 381
 382         /* reset maximal bounds: */
 383         ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
 384         ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
 385
 386         ctx->dirty = ~0;
 387 }
 388
 389 /* tile needs restore if it isn't completely contained within the
 390  * cleared scissor:
 391  */
 392 static bool
 393 skip_restore(struct pipe_scissor_state *scissor, struct fd_tile *tile)
 394 {
 395         unsigned minx = tile->xoff;
 396         unsigned maxx = tile->xoff + tile->bin_w;
 397         unsigned miny = tile->yoff;
 398         unsigned maxy = tile->yoff + tile->bin_h;
 399         return (minx >= scissor->minx) && (maxx <= scissor->maxx) &&
 400                         (miny >= scissor->miny) && (maxy <= scissor->maxy);
 401 }
 402
 403 /* When deciding whether a tile needs mem2gmem, we need to take into
 404  * account the scissor rect(s) that were cleared.  To simplify we only
 405  * consider the last scissor rect for each buffer, since the common
 406  * case would be a single clear.
 407  */
 408 bool
 409 fd_gmem_needs_restore(struct fd_context *ctx, struct fd_tile *tile,
 410                 uint32_t buffers)
 411 {
 412         if (!(ctx->restore & buffers))
 413                 return false;
 414
 415         /* if buffers partially cleared, then slow-path to figure out
 416          * if this particular tile needs restoring:
 417          */
 418         if ((buffers & FD_BUFFER_COLOR) &&
 419                         (ctx->partial_cleared & FD_BUFFER_COLOR) &&
 420                         skip_restore(&ctx->cleared_scissor.color, tile))
 421                 return false;
 422         if ((buffers & FD_BUFFER_DEPTH) &&
 423                         (ctx->partial_cleared & FD_BUFFER_DEPTH) &&
 424                         skip_restore(&ctx->cleared_scissor.depth, tile))
 425                 return false;
 426         if ((buffers & FD_BUFFER_STENCIL) &&
 427                         (ctx->partial_cleared & FD_BUFFER_STENCIL) &&
 428                         skip_restore(&ctx->cleared_scissor.stencil, tile))
 429                 return false;
 430
 431         return true;
 432 }