src/gallium/drivers/freedreno/freedreno_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_pack_color.h"
  34
  35 #include "freedreno_gmem.h"
  36 #include "freedreno_context.h"
  37 #include "freedreno_state.h"
  38 #include "freedreno_program.h"
  39 #include "freedreno_resource.h"
  40 #include "freedreno_zsa.h"
  41 #include "freedreno_util.h"
  42
  43 /*
  44  * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
  45  * inside the GPU.  All rendering happens to GMEM.  Larger render targets
  46  * are split into tiles that are small enough for the color (and depth and/or
  47  * stencil, if enabled) buffers to fit within GMEM.  Before rendering a tile,
  48  * if there was not a clear invalidating the previous tile contents, we need
  49  * to restore the previous tiles contents (system mem -> GMEM), and after all
  50  * the draw calls, before moving to the next tile, we need to save the tile
  51  * contents (GMEM -> system mem).
  52  *
  53  * The code in this file handles dealing with GMEM and tiling.
  54  *
  55  * The structure of the ringbuffer ends up being:
  56  *
  57  *     +--<---<-- IB ---<---+---<---+---<---<---<--+
  58  *     |                    |       |              |
  59  *     v                    ^       ^              ^
  60  *   ------------------------------------------------------
  61  *     | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
  62  *   ------------------------------------------------------
  63  *                       ^
  64  *                       |
  65  *                       address submitted in issueibcmds
  66  *
  67  * Where the per-tile section handles scissor setup, mem2gmem restore (if
  68  * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
  69  * resolve.
  70  */
  71
  72 /* transfer from gmem to system memory (ie. normal RAM) */
  73
  74 static void
  75 emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
  76                 struct pipe_surface *psurf)
  77 {
  78         struct fd_resource *rsc = fd_resource(psurf->texture);
  79
  80         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  81         OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
  82         OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) |
  83                         RB_COLOR_INFO_COLOR_BASE(base / 1024) |
  84                         RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format)));
  85
  86         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
  87         OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
  88         OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
  89         OUT_RELOC(ring, rsc->bo, 0, 0);         /* RB_COPY_DEST_BASE */
  90         OUT_RING(ring, rsc->pitch >> 5);        /* RB_COPY_DEST_PITCH */
  91         OUT_RING(ring, RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) |
  92                         RB_COPY_DEST_INFO_LINEAR |      /* RB_COPY_DEST_INFO */
  93                         RB_COPY_DEST_INFO_SWAP(swap) |
  94                         RB_COPY_DEST_INFO_WRITE_RED |
  95                         RB_COPY_DEST_INFO_WRITE_GREEN |
  96                         RB_COPY_DEST_INFO_WRITE_BLUE |
  97                         RB_COPY_DEST_INFO_WRITE_ALPHA);
  98
  99         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 100         OUT_RING(ring, 0x0000000);
 101
 102         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 103         OUT_RING(ring, 0x00000000);
 104         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
 105                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 106         OUT_RING(ring, 3);                                      /* NumIndices */
 107 }
 108
 109 static void
 110 emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring,
 111                 uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
 112 {
 113         struct fd_framebuffer_stateobj *fb = &ctx->framebuffer;
 114         struct pipe_framebuffer_state *pfb = &fb->base;
 115
 116         fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
 117                         { .prsc = ctx->solid_vertexbuf, .size = 48 },
 118                 }, 1);
 119
 120         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 121         OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
 122         OUT_RING(ring, 0);
 123
 124         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 125         OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
 126         OUT_RING(ring, 0x0000028f);
 127
 128         fd_program_emit(ring, &ctx->solid_prog);
 129
 130         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 131         OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
 132         OUT_RING(ring, 0x0000ffff);
 133
 134         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 135         OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
 136         OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 137
 138         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 139         OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL));
 140         OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 141                         PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
 142                         PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
 143
 144         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 145         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
 146         OUT_RING(ring, xy2d(0, 0));                       /* PA_SC_WINDOW_SCISSOR_TL */
 147         OUT_RING(ring, xy2d(pfb->width, pfb->height));    /* PA_SC_WINDOW_SCISSOR_BR */
 148
 149         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 150         OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
 151         OUT_RING(ring, PA_CL_VTE_CNTL_VTX_W0_FMT |
 152                         PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 153                         PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 154                         PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 155                         PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 156
 157         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 158         OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
 159         OUT_RING(ring, 0x00000000);
 160
 161         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 162         OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
 163         OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
 164
 165         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 166         OUT_RING(ring, CP_REG(REG_RB_COPY_DEST_OFFSET));
 167         OUT_RING(ring, RB_COPY_DEST_OFFSET_X(xoff) | RB_COPY_DEST_OFFSET_Y(yoff));
 168
 169         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 170                 emit_gmem2mem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
 171
 172         if (ctx->resolve & FD_BUFFER_COLOR)
 173                 emit_gmem2mem_surf(ring, 1, 0, pfb->cbufs[0]);
 174
 175         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 176         OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
 177         OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 178 }
 179
 180 /* transfer from system memory to gmem */
 181
 182 static void
 183 emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
 184                 struct pipe_surface *psurf)
 185 {
 186         struct fd_resource *rsc = fd_resource(psurf->texture);
 187         uint32_t swiz;
 188
 189         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 190         OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
 191         OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) |
 192                         RB_COLOR_INFO_COLOR_BASE(base / 1024) |
 193                         RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format)));
 194
 195         swiz = fd_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
 196                         PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA);
 197
 198         /* emit fb as a texture: */
 199         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 200         OUT_RING(ring, 0x00010000);
 201         OUT_RING(ring, SQ_TEX0_CLAMP_X(SQ_TEX_WRAP) |
 202                         SQ_TEX0_CLAMP_Y(SQ_TEX_WRAP) |
 203                         SQ_TEX0_CLAMP_Z(SQ_TEX_WRAP) |
 204                         SQ_TEX0_PITCH(rsc->pitch));
 205         OUT_RELOC(ring, rsc->bo, 0,
 206                         fd_pipe2surface(psurf->format) | 0x800);
 207         OUT_RING(ring, SQ_TEX2_WIDTH(psurf->width) |
 208                         SQ_TEX2_HEIGHT(psurf->height));
 209         OUT_RING(ring, 0x01000000 | // XXX
 210                         swiz |
 211                         SQ_TEX3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
 212                         SQ_TEX3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
 213         OUT_RING(ring, 0x00000000);
 214         OUT_RING(ring, 0x00000200);
 215
 216         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 217         OUT_RING(ring, 0x00000000);
 218         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
 219                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 220         OUT_RING(ring, 3);                                      /* NumIndices */
 221 }
 222
 223 static void
 224 emit_mem2gmem(struct fd_context *ctx, struct fd_ringbuffer *ring,
 225                 uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
 226 {
 227         struct fd_framebuffer_stateobj *fb = &ctx->framebuffer;
 228         struct pipe_framebuffer_state *pfb = &fb->base;
 229         float x0, y0, x1, y1;
 230
 231         fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
 232                         { .prsc = ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
 233                         { .prsc = ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
 234                 }, 2);
 235
 236         /* write texture coordinates to vertexbuf: */
 237         x0 = ((float)xoff) / ((float)pfb->width);
 238         x1 = ((float)xoff + bin_w) / ((float)pfb->width);
 239         y0 = ((float)yoff) / ((float)pfb->height);
 240         y1 = ((float)yoff + bin_h) / ((float)pfb->height);
 241         OUT_PKT3(ring, CP_MEM_WRITE, 9);
 242         OUT_RELOC(ring, fd_resource(ctx->solid_vertexbuf)->bo, 0x60, 0);
 243         OUT_RING(ring, f2d(x0));
 244         OUT_RING(ring, f2d(y0));
 245         OUT_RING(ring, f2d(x1));
 246         OUT_RING(ring, f2d(y0));
 247         OUT_RING(ring, f2d(x0));
 248         OUT_RING(ring, f2d(y1));
 249         OUT_RING(ring, f2d(x1));
 250         OUT_RING(ring, f2d(y1));
 251
 252         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 253         OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
 254         OUT_RING(ring, 0);
 255
 256         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 257         OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
 258         OUT_RING(ring, 0x0000003b);
 259
 260         fd_program_emit(ring, &ctx->blit_prog);
 261
 262         OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1);
 263         OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE);
 264
 265         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 266         OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
 267         OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 268
 269         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 270         OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL));
 271         OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
 272                         PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
 273                         PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
 274
 275         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 276         OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
 277         OUT_RING(ring, 0x0000ffff);
 278
 279         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 280         OUT_RING(ring, CP_REG(REG_RB_COLORCONTROL));
 281         OUT_RING(ring, RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
 282                         RB_COLORCONTROL_BLEND_DISABLE |
 283                         RB_COLORCONTROL_ROP_CODE(12) |
 284                         RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 285                         RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 286
 287         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 288         OUT_RING(ring, CP_REG(REG_RB_BLEND_CONTROL));
 289         OUT_RING(ring, RB_BLENDCONTROL_COLOR_SRCBLEND(RB_BLEND_ONE) |
 290                         RB_BLENDCONTROL_COLOR_COMB_FCN(COMB_DST_PLUS_SRC) |
 291                         RB_BLENDCONTROL_COLOR_DESTBLEND(RB_BLEND_ZERO) |
 292                         RB_BLENDCONTROL_ALPHA_SRCBLEND(RB_BLEND_ONE) |
 293                         RB_BLENDCONTROL_ALPHA_COMB_FCN(COMB_DST_PLUS_SRC) |
 294                         RB_BLENDCONTROL_ALPHA_DESTBLEND(RB_BLEND_ZERO));
 295
 296         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 297         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
 298         OUT_RING(ring, PA_SC_WINDOW_OFFSET_DISABLE |
 299                         xy2d(0,0));                     /* PA_SC_WINDOW_SCISSOR_TL */
 300         OUT_RING(ring, xy2d(bin_w, bin_h));     /* PA_SC_WINDOW_SCISSOR_BR */
 301
 302         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 303         OUT_RING(ring, CP_REG(REG_PA_CL_VPORT_XSCALE));
 304         OUT_RING(ring, f2d((float)bin_w/2.0));  /* PA_CL_VPORT_XSCALE */
 305         OUT_RING(ring, f2d((float)bin_w/2.0));  /* PA_CL_VPORT_XOFFSET */
 306         OUT_RING(ring, f2d(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
 307         OUT_RING(ring, f2d((float)bin_h/2.0));  /* PA_CL_VPORT_YOFFSET */
 308
 309         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 310         OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
 311         OUT_RING(ring, PA_CL_VTE_CNTL_VTX_XY_FMT |
 312                         PA_CL_VTE_CNTL_VTX_Z_FMT |       // XXX check this???
 313                         PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 314                         PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 315                         PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 316                         PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 317
 318         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 319         OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
 320         OUT_RING(ring, 0x00000000);
 321
 322         if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 323                 emit_mem2gmem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
 324
 325         if (ctx->resolve & FD_BUFFER_COLOR)
 326                 emit_mem2gmem_surf(ring, 1, 0, pfb->cbufs[0]);
 327
 328         /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
 329 }
 330
 331 void
 332 fd_gmem_render_tiles(struct pipe_context *pctx)
 333 {
 334         struct fd_context *ctx = fd_context(pctx);
 335         struct fd_framebuffer_stateobj *fb = &ctx->framebuffer;
 336         struct pipe_framebuffer_state *pfb = &fb->base;
 337         struct fd_ringbuffer *ring;
 338         uint32_t i, yoff = 0;
 339         uint32_t timestamp;
 340         ring = ctx->ring;
 341
 342         DBG("rendering %dx%d tiles (%s/%s)", fb->nbins_x, fb->nbins_y,
 343                         util_format_name(pfb->cbufs[0]->format),
 344                         pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
 345
 346         /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
 347         fd_ringmarker_mark(ctx->draw_end);
 348
 349         for (i = 0; i < fb->nbins_y; i++) {
 350                 uint32_t j, xoff = 0;
 351                 uint32_t bin_h = fb->bin_h;
 352
 353                 /* clip bin height: */
 354                 bin_h = min(bin_h, pfb->height - yoff);
 355
 356                 for (j = 0; j < fb->nbins_x; j++) {
 357                         uint32_t bin_w = fb->bin_w;
 358
 359                         /* clip bin width: */
 360                         bin_w = min(bin_w, pfb->width - xoff);
 361
 362                         DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 363                                         bin_h, yoff, bin_w, xoff);
 364
 365                         fd_emit_framebuffer_state(ring, &ctx->framebuffer);
 366
 367                         /* setup screen scissor for current tile (same for mem2gmem): */
 368                         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 369                         OUT_RING(ring, CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL));
 370                         OUT_RING(ring, xy2d(0,0));           /* PA_SC_SCREEN_SCISSOR_TL */
 371                         OUT_RING(ring, xy2d(bin_w, bin_h));  /* PA_SC_SCREEN_SCISSOR_BR */
 372
 373                         if (ctx->restore)
 374                                 emit_mem2gmem(ctx, ring, xoff, yoff, bin_w, bin_h);
 375
 376                         /* setup window scissor and offset for current tile (different
 377                          * from mem2gmem):
 378                          */
 379                         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 380                         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
 381                         OUT_RING(ring, PA_SC_WINDOW_OFFSET_X(-xoff) |
 382                                         PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */
 383
 384                         /* emit IB to drawcmds: */
 385                         OUT_IB  (ring, ctx->draw_start, ctx->draw_end);
 386
 387                         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 388                         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
 389                         OUT_RING(ring, 0x00000000);          /* PA_SC_WINDOW_OFFSET */
 390
 391                         /* emit gmem2mem to transfer tile back to system memory: */
 392                         emit_gmem2mem(ctx, ring, xoff, yoff, bin_w, bin_h);
 393
 394                         xoff += bin_w;
 395                 }
 396
 397                 yoff += bin_h;
 398         }
 399
 400         /* GPU executes starting from tile cmds, which IB back to draw cmds: */
 401         fd_ringmarker_flush(ctx->draw_end);
 402
 403         /* mark start for next draw cmds: */
 404         fd_ringmarker_mark(ctx->draw_start);
 405
 406         /* update timestamps on render targets: */
 407         fd_pipe_timestamp(ctx->screen->pipe, &timestamp);
 408         fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
 409         if (pfb->zsbuf)
 410                 fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
 411
 412         /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
 413          * after the draw/clear calls, but executed before, we need to preemptively
 414          * flag some state as dirty before the first draw/clear call.
 415          *
 416          * TODO maybe we need to mark all state as dirty to not worry about state
 417          * being clobbered by other contexts?
 418          */
 419         ctx->dirty |= FD_DIRTY_ZSA |
 420                         FD_DIRTY_RASTERIZER |
 421                         FD_DIRTY_FRAMEBUFFER |
 422                         FD_DIRTY_SAMPLE_MASK |
 423                         FD_DIRTY_VIEWPORT |
 424                         FD_DIRTY_CONSTBUF |
 425                         FD_DIRTY_PROG |
 426                         FD_DIRTY_SCISSOR |
 427                         /* probably only needed if we need to mem2gmem on the next
 428                          * draw..  but not sure if there is a good way to know?
 429                          */
 430                         FD_DIRTY_VERTTEX |
 431                         FD_DIRTY_FRAGTEX |
 432                         FD_DIRTY_BLEND;
 433 }
 434
 435 void
 436 fd_gmem_calculate_tiles(struct pipe_context *pctx)
 437 {
 438         struct fd_context *ctx = fd_context(pctx);
 439         struct fd_framebuffer_stateobj *fb = &ctx->framebuffer;
 440         struct pipe_framebuffer_state *pfb = &fb->base;
 441         uint32_t nbins_x = 1, nbins_y = 1;
 442         uint32_t bin_w, bin_h;
 443         uint32_t cpp = util_format_get_blocksize(pfb->cbufs[0]->format);
 444         uint32_t gmem_size = ctx->screen->gmemsize_bytes;
 445         uint32_t max_width = 992;
 446
 447 // TODO we probably could optimize this a bit if we know that
 448 // Z or stencil is not enabled for any of the draw calls..
 449 //      if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
 450                 gmem_size /= 2;
 451                 max_width = 256;
 452 //      }
 453
 454         bin_w = ALIGN(pfb->width, 32);
 455         bin_h = ALIGN(pfb->height, 32);
 456
 457         /* first, find a bin width that satisfies the maximum width
 458          * restrictions:
 459          */
 460         while (bin_w > max_width) {
 461                 nbins_x++;
 462                 bin_w = ALIGN(pfb->width / nbins_x, 32);
 463         }
 464
 465         /* then find a bin height that satisfies the memory constraints:
 466          */
 467         while ((bin_w * bin_h * cpp) > gmem_size) {
 468                 nbins_y++;
 469                 bin_h = ALIGN(pfb->height / nbins_y, 32);
 470         }
 471
 472         if ((nbins_x > 1) || (nbins_y > 1)) {
 473                 fb->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE;
 474         } else {
 475                 fb->pa_su_sc_mode_cntl &= ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE;
 476         }
 477
 478         DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
 479
 480 //if we use hw binning, tile sizes (in multiple of 32) need to
 481 //fit in 5 bits.. for now don't care because we aren't using
 482 //that:
 483 //      assert(!(bin_h/32 & ~0x1f));
 484 //      assert(!(bin_w/32 & ~0x1f));
 485
 486         fb->nbins_x = nbins_x;
 487         fb->nbins_y = nbins_y;
 488         fb->bin_w = bin_w;
 489         fb->bin_h = bin_h;
 490
 491 }