1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_pack_color.h"
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_state.h"
38 #include "freedreno_program.h"
39 #include "freedreno_resource.h"
40 #include "freedreno_zsa.h"
41 #include "freedreno_util.h"
44 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
45 * inside the GPU. All rendering happens to GMEM. Larger render targets
46 * are split into tiles that are small enough for the color (and depth and/or
47 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
48 * if there was not a clear invalidating the previous tile contents, we need
49 * to restore the previous tiles contents (system mem -> GMEM), and after all
50 * the draw calls, before moving to the next tile, we need to save the tile
51 * contents (GMEM -> system mem).
53 * The code in this file handles dealing with GMEM and tiling.
55 * The structure of the ringbuffer ends up being:
57 * +--<---<-- IB ---<---+---<---+---<---<---<--+
60 * ------------------------------------------------------
61 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
62 * ------------------------------------------------------
65 * address submitted in issueibcmds
67 * Where the per-tile section handles scissor setup, mem2gmem restore (if
68 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
72 static uint32_t fmt2swap(enum pipe_format format
)
75 case PIPE_FORMAT_B8G8R8A8_UNORM
:
76 /* TODO probably some more.. */
83 /* transfer from gmem to system memory (ie. normal RAM) */
86 emit_gmem2mem_surf(struct fd_ringbuffer
*ring
, uint32_t base
,
87 struct pipe_surface
*psurf
)
89 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
90 uint32_t swap
= fmt2swap(psurf
->format
);
92 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
93 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_INFO
));
94 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(swap
) |
95 A2XX_RB_COLOR_INFO_BASE(base
/ 1024) |
96 A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf
->format
)));
98 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
99 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_CONTROL
));
100 OUT_RING(ring
, 0x00000000); /* RB_COPY_CONTROL */
101 OUT_RELOC(ring
, rsc
->bo
, 0, 0); /* RB_COPY_DEST_BASE */
102 OUT_RING(ring
, rsc
->pitch
>> 5); /* RB_COPY_DEST_PITCH */
103 OUT_RING(ring
, /* RB_COPY_DEST_INFO */
104 A2XX_RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf
->format
)) |
105 A2XX_RB_COPY_DEST_INFO_LINEAR
|
106 A2XX_RB_COPY_DEST_INFO_SWAP(swap
) |
107 A2XX_RB_COPY_DEST_INFO_WRITE_RED
|
108 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN
|
109 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE
|
110 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA
);
112 OUT_PKT3(ring
, CP_WAIT_FOR_IDLE
, 1);
113 OUT_RING(ring
, 0x0000000);
115 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
116 OUT_RING(ring
, 0x00000000);
117 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_AUTO_INDEX
,
118 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
119 OUT_RING(ring
, 3); /* NumIndices */
123 emit_gmem2mem(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
124 uint32_t xoff
, uint32_t yoff
, uint32_t bin_w
, uint32_t bin_h
)
126 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
128 fd_emit_vertex_bufs(ring
, 0x9c, (struct fd_vertex_buf
[]) {
129 { .prsc
= ctx
->solid_vertexbuf
, .size
= 48 },
132 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
133 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
136 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
137 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
138 OUT_RING(ring
, 0x0000028f);
140 fd_program_emit(ring
, &ctx
->solid_prog
);
142 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
143 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
144 OUT_RING(ring
, 0x0000ffff);
146 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
147 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
148 OUT_RING(ring
, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE
);
150 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
151 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL
));
152 OUT_RING(ring
, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST
| /* PA_SU_SC_MODE_CNTL */
153 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
154 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES
));
156 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
157 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
158 OUT_RING(ring
, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */
159 OUT_RING(ring
, xy2d(pfb
->width
, pfb
->height
)); /* PA_SC_WINDOW_SCISSOR_BR */
161 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
162 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
163 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT
|
164 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
165 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
166 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
167 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
);
169 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
170 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
171 OUT_RING(ring
, 0x00000000);
173 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
174 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
175 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY
));
177 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
178 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET
));
179 OUT_RING(ring
, A2XX_RB_COPY_DEST_OFFSET_X(xoff
) |
180 A2XX_RB_COPY_DEST_OFFSET_Y(yoff
));
182 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
))
183 emit_gmem2mem_surf(ring
, bin_w
* bin_h
, pfb
->zsbuf
);
185 if (ctx
->resolve
& FD_BUFFER_COLOR
)
186 emit_gmem2mem_surf(ring
, 0, pfb
->cbufs
[0]);
188 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
189 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
190 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH
));
193 /* transfer from system memory to gmem */
196 emit_mem2gmem_surf(struct fd_ringbuffer
*ring
, uint32_t base
,
197 struct pipe_surface
*psurf
)
199 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
202 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
203 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_INFO
));
204 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf
->format
)) |
205 A2XX_RB_COLOR_INFO_BASE(base
) |
206 A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf
->format
)));
208 swiz
= fd_tex_swiz(psurf
->format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
209 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
);
211 /* emit fb as a texture: */
212 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
213 OUT_RING(ring
, 0x00010000);
214 OUT_RING(ring
, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP
) |
215 A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP
) |
216 A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP
) |
217 A2XX_SQ_TEX_0_PITCH(rsc
->pitch
));
218 OUT_RELOC(ring
, rsc
->bo
, 0,
219 fd_pipe2surface(psurf
->format
) | 0x800);
220 OUT_RING(ring
, A2XX_SQ_TEX_2_WIDTH(psurf
->width
- 1) |
221 A2XX_SQ_TEX_2_HEIGHT(psurf
->height
- 1));
222 OUT_RING(ring
, 0x01000000 | // XXX
224 A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT
) |
225 A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT
));
226 OUT_RING(ring
, 0x00000000);
227 OUT_RING(ring
, 0x00000200);
229 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
230 OUT_RING(ring
, 0x00000000);
231 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_AUTO_INDEX
,
232 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
233 OUT_RING(ring
, 3); /* NumIndices */
237 emit_mem2gmem(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
238 uint32_t xoff
, uint32_t yoff
, uint32_t bin_w
, uint32_t bin_h
)
240 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
241 float x0
, y0
, x1
, y1
;
243 fd_emit_vertex_bufs(ring
, 0x9c, (struct fd_vertex_buf
[]) {
244 { .prsc
= ctx
->solid_vertexbuf
, .size
= 48, .offset
= 0x30 },
245 { .prsc
= ctx
->solid_vertexbuf
, .size
= 32, .offset
= 0x60 },
248 /* write texture coordinates to vertexbuf: */
249 x0
= ((float)xoff
) / ((float)pfb
->width
);
250 x1
= ((float)xoff
+ bin_w
) / ((float)pfb
->width
);
251 y0
= ((float)yoff
) / ((float)pfb
->height
);
252 y1
= ((float)yoff
+ bin_h
) / ((float)pfb
->height
);
253 OUT_PKT3(ring
, CP_MEM_WRITE
, 9);
254 OUT_RELOC(ring
, fd_resource(ctx
->solid_vertexbuf
)->bo
, 0x60, 0);
255 OUT_RING(ring
, fui(x0
));
256 OUT_RING(ring
, fui(y0
));
257 OUT_RING(ring
, fui(x1
));
258 OUT_RING(ring
, fui(y0
));
259 OUT_RING(ring
, fui(x0
));
260 OUT_RING(ring
, fui(y1
));
261 OUT_RING(ring
, fui(x1
));
262 OUT_RING(ring
, fui(y1
));
264 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
265 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
268 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
269 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
270 OUT_RING(ring
, 0x0000003b);
272 fd_program_emit(ring
, &ctx
->blit_prog
);
274 OUT_PKT0(ring
, REG_A2XX_TC_CNTL_STATUS
, 1);
275 OUT_RING(ring
, A2XX_TC_CNTL_STATUS_L2_INVALIDATE
);
277 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
278 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
279 OUT_RING(ring
, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE
);
281 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
282 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL
));
283 OUT_RING(ring
, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST
|
284 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
285 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES
));
287 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
288 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
289 OUT_RING(ring
, 0x0000ffff);
291 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
292 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLORCONTROL
));
293 OUT_RING(ring
, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS
) |
294 A2XX_RB_COLORCONTROL_BLEND_DISABLE
|
295 A2XX_RB_COLORCONTROL_ROP_CODE(12) |
296 A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE
) |
297 A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL
));
299 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
300 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_CONTROL
));
301 OUT_RING(ring
, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE
) |
302 A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC
) |
303 A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO
) |
304 A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE
) |
305 A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC
) |
306 A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO
));
308 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
309 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
310 OUT_RING(ring
, A2XX_PA_SC_WINDOW_OFFSET_DISABLE
|
311 xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
312 OUT_RING(ring
, xy2d(bin_w
, bin_h
)); /* PA_SC_WINDOW_SCISSOR_BR */
314 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
315 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE
));
316 OUT_RING(ring
, fui((float)bin_w
/2.0)); /* PA_CL_VPORT_XSCALE */
317 OUT_RING(ring
, fui((float)bin_w
/2.0)); /* PA_CL_VPORT_XOFFSET */
318 OUT_RING(ring
, fui(-(float)bin_h
/2.0)); /* PA_CL_VPORT_YSCALE */
319 OUT_RING(ring
, fui((float)bin_h
/2.0)); /* PA_CL_VPORT_YOFFSET */
321 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
322 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
323 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT
|
324 A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT
| // XXX check this???
325 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
326 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
327 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
328 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
);
330 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
331 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
332 OUT_RING(ring
, 0x00000000);
334 if (ctx
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
))
335 emit_mem2gmem_surf(ring
, bin_w
* bin_h
, pfb
->zsbuf
);
337 if (ctx
->restore
& FD_BUFFER_COLOR
)
338 emit_mem2gmem_surf(ring
, 0, pfb
->cbufs
[0]);
340 /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
344 calculate_tiles(struct fd_context
*ctx
)
346 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
347 struct pipe_scissor_state
*scissor
= &ctx
->max_scissor
;
348 uint32_t cpp
= util_format_get_blocksize(ctx
->framebuffer
.cbufs
[0]->format
);
349 uint32_t gmem_size
= ctx
->screen
->gmemsize_bytes
;
350 uint32_t minx
, miny
, width
, height
;
351 uint32_t nbins_x
= 1, nbins_y
= 1;
352 uint32_t bin_w
, bin_h
;
353 uint32_t max_width
= 992;
355 if ((gmem
->cpp
== cpp
) &&
356 !memcmp(&gmem
->scissor
, scissor
, sizeof(gmem
->scissor
))) {
357 /* everything is up-to-date */
361 minx
= scissor
->minx
& ~31; /* round down to multiple of 32 */
362 miny
= scissor
->miny
& ~31;
363 width
= scissor
->maxx
- minx
;
364 height
= scissor
->maxy
- miny
;
366 // TODO we probably could optimize this a bit if we know that
367 // Z or stencil is not enabled for any of the draw calls..
368 // if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
373 bin_w
= ALIGN(width
, 32);
374 bin_h
= ALIGN(height
, 32);
376 /* first, find a bin width that satisfies the maximum width
379 while (bin_w
> max_width
) {
381 bin_w
= ALIGN(width
/ nbins_x
, 32);
384 /* then find a bin height that satisfies the memory constraints:
386 while ((bin_w
* bin_h
* cpp
) > gmem_size
) {
388 bin_h
= ALIGN(height
/ nbins_y
, 32);
391 DBG("using %d bins of size %dx%d", nbins_x
*nbins_y
, bin_w
, bin_h
);
393 gmem
->scissor
= *scissor
;
399 gmem
->nbins_x
= nbins_x
;
400 gmem
->nbins_y
= nbins_y
;
402 gmem
->height
= height
;
406 fd_gmem_render_tiles(struct pipe_context
*pctx
)
408 struct fd_context
*ctx
= fd_context(pctx
);
409 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
410 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
411 struct fd_ringbuffer
*ring
= ctx
->ring
;
412 enum a2xx_colorformatx colorformatx
= fd_pipe2color(pfb
->cbufs
[0]->format
);
413 uint32_t i
, timestamp
, yoff
= 0;
416 calculate_tiles(ctx
);
418 DBG("rendering %dx%d tiles (%s/%s)", gmem
->nbins_x
, gmem
->nbins_y
,
419 util_format_name(pfb
->cbufs
[0]->format
),
420 pfb
->zsbuf
? util_format_name(pfb
->zsbuf
->format
) : "none");
422 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
423 fd_ringmarker_mark(ctx
->draw_end
);
425 /* RB_SURFACE_INFO / RB_DEPTH_INFO can be emitted once per tile pass,
426 * but RB_COLOR_INFO gets overwritten by gmem2mem and mem2gmem and so
427 * needs to be emitted for each tile:
429 OUT_PKT3(ring
, CP_SET_CONSTANT
, 4);
430 OUT_RING(ring
, CP_REG(REG_A2XX_RB_SURFACE_INFO
));
431 OUT_RING(ring
, gmem
->bin_w
); /* RB_SURFACE_INFO */
432 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
433 A2XX_RB_COLOR_INFO_FORMAT(colorformatx
));
434 reg
= A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem
->bin_w
* gmem
->bin_h
, 4));
436 reg
|= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb
->zsbuf
->format
));
437 OUT_RING(ring
, reg
); /* RB_DEPTH_INFO */
440 for (i
= 0; i
< gmem
->nbins_y
; i
++) {
441 uint32_t j
, xoff
= gmem
->minx
;
442 uint32_t bh
= gmem
->bin_h
;
444 /* clip bin height: */
445 bh
= min(bh
, gmem
->height
- yoff
);
447 for (j
= 0; j
< gmem
->nbins_x
; j
++) {
448 uint32_t bw
= gmem
->bin_w
;
450 /* clip bin width: */
451 bw
= min(bw
, gmem
->width
- xoff
);
453 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
456 /* setup screen scissor for current tile (same for mem2gmem): */
457 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
458 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL
));
459 OUT_RING(ring
, xy2d(0,0)); /* PA_SC_SCREEN_SCISSOR_TL */
460 OUT_RING(ring
, xy2d(bw
, bh
)); /* PA_SC_SCREEN_SCISSOR_BR */
463 emit_mem2gmem(ctx
, ring
, xoff
, yoff
, bw
, bh
);
465 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
466 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_INFO
));
467 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
468 A2XX_RB_COLOR_INFO_FORMAT(colorformatx
));
470 /* setup window scissor and offset for current tile (different
473 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
474 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
475 OUT_RING(ring
, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff
) |
476 A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff
));/* PA_SC_WINDOW_OFFSET */
478 /* emit IB to drawcmds: */
479 OUT_IB (ring
, ctx
->draw_start
, ctx
->draw_end
);
481 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
482 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
483 OUT_RING(ring
, 0x00000000); /* PA_SC_WINDOW_OFFSET */
485 /* emit gmem2mem to transfer tile back to system memory: */
486 emit_gmem2mem(ctx
, ring
, xoff
, yoff
, bw
, bh
);
494 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
495 fd_ringmarker_flush(ctx
->draw_end
);
497 /* mark start for next draw cmds: */
498 fd_ringmarker_mark(ctx
->draw_start
);
500 /* update timestamps on render targets: */
501 fd_pipe_timestamp(ctx
->screen
->pipe
, ×tamp
);
502 fd_resource(pfb
->cbufs
[0]->texture
)->timestamp
= timestamp
;
504 fd_resource(pfb
->zsbuf
->texture
)->timestamp
= timestamp
;
506 /* reset maximal bounds: */
507 ctx
->max_scissor
.minx
= ctx
->max_scissor
.miny
= ~0;
508 ctx
->max_scissor
.maxx
= ctx
->max_scissor
.maxy
= 0;
510 /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
511 * after the draw/clear calls, but executed before, we need to preemptively
512 * flag some state as dirty before the first draw/clear call.
514 * TODO maybe we need to mark all state as dirty to not worry about state
515 * being clobbered by other contexts?
517 ctx
->dirty
|= FD_DIRTY_ZSA
|
518 FD_DIRTY_RASTERIZER
|
519 FD_DIRTY_FRAMEBUFFER
|
520 FD_DIRTY_SAMPLE_MASK
|
525 /* probably only needed if we need to mem2gmem on the next
526 * draw.. but not sure if there is a good way to know?