2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_format.h"
28 #include "util/u_format_rgtc.h"
29 #include "util/u_format_zs.h"
30 #include "util/u_inlines.h"
31 #include "util/u_transfer.h"
32 #include "util/u_string.h"
33 #include "util/u_surface.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_batch_cache.h"
38 #include "freedreno_screen.h"
39 #include "freedreno_surface.h"
40 #include "freedreno_context.h"
41 #include "freedreno_query_hw.h"
42 #include "freedreno_util.h"
46 /* XXX this should go away, needed for 'struct winsys_handle' */
47 #include "state_tracker/drm_driver.h"
50 * Go through the entire state and see if the resource is bound
51 * anywhere. If it is, mark the relevant state as dirty. This is
52 * called on realloc_bo to ensure the neccessary state is re-
53 * emitted so the GPU looks at the new backing bo.
56 rebind_resource(struct fd_context
*ctx
, struct pipe_resource
*prsc
)
59 for (unsigned i
= 0; i
< ctx
->vtx
.vertexbuf
.count
&& !(ctx
->dirty
& FD_DIRTY_VTXBUF
); i
++) {
60 if (ctx
->vtx
.vertexbuf
.vb
[i
].buffer
.resource
== prsc
)
61 ctx
->dirty
|= FD_DIRTY_VTXBUF
;
64 /* per-shader-stage resources: */
65 for (unsigned stage
= 0; stage
< PIPE_SHADER_TYPES
; stage
++) {
66 /* Constbufs.. note that constbuf[0] is normal uniforms emitted in
67 * cmdstream rather than by pointer..
69 const unsigned num_ubos
= util_last_bit(ctx
->constbuf
[stage
].enabled_mask
);
70 for (unsigned i
= 1; i
< num_ubos
; i
++) {
71 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_CONST
)
73 if (ctx
->constbuf
[stage
].cb
[i
].buffer
== prsc
)
74 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_CONST
;
78 for (unsigned i
= 0; i
< ctx
->tex
[stage
].num_textures
; i
++) {
79 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_TEX
)
81 if (ctx
->tex
[stage
].textures
[i
] && (ctx
->tex
[stage
].textures
[i
]->texture
== prsc
))
82 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_TEX
;
86 const unsigned num_ssbos
= util_last_bit(ctx
->shaderbuf
[stage
].enabled_mask
);
87 for (unsigned i
= 0; i
< num_ssbos
; i
++) {
88 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_SSBO
)
90 if (ctx
->shaderbuf
[stage
].sb
[i
].buffer
== prsc
)
91 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_SSBO
;
97 realloc_bo(struct fd_resource
*rsc
, uint32_t size
)
99 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
100 uint32_t flags
= DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
101 DRM_FREEDRENO_GEM_TYPE_KMEM
; /* TODO */
103 /* if we start using things other than write-combine,
104 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
110 rsc
->bo
= fd_bo_new(screen
->dev
, size
, flags
);
111 util_range_set_empty(&rsc
->valid_buffer_range
);
112 fd_bc_invalidate_resource(rsc
, true);
116 do_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*blit
, bool fallback
)
118 /* TODO size threshold too?? */
120 /* do blit on gpu: */
121 fd_blitter_pipe_begin(ctx
, false, true, FD_STAGE_BLIT
);
122 ctx
->blit(ctx
, blit
);
123 fd_blitter_pipe_end(ctx
);
125 /* do blit on cpu: */
126 util_resource_copy_region(&ctx
->base
,
127 blit
->dst
.resource
, blit
->dst
.level
, blit
->dst
.box
.x
,
128 blit
->dst
.box
.y
, blit
->dst
.box
.z
,
129 blit
->src
.resource
, blit
->src
.level
, &blit
->src
.box
);
134 fd_try_shadow_resource(struct fd_context
*ctx
, struct fd_resource
*rsc
,
135 unsigned level
, const struct pipe_box
*box
)
137 struct pipe_context
*pctx
= &ctx
->base
;
138 struct pipe_resource
*prsc
= &rsc
->base
;
139 bool fallback
= false;
144 /* TODO: somehow munge dimensions and format to copy unsupported
145 * render target format to something that is supported?
147 if (!pctx
->screen
->is_format_supported(pctx
->screen
,
148 prsc
->format
, prsc
->target
, prsc
->nr_samples
,
149 prsc
->nr_storage_samples
,
150 PIPE_BIND_RENDER_TARGET
))
153 /* do shadowing back-blits on the cpu for buffers: */
154 if (prsc
->target
== PIPE_BUFFER
)
157 bool whole_level
= util_texrange_covers_whole_level(prsc
, level
,
158 box
->x
, box
->y
, box
->z
, box
->width
, box
->height
, box
->depth
);
160 /* TODO need to be more clever about current level */
161 if ((prsc
->target
>= PIPE_TEXTURE_2D
) && !whole_level
)
164 struct pipe_resource
*pshadow
=
165 pctx
->screen
->resource_create(pctx
->screen
, prsc
);
170 assert(!ctx
->in_shadow
);
171 ctx
->in_shadow
= true;
173 /* get rid of any references that batch-cache might have to us (which
174 * should empty/destroy rsc->batches hashset)
176 fd_bc_invalidate_resource(rsc
, false);
178 mtx_lock(&ctx
->screen
->lock
);
180 /* Swap the backing bo's, so shadow becomes the old buffer,
181 * blit from shadow to new buffer. From here on out, we
184 * Note that we need to do it in this order, otherwise if
185 * we go down cpu blit path, the recursive transfer_map()
186 * sees the wrong status..
188 struct fd_resource
*shadow
= fd_resource(pshadow
);
190 DBG("shadow: %p (%d) -> %p (%d)\n", rsc
, rsc
->base
.reference
.count
,
191 shadow
, shadow
->base
.reference
.count
);
193 /* TODO valid_buffer_range?? */
194 swap(rsc
->bo
, shadow
->bo
);
195 swap(rsc
->write_batch
, shadow
->write_batch
);
197 /* at this point, the newly created shadow buffer is not referenced
198 * by any batches, but the existing rsc (probably) is. We need to
199 * transfer those references over:
201 debug_assert(shadow
->batch_mask
== 0);
202 struct fd_batch
*batch
;
203 foreach_batch(batch
, &ctx
->screen
->batch_cache
, rsc
->batch_mask
) {
204 struct set_entry
*entry
= _mesa_set_search(batch
->resources
, rsc
);
205 _mesa_set_remove(batch
->resources
, entry
);
206 _mesa_set_add(batch
->resources
, shadow
);
208 swap(rsc
->batch_mask
, shadow
->batch_mask
);
210 mtx_unlock(&ctx
->screen
->lock
);
212 struct pipe_blit_info blit
= {};
213 blit
.dst
.resource
= prsc
;
214 blit
.dst
.format
= prsc
->format
;
215 blit
.src
.resource
= pshadow
;
216 blit
.src
.format
= pshadow
->format
;
217 blit
.mask
= util_format_get_mask(prsc
->format
);
218 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
220 #define set_box(field, val) do { \
221 blit.dst.field = (val); \
222 blit.src.field = (val); \
225 /* blit the other levels in their entirety: */
226 for (unsigned l
= 0; l
<= prsc
->last_level
; l
++) {
230 /* just blit whole level: */
232 set_box(box
.width
, u_minify(prsc
->width0
, l
));
233 set_box(box
.height
, u_minify(prsc
->height0
, l
));
234 set_box(box
.depth
, u_minify(prsc
->depth0
, l
));
236 do_blit(ctx
, &blit
, fallback
);
239 /* deal w/ current level specially, since we might need to split
240 * it up into a couple blits:
243 set_box(level
, level
);
245 switch (prsc
->target
) {
247 case PIPE_TEXTURE_1D
:
250 set_box(box
.height
, 1);
251 set_box(box
.depth
, 1);
255 set_box(box
.width
, box
->x
);
257 do_blit(ctx
, &blit
, fallback
);
259 if ((box
->x
+ box
->width
) < u_minify(prsc
->width0
, level
)) {
260 set_box(box
.x
, box
->x
+ box
->width
);
261 set_box(box
.width
, u_minify(prsc
->width0
, level
) - (box
->x
+ box
->width
));
263 do_blit(ctx
, &blit
, fallback
);
266 case PIPE_TEXTURE_2D
:
273 ctx
->in_shadow
= false;
275 pipe_resource_reference(&pshadow
, NULL
);
280 static struct fd_resource
*
281 fd_alloc_staging(struct fd_context
*ctx
, struct fd_resource
*rsc
,
282 unsigned level
, const struct pipe_box
*box
)
284 struct pipe_context
*pctx
= &ctx
->base
;
285 struct pipe_resource tmpl
= rsc
->base
;
287 tmpl
.width0
= box
->width
;
288 tmpl
.height0
= box
->height
;
289 tmpl
.depth0
= box
->depth
;
292 tmpl
.bind
|= PIPE_BIND_LINEAR
;
294 struct pipe_resource
*pstaging
=
295 pctx
->screen
->resource_create(pctx
->screen
, &tmpl
);
299 return fd_resource(pstaging
);
303 fd_blit_from_staging(struct fd_context
*ctx
, struct fd_transfer
*trans
)
305 struct pipe_resource
*dst
= trans
->base
.resource
;
306 struct pipe_blit_info blit
= {};
308 blit
.dst
.resource
= dst
;
309 blit
.dst
.format
= dst
->format
;
310 blit
.dst
.level
= trans
->base
.level
;
311 blit
.dst
.box
= trans
->base
.box
;
312 blit
.src
.resource
= trans
->staging_prsc
;
313 blit
.src
.format
= trans
->staging_prsc
->format
;
315 blit
.src
.box
= trans
->staging_box
;
316 blit
.mask
= util_format_get_mask(trans
->staging_prsc
->format
);
317 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
319 do_blit(ctx
, &blit
, false);
323 fd_blit_to_staging(struct fd_context
*ctx
, struct fd_transfer
*trans
)
325 struct pipe_resource
*src
= trans
->base
.resource
;
326 struct pipe_blit_info blit
= {};
328 blit
.src
.resource
= src
;
329 blit
.src
.format
= src
->format
;
330 blit
.src
.level
= trans
->base
.level
;
331 blit
.src
.box
= trans
->base
.box
;
332 blit
.dst
.resource
= trans
->staging_prsc
;
333 blit
.dst
.format
= trans
->staging_prsc
->format
;
335 blit
.dst
.box
= trans
->staging_box
;
336 blit
.mask
= util_format_get_mask(trans
->staging_prsc
->format
);
337 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
339 do_blit(ctx
, &blit
, false);
343 fd_resource_layer_offset(struct fd_resource
*rsc
,
344 struct fd_resource_slice
*slice
,
347 if (rsc
->layer_first
)
348 return layer
* rsc
->layer_size
;
350 return layer
* slice
->size0
;
353 static void fd_resource_transfer_flush_region(struct pipe_context
*pctx
,
354 struct pipe_transfer
*ptrans
,
355 const struct pipe_box
*box
)
357 struct fd_resource
*rsc
= fd_resource(ptrans
->resource
);
359 if (ptrans
->resource
->target
== PIPE_BUFFER
)
360 util_range_add(&rsc
->valid_buffer_range
,
361 ptrans
->box
.x
+ box
->x
,
362 ptrans
->box
.x
+ box
->x
+ box
->width
);
366 flush_resource(struct fd_context
*ctx
, struct fd_resource
*rsc
, unsigned usage
)
368 struct fd_batch
*write_batch
= NULL
;
370 fd_batch_reference(&write_batch
, rsc
->write_batch
);
372 if (usage
& PIPE_TRANSFER_WRITE
) {
373 struct fd_batch
*batch
, *batches
[32] = {};
376 /* This is a bit awkward, probably a fd_batch_flush_locked()
377 * would make things simpler.. but we need to hold the lock
378 * to iterate the batches which reference this resource. So
379 * we must first grab references under a lock, then flush.
381 mtx_lock(&ctx
->screen
->lock
);
382 batch_mask
= rsc
->batch_mask
;
383 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
)
384 fd_batch_reference(&batches
[batch
->idx
], batch
);
385 mtx_unlock(&ctx
->screen
->lock
);
387 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
)
388 fd_batch_flush(batch
, false, false);
390 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
) {
391 fd_batch_sync(batch
);
392 fd_batch_reference(&batches
[batch
->idx
], NULL
);
394 assert(rsc
->batch_mask
== 0);
395 } else if (write_batch
) {
396 fd_batch_flush(write_batch
, true, false);
399 fd_batch_reference(&write_batch
, NULL
);
401 assert(!rsc
->write_batch
);
405 fd_flush_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
407 flush_resource(fd_context(pctx
), fd_resource(prsc
), PIPE_TRANSFER_READ
);
411 fd_resource_transfer_unmap(struct pipe_context
*pctx
,
412 struct pipe_transfer
*ptrans
)
414 struct fd_context
*ctx
= fd_context(pctx
);
415 struct fd_resource
*rsc
= fd_resource(ptrans
->resource
);
416 struct fd_transfer
*trans
= fd_transfer(ptrans
);
418 if (trans
->staging_prsc
) {
419 if (ptrans
->usage
& PIPE_TRANSFER_WRITE
)
420 fd_blit_from_staging(ctx
, trans
);
421 pipe_resource_reference(&trans
->staging_prsc
, NULL
);
424 if (!(ptrans
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
425 fd_bo_cpu_fini(rsc
->bo
);
428 util_range_add(&rsc
->valid_buffer_range
,
430 ptrans
->box
.x
+ ptrans
->box
.width
);
432 pipe_resource_reference(&ptrans
->resource
, NULL
);
433 slab_free(&ctx
->transfer_pool
, ptrans
);
437 fd_resource_transfer_map(struct pipe_context
*pctx
,
438 struct pipe_resource
*prsc
,
439 unsigned level
, unsigned usage
,
440 const struct pipe_box
*box
,
441 struct pipe_transfer
**pptrans
)
443 struct fd_context
*ctx
= fd_context(pctx
);
444 struct fd_resource
*rsc
= fd_resource(prsc
);
445 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, level
);
446 struct fd_transfer
*trans
;
447 struct pipe_transfer
*ptrans
;
448 enum pipe_format format
= prsc
->format
;
454 DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc
, level
, usage
,
455 box
->width
, box
->height
, box
->x
, box
->y
);
457 ptrans
= slab_alloc(&ctx
->transfer_pool
);
461 /* slab_alloc_st() doesn't zero: */
462 trans
= fd_transfer(ptrans
);
463 memset(trans
, 0, sizeof(*trans
));
465 pipe_resource_reference(&ptrans
->resource
, prsc
);
466 ptrans
->level
= level
;
467 ptrans
->usage
= usage
;
469 ptrans
->stride
= util_format_get_nblocksx(format
, slice
->pitch
) * rsc
->cpp
;
470 ptrans
->layer_stride
= rsc
->layer_first
? rsc
->layer_size
: slice
->size0
;
472 /* we always need a staging texture for tiled buffers:
474 * TODO we might sometimes want to *also* shadow the resource to avoid
475 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
478 if (rsc
->tile_mode
) {
479 struct fd_resource
*staging_rsc
;
481 staging_rsc
= fd_alloc_staging(ctx
, rsc
, level
, box
);
483 // TODO for PIPE_TRANSFER_READ, need to do untiling blit..
484 trans
->staging_prsc
= &staging_rsc
->base
;
485 trans
->base
.stride
= util_format_get_nblocksx(format
,
486 staging_rsc
->slices
[0].pitch
) * staging_rsc
->cpp
;
487 trans
->base
.layer_stride
= staging_rsc
->layer_first
?
488 staging_rsc
->layer_size
: staging_rsc
->slices
[0].size0
;
489 trans
->staging_box
= *box
;
490 trans
->staging_box
.x
= 0;
491 trans
->staging_box
.y
= 0;
492 trans
->staging_box
.z
= 0;
494 if (usage
& PIPE_TRANSFER_READ
) {
495 fd_blit_to_staging(ctx
, trans
);
496 fd_bo_cpu_prep(rsc
->bo
, ctx
->pipe
, DRM_FREEDRENO_PREP_READ
);
499 buf
= fd_bo_map(staging_rsc
->bo
);
504 ctx
->stats
.staging_uploads
++;
510 if (ctx
->in_shadow
&& !(usage
& PIPE_TRANSFER_READ
))
511 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
513 if (usage
& PIPE_TRANSFER_READ
)
514 op
|= DRM_FREEDRENO_PREP_READ
;
516 if (usage
& PIPE_TRANSFER_WRITE
)
517 op
|= DRM_FREEDRENO_PREP_WRITE
;
519 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
520 realloc_bo(rsc
, fd_bo_size(rsc
->bo
));
521 rebind_resource(ctx
, prsc
);
522 } else if ((usage
& PIPE_TRANSFER_WRITE
) &&
523 prsc
->target
== PIPE_BUFFER
&&
524 !util_ranges_intersect(&rsc
->valid_buffer_range
,
525 box
->x
, box
->x
+ box
->width
)) {
526 /* We are trying to write to a previously uninitialized range. No need
529 } else if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
530 struct fd_batch
*write_batch
= NULL
;
532 /* hold a reference, so it doesn't disappear under us: */
533 fd_batch_reference(&write_batch
, rsc
->write_batch
);
535 if ((usage
& PIPE_TRANSFER_WRITE
) && write_batch
&&
536 write_batch
->back_blit
) {
537 /* if only thing pending is a back-blit, we can discard it: */
538 fd_batch_reset(write_batch
);
541 /* If the GPU is writing to the resource, or if it is reading from the
542 * resource and we're trying to write to it, flush the renders.
544 bool needs_flush
= pending(rsc
, !!(usage
& PIPE_TRANSFER_WRITE
));
545 bool busy
= needs_flush
|| (0 != fd_bo_cpu_prep(rsc
->bo
,
546 ctx
->pipe
, op
| DRM_FREEDRENO_PREP_NOSYNC
));
548 /* if we need to flush/stall, see if we can make a shadow buffer
551 * TODO we could go down this path !reorder && !busy_for_read
552 * ie. we only *don't* want to go down this path if the blit
553 * will trigger a flush!
555 if (ctx
->screen
->reorder
&& busy
&& !(usage
& PIPE_TRANSFER_READ
) &&
556 (usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
557 /* try shadowing only if it avoids a flush, otherwise staging would
560 if (needs_flush
&& fd_try_shadow_resource(ctx
, rsc
, level
, box
)) {
561 needs_flush
= busy
= false;
562 rebind_resource(ctx
, prsc
);
563 ctx
->stats
.shadow_uploads
++;
565 struct fd_resource
*staging_rsc
;
568 flush_resource(ctx
, rsc
, usage
);
572 /* in this case, we don't need to shadow the whole resource,
573 * since any draw that references the previous contents has
574 * already had rendering flushed for all tiles. So we can
575 * use a staging buffer to do the upload.
577 staging_rsc
= fd_alloc_staging(ctx
, rsc
, level
, box
);
579 trans
->staging_prsc
= &staging_rsc
->base
;
580 trans
->base
.stride
= util_format_get_nblocksx(format
,
581 staging_rsc
->slices
[0].pitch
) * staging_rsc
->cpp
;
582 trans
->base
.layer_stride
= staging_rsc
->layer_first
?
583 staging_rsc
->layer_size
: staging_rsc
->slices
[0].size0
;
584 trans
->staging_box
= *box
;
585 trans
->staging_box
.x
= 0;
586 trans
->staging_box
.y
= 0;
587 trans
->staging_box
.z
= 0;
588 buf
= fd_bo_map(staging_rsc
->bo
);
593 fd_batch_reference(&write_batch
, NULL
);
595 ctx
->stats
.staging_uploads
++;
603 flush_resource(ctx
, rsc
, usage
);
607 fd_batch_reference(&write_batch
, NULL
);
609 /* The GPU keeps track of how the various bo's are being used, and
610 * will wait if necessary for the proper operation to have
614 ret
= fd_bo_cpu_prep(rsc
->bo
, ctx
->pipe
, op
);
620 buf
= fd_bo_map(rsc
->bo
);
621 offset
= slice
->offset
+
622 box
->y
/ util_format_get_blockheight(format
) * ptrans
->stride
+
623 box
->x
/ util_format_get_blockwidth(format
) * rsc
->cpp
+
624 fd_resource_layer_offset(rsc
, slice
, box
->z
);
626 if (usage
& PIPE_TRANSFER_WRITE
)
634 fd_resource_transfer_unmap(pctx
, ptrans
);
639 fd_resource_destroy(struct pipe_screen
*pscreen
,
640 struct pipe_resource
*prsc
)
642 struct fd_resource
*rsc
= fd_resource(prsc
);
643 fd_bc_invalidate_resource(rsc
, true);
646 util_range_destroy(&rsc
->valid_buffer_range
);
651 fd_resource_get_handle(struct pipe_screen
*pscreen
,
652 struct pipe_context
*pctx
,
653 struct pipe_resource
*prsc
,
654 struct winsys_handle
*handle
,
657 struct fd_resource
*rsc
= fd_resource(prsc
);
659 return fd_screen_bo_get_handle(pscreen
, rsc
->bo
,
660 rsc
->slices
[0].pitch
* rsc
->cpp
, handle
);
664 setup_slices(struct fd_resource
*rsc
, uint32_t alignment
, enum pipe_format format
)
666 struct pipe_resource
*prsc
= &rsc
->base
;
667 struct fd_screen
*screen
= fd_screen(prsc
->screen
);
668 enum util_format_layout layout
= util_format_description(format
)->layout
;
669 uint32_t pitchalign
= screen
->gmem_alignw
;
670 uint32_t level
, size
= 0;
671 uint32_t width
= prsc
->width0
;
672 uint32_t height
= prsc
->height0
;
673 uint32_t depth
= prsc
->depth0
;
674 /* in layer_first layout, the level (slice) contains just one
675 * layer (since in fact the layer contains the slices)
677 uint32_t layers_in_level
= rsc
->layer_first
? 1 : prsc
->array_size
;
679 for (level
= 0; level
<= prsc
->last_level
; level
++) {
680 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, level
);
683 if (layout
== UTIL_FORMAT_LAYOUT_ASTC
)
684 slice
->pitch
= width
=
685 util_align_npot(width
, pitchalign
* util_format_get_blockwidth(format
));
687 slice
->pitch
= width
= align(width
, pitchalign
);
688 slice
->offset
= size
;
689 blocks
= util_format_get_nblocks(format
, width
, height
);
690 /* 1d array and 2d array textures must all have the same layer size
691 * for each miplevel on a3xx. 3d textures can have different layer
692 * sizes for high levels, but the hw auto-sizer is buggy (or at least
693 * different than what this code does), so as soon as the layer size
694 * range gets into range, we stop reducing it.
696 if (prsc
->target
== PIPE_TEXTURE_3D
&& (
698 (level
> 1 && rsc
->slices
[level
- 1].size0
> 0xf000)))
699 slice
->size0
= align(blocks
* rsc
->cpp
, alignment
);
700 else if (level
== 0 || rsc
->layer_first
|| alignment
== 1)
701 slice
->size0
= align(blocks
* rsc
->cpp
, alignment
);
703 slice
->size0
= rsc
->slices
[level
- 1].size0
;
705 size
+= slice
->size0
* depth
* layers_in_level
;
707 width
= u_minify(width
, 1);
708 height
= u_minify(height
, 1);
709 depth
= u_minify(depth
, 1);
716 slice_alignment(enum pipe_texture_target target
)
718 /* on a3xx, 2d array and 3d textures seem to want their
719 * layers aligned to page boundaries:
722 case PIPE_TEXTURE_3D
:
723 case PIPE_TEXTURE_1D_ARRAY
:
724 case PIPE_TEXTURE_2D_ARRAY
:
731 /* cross generation texture layout to plug in to screen->setup_slices()..
732 * replace with generation specific one as-needed.
734 * TODO for a4xx probably can extract out the a4xx specific logic int
735 * a small fd4_setup_slices() wrapper that sets up layer_first, and then
739 fd_setup_slices(struct fd_resource
*rsc
)
743 alignment
= slice_alignment(rsc
->base
.target
);
745 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
746 if (is_a4xx(screen
)) {
747 switch (rsc
->base
.target
) {
748 case PIPE_TEXTURE_3D
:
749 rsc
->layer_first
= false;
752 rsc
->layer_first
= true;
758 return setup_slices(rsc
, alignment
, rsc
->base
.format
);
761 /* special case to resize query buf after allocated.. */
763 fd_resource_resize(struct pipe_resource
*prsc
, uint32_t sz
)
765 struct fd_resource
*rsc
= fd_resource(prsc
);
767 debug_assert(prsc
->width0
== 0);
768 debug_assert(prsc
->target
== PIPE_BUFFER
);
769 debug_assert(prsc
->bind
== PIPE_BIND_QUERY_BUFFER
);
772 realloc_bo(rsc
, fd_screen(prsc
->screen
)->setup_slices(rsc
));
775 // TODO common helper?
777 has_depth(enum pipe_format format
)
780 case PIPE_FORMAT_Z16_UNORM
:
781 case PIPE_FORMAT_Z32_UNORM
:
782 case PIPE_FORMAT_Z32_FLOAT
:
783 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
784 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
785 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
786 case PIPE_FORMAT_Z24X8_UNORM
:
787 case PIPE_FORMAT_X8Z24_UNORM
:
795 * Create a new texture object, using the given template info.
797 static struct pipe_resource
*
798 fd_resource_create(struct pipe_screen
*pscreen
,
799 const struct pipe_resource
*tmpl
)
801 struct fd_screen
*screen
= fd_screen(pscreen
);
802 struct fd_resource
*rsc
= CALLOC_STRUCT(fd_resource
);
803 struct pipe_resource
*prsc
= &rsc
->base
;
804 enum pipe_format format
= tmpl
->format
;
807 DBG("%p: target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
808 "nr_samples=%u, usage=%u, bind=%x, flags=%x", prsc
,
809 tmpl
->target
, util_format_name(format
),
810 tmpl
->width0
, tmpl
->height0
, tmpl
->depth0
,
811 tmpl
->array_size
, tmpl
->last_level
, tmpl
->nr_samples
,
812 tmpl
->usage
, tmpl
->bind
, tmpl
->flags
);
820 (PIPE_BIND_SCANOUT | \
822 PIPE_BIND_DISPLAY_TARGET)
824 if (screen
->tile_mode
&&
825 (tmpl
->target
!= PIPE_BUFFER
) &&
826 (tmpl
->bind
& PIPE_BIND_SAMPLER_VIEW
) &&
827 !(tmpl
->bind
& LINEAR
)) {
828 rsc
->tile_mode
= screen
->tile_mode(tmpl
);
831 pipe_reference_init(&prsc
->reference
, 1);
833 prsc
->screen
= pscreen
;
835 util_range_init(&rsc
->valid_buffer_range
);
837 rsc
->internal_format
= format
;
838 rsc
->cpp
= util_format_get_blocksize(format
);
839 prsc
->nr_samples
= MAX2(1, prsc
->nr_samples
);
840 rsc
->cpp
*= prsc
->nr_samples
;
844 // XXX probably need some extra work if we hit rsc shadowing path w/ lrz..
845 if ((is_a5xx(screen
) || is_a6xx(screen
)) &&
846 (fd_mesa_debug
& FD_DBG_LRZ
) && has_depth(format
)) {
847 const uint32_t flags
= DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
848 DRM_FREEDRENO_GEM_TYPE_KMEM
; /* TODO */
849 unsigned lrz_pitch
= align(DIV_ROUND_UP(tmpl
->width0
, 8), 64);
850 unsigned lrz_height
= DIV_ROUND_UP(tmpl
->height0
, 8);
851 unsigned size
= lrz_pitch
* lrz_height
* 2;
853 size
+= 0x1000; /* for GRAS_LRZ_FAST_CLEAR_BUFFER */
855 rsc
->lrz_height
= lrz_height
;
856 rsc
->lrz_width
= lrz_pitch
;
857 rsc
->lrz_pitch
= lrz_pitch
;
858 rsc
->lrz
= fd_bo_new(screen
->dev
, size
, flags
);
861 size
= screen
->setup_slices(rsc
);
863 /* special case for hw-query buffer, which we need to allocate before we
867 /* note, semi-intention == instead of & */
868 debug_assert(prsc
->bind
== PIPE_BIND_QUERY_BUFFER
);
872 if (rsc
->layer_first
) {
873 rsc
->layer_size
= align(size
, 4096);
874 size
= rsc
->layer_size
* prsc
->array_size
;
877 realloc_bo(rsc
, size
);
883 fd_resource_destroy(pscreen
, prsc
);
888 * Create a texture from a winsys_handle. The handle is often created in
889 * another process by first creating a pipe texture and then calling
890 * resource_get_handle.
892 static struct pipe_resource
*
893 fd_resource_from_handle(struct pipe_screen
*pscreen
,
894 const struct pipe_resource
*tmpl
,
895 struct winsys_handle
*handle
, unsigned usage
)
897 struct fd_resource
*rsc
= CALLOC_STRUCT(fd_resource
);
898 struct fd_resource_slice
*slice
= &rsc
->slices
[0];
899 struct pipe_resource
*prsc
= &rsc
->base
;
900 uint32_t pitchalign
= fd_screen(pscreen
)->gmem_alignw
;
902 DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
903 "nr_samples=%u, usage=%u, bind=%x, flags=%x",
904 tmpl
->target
, util_format_name(tmpl
->format
),
905 tmpl
->width0
, tmpl
->height0
, tmpl
->depth0
,
906 tmpl
->array_size
, tmpl
->last_level
, tmpl
->nr_samples
,
907 tmpl
->usage
, tmpl
->bind
, tmpl
->flags
);
914 pipe_reference_init(&prsc
->reference
, 1);
916 prsc
->screen
= pscreen
;
918 util_range_init(&rsc
->valid_buffer_range
);
920 rsc
->bo
= fd_screen_bo_from_handle(pscreen
, handle
);
924 prsc
->nr_samples
= MAX2(1, prsc
->nr_samples
);
925 rsc
->internal_format
= tmpl
->format
;
926 rsc
->cpp
= prsc
->nr_samples
* util_format_get_blocksize(tmpl
->format
);
927 slice
->pitch
= handle
->stride
/ rsc
->cpp
;
928 slice
->offset
= handle
->offset
;
929 slice
->size0
= handle
->stride
* prsc
->height0
;
931 if ((slice
->pitch
< align(prsc
->width0
, pitchalign
)) ||
932 (slice
->pitch
& (pitchalign
- 1)))
940 fd_resource_destroy(pscreen
, prsc
);
945 * _copy_region using pipe (3d engine)
948 fd_blitter_pipe_copy_region(struct fd_context
*ctx
,
949 struct pipe_resource
*dst
,
951 unsigned dstx
, unsigned dsty
, unsigned dstz
,
952 struct pipe_resource
*src
,
954 const struct pipe_box
*src_box
)
956 /* not until we allow rendertargets to be buffers */
957 if (dst
->target
== PIPE_BUFFER
|| src
->target
== PIPE_BUFFER
)
960 if (!util_blitter_is_copy_supported(ctx
->blitter
, dst
, src
))
963 /* TODO we could discard if dst box covers dst level fully.. */
964 fd_blitter_pipe_begin(ctx
, false, false, FD_STAGE_BLIT
);
965 util_blitter_copy_texture(ctx
->blitter
,
966 dst
, dst_level
, dstx
, dsty
, dstz
,
967 src
, src_level
, src_box
);
968 fd_blitter_pipe_end(ctx
);
974 * Copy a block of pixels from one resource to another.
975 * The resource must be of the same format.
976 * Resources with nr_samples > 1 are not allowed.
979 fd_resource_copy_region(struct pipe_context
*pctx
,
980 struct pipe_resource
*dst
,
982 unsigned dstx
, unsigned dsty
, unsigned dstz
,
983 struct pipe_resource
*src
,
985 const struct pipe_box
*src_box
)
987 struct fd_context
*ctx
= fd_context(pctx
);
989 /* TODO if we have 2d core, or other DMA engine that could be used
990 * for simple copies and reasonably easily synchronized with the 3d
991 * core, this is where we'd plug it in..
994 /* try blit on 3d pipe: */
995 if (fd_blitter_pipe_copy_region(ctx
,
996 dst
, dst_level
, dstx
, dsty
, dstz
,
997 src
, src_level
, src_box
))
1000 /* else fallback to pure sw: */
1001 util_resource_copy_region(pctx
,
1002 dst
, dst_level
, dstx
, dsty
, dstz
,
1003 src
, src_level
, src_box
);
1007 fd_render_condition_check(struct pipe_context
*pctx
)
1009 struct fd_context
*ctx
= fd_context(pctx
);
1011 if (!ctx
->cond_query
)
1014 union pipe_query_result res
= { 0 };
1016 ctx
->cond_mode
!= PIPE_RENDER_COND_NO_WAIT
&&
1017 ctx
->cond_mode
!= PIPE_RENDER_COND_BY_REGION_NO_WAIT
;
1019 if (pctx
->get_query_result(pctx
, ctx
->cond_query
, wait
, &res
))
1020 return (bool)res
.u64
!= ctx
->cond_cond
;
1026 * Optimal hardware path for blitting pixels.
1027 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
1030 fd_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
1032 struct fd_context
*ctx
= fd_context(pctx
);
1033 struct pipe_blit_info info
= *blit_info
;
1034 bool discard
= false;
1036 if (info
.render_condition_enable
&& !fd_render_condition_check(pctx
))
1039 if (!info
.scissor_enable
&& !info
.alpha_blend
) {
1040 discard
= util_texrange_covers_whole_level(info
.dst
.resource
,
1041 info
.dst
.level
, info
.dst
.box
.x
, info
.dst
.box
.y
,
1042 info
.dst
.box
.z
, info
.dst
.box
.width
,
1043 info
.dst
.box
.height
, info
.dst
.box
.depth
);
1046 if (util_try_blit_via_copy_region(pctx
, &info
)) {
1050 if (info
.mask
& PIPE_MASK_S
) {
1051 DBG("cannot blit stencil, skipping");
1052 info
.mask
&= ~PIPE_MASK_S
;
1055 if (!util_blitter_is_blit_supported(ctx
->blitter
, &info
)) {
1056 DBG("blit unsupported %s -> %s",
1057 util_format_short_name(info
.src
.resource
->format
),
1058 util_format_short_name(info
.dst
.resource
->format
));
1062 fd_blitter_pipe_begin(ctx
, info
.render_condition_enable
, discard
, FD_STAGE_BLIT
);
1063 ctx
->blit(ctx
, &info
);
1064 fd_blitter_pipe_end(ctx
);
1068 fd_blitter_pipe_begin(struct fd_context
*ctx
, bool render_cond
, bool discard
,
1069 enum fd_render_stage stage
)
1071 util_blitter_save_fragment_constant_buffer_slot(ctx
->blitter
,
1072 ctx
->constbuf
[PIPE_SHADER_FRAGMENT
].cb
);
1073 util_blitter_save_vertex_buffer_slot(ctx
->blitter
, ctx
->vtx
.vertexbuf
.vb
);
1074 util_blitter_save_vertex_elements(ctx
->blitter
, ctx
->vtx
.vtx
);
1075 util_blitter_save_vertex_shader(ctx
->blitter
, ctx
->prog
.vp
);
1076 util_blitter_save_so_targets(ctx
->blitter
, ctx
->streamout
.num_targets
,
1077 ctx
->streamout
.targets
);
1078 util_blitter_save_rasterizer(ctx
->blitter
, ctx
->rasterizer
);
1079 util_blitter_save_viewport(ctx
->blitter
, &ctx
->viewport
);
1080 util_blitter_save_scissor(ctx
->blitter
, &ctx
->scissor
);
1081 util_blitter_save_fragment_shader(ctx
->blitter
, ctx
->prog
.fp
);
1082 util_blitter_save_blend(ctx
->blitter
, ctx
->blend
);
1083 util_blitter_save_depth_stencil_alpha(ctx
->blitter
, ctx
->zsa
);
1084 util_blitter_save_stencil_ref(ctx
->blitter
, &ctx
->stencil_ref
);
1085 util_blitter_save_sample_mask(ctx
->blitter
, ctx
->sample_mask
);
1086 util_blitter_save_framebuffer(ctx
->blitter
, &ctx
->framebuffer
);
1087 util_blitter_save_fragment_sampler_states(ctx
->blitter
,
1088 ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_samplers
,
1089 (void **)ctx
->tex
[PIPE_SHADER_FRAGMENT
].samplers
);
1090 util_blitter_save_fragment_sampler_views(ctx
->blitter
,
1091 ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
,
1092 ctx
->tex
[PIPE_SHADER_FRAGMENT
].textures
);
1094 util_blitter_save_render_condition(ctx
->blitter
,
1095 ctx
->cond_query
, ctx
->cond_cond
, ctx
->cond_mode
);
1098 fd_batch_set_stage(ctx
->batch
, stage
);
1100 ctx
->in_blit
= discard
;
1104 fd_blitter_pipe_end(struct fd_context
*ctx
)
1107 fd_batch_set_stage(ctx
->batch
, FD_STAGE_NULL
);
1108 ctx
->in_blit
= false;
1112 fd_invalidate_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
1114 struct fd_resource
*rsc
= fd_resource(prsc
);
1117 * TODO I guess we could track that the resource is invalidated and
1118 * use that as a hint to realloc rather than stall in _transfer_map(),
1119 * even in the non-DISCARD_WHOLE_RESOURCE case?
1122 if (rsc
->write_batch
) {
1123 struct fd_batch
*batch
= rsc
->write_batch
;
1124 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1126 if (pfb
->zsbuf
&& pfb
->zsbuf
->texture
== prsc
)
1127 batch
->resolve
&= ~(FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
);
1129 for (unsigned i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1130 if (pfb
->cbufs
[i
] && pfb
->cbufs
[i
]->texture
== prsc
) {
1131 batch
->resolve
&= ~(PIPE_CLEAR_COLOR0
<< i
);
1139 static enum pipe_format
1140 fd_resource_get_internal_format(struct pipe_resource
*prsc
)
1142 return fd_resource(prsc
)->internal_format
;
1146 fd_resource_set_stencil(struct pipe_resource
*prsc
,
1147 struct pipe_resource
*stencil
)
1149 fd_resource(prsc
)->stencil
= fd_resource(stencil
);
1152 static struct pipe_resource
*
1153 fd_resource_get_stencil(struct pipe_resource
*prsc
)
1155 struct fd_resource
*rsc
= fd_resource(prsc
);
1157 return &rsc
->stencil
->base
;
1161 static const struct u_transfer_vtbl transfer_vtbl
= {
1162 .resource_create
= fd_resource_create
,
1163 .resource_destroy
= fd_resource_destroy
,
1164 .transfer_map
= fd_resource_transfer_map
,
1165 .transfer_flush_region
= fd_resource_transfer_flush_region
,
1166 .transfer_unmap
= fd_resource_transfer_unmap
,
1167 .get_internal_format
= fd_resource_get_internal_format
,
1168 .set_stencil
= fd_resource_set_stencil
,
1169 .get_stencil
= fd_resource_get_stencil
,
1173 fd_resource_screen_init(struct pipe_screen
*pscreen
)
1175 struct fd_screen
*screen
= fd_screen(pscreen
);
1176 bool fake_rgtc
= screen
->gpu_id
< 400;
1178 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1179 pscreen
->resource_from_handle
= fd_resource_from_handle
;
1180 pscreen
->resource_get_handle
= fd_resource_get_handle
;
1181 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1183 pscreen
->transfer_helper
= u_transfer_helper_create(&transfer_vtbl
,
1184 true, false, fake_rgtc
, true);
1186 if (!screen
->setup_slices
)
1187 screen
->setup_slices
= fd_setup_slices
;
1191 fd_resource_context_init(struct pipe_context
*pctx
)
1193 pctx
->transfer_map
= u_transfer_helper_transfer_map
;
1194 pctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1195 pctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1196 pctx
->buffer_subdata
= u_default_buffer_subdata
;
1197 pctx
->texture_subdata
= u_default_texture_subdata
;
1198 pctx
->create_surface
= fd_create_surface
;
1199 pctx
->surface_destroy
= fd_surface_destroy
;
1200 pctx
->resource_copy_region
= fd_resource_copy_region
;
1201 pctx
->blit
= fd_blit
;
1202 pctx
->flush_resource
= fd_flush_resource
;
1203 pctx
->invalidate_resource
= fd_invalidate_resource
;