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052565dcbdc9f22ff98d2b62d17497e6e496becd
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
40
41 #include "os/os_time.h"
42
43 #include <stdio.h>
44 #include <errno.h>
45 #include <stdlib.h>
46
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
52
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57
58 #include "ir3/ir3_nir.h"
59
60 /* XXX this should go away */
61 #include "state_tracker/drm_driver.h"
62
63 static const struct debug_named_value debug_options[] = {
64 {"msgs", FD_DBG_MSGS, "Print debug messages"},
65 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
66 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
67 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
68 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
69 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
70 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
71 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
72 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
73 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
74 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
75 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
76 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
77 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
78 {"nir", FD_DBG_NIR, "Prefer NIR as native IR"},
79 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 DEBUG_NAMED_VALUE_END
83 };
84
85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
86
87 int fd_mesa_debug = 0;
88 bool fd_binning_enabled = true;
89 static bool glsl120 = false;
90
91 static const char *
92 fd_screen_get_name(struct pipe_screen *pscreen)
93 {
94 static char buffer[128];
95 util_snprintf(buffer, sizeof(buffer), "FD%03d",
96 fd_screen(pscreen)->device_id);
97 return buffer;
98 }
99
100 static const char *
101 fd_screen_get_vendor(struct pipe_screen *pscreen)
102 {
103 return "freedreno";
104 }
105
106 static const char *
107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
108 {
109 return "Qualcomm";
110 }
111
112
113 static uint64_t
114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
115 {
116 struct fd_screen *screen = fd_screen(pscreen);
117
118 if (screen->has_timestamp) {
119 uint64_t n;
120 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
121 debug_assert(screen->max_freq > 0);
122 return n * 1000000000 / screen->max_freq;
123 } else {
124 int64_t cpu_time = os_time_get() * 1000;
125 return cpu_time + screen->cpu_gpu_time_delta;
126 }
127
128 }
129
130 static void
131 fd_screen_destroy(struct pipe_screen *pscreen)
132 {
133 struct fd_screen *screen = fd_screen(pscreen);
134
135 if (screen->pipe)
136 fd_pipe_del(screen->pipe);
137
138 if (screen->dev)
139 fd_device_del(screen->dev);
140
141 fd_bc_fini(&screen->batch_cache);
142
143 slab_destroy_parent(&screen->transfer_pool);
144
145 mtx_destroy(&screen->lock);
146
147 ralloc_free(screen->compiler);
148
149 free(screen);
150 }
151
152 /*
153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
154 tables for things that differ if the delta is not too much..
155 */
156 static int
157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
158 {
159 struct fd_screen *screen = fd_screen(pscreen);
160
161 /* this is probably not totally correct.. but it's a start: */
162 switch (param) {
163 /* Supported features (boolean caps). */
164 case PIPE_CAP_NPOT_TEXTURES:
165 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
166 case PIPE_CAP_TWO_SIDED_STENCIL:
167 case PIPE_CAP_ANISOTROPIC_FILTER:
168 case PIPE_CAP_POINT_SPRITE:
169 case PIPE_CAP_TEXTURE_SHADOW_MAP:
170 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
171 case PIPE_CAP_TEXTURE_SWIZZLE:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
173 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP:
176 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
177 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
178 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
179 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
180 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
182 case PIPE_CAP_STRING_MARKER:
183 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
184 return 1;
185
186 case PIPE_CAP_VERTEXID_NOBASE:
187 return is_a3xx(screen) || is_a4xx(screen);
188
189 case PIPE_CAP_USER_CONSTANT_BUFFERS:
190 return is_a4xx(screen) ? 0 : 1;
191
192 case PIPE_CAP_COMPUTE:
193 return has_compute(screen);
194
195 case PIPE_CAP_SHADER_STENCIL_EXPORT:
196 case PIPE_CAP_TGSI_TEXCOORD:
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
198 case PIPE_CAP_TEXTURE_MULTISAMPLE:
199 case PIPE_CAP_TEXTURE_BARRIER:
200 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
201 case PIPE_CAP_QUERY_MEMORY_INFO:
202 case PIPE_CAP_PCI_GROUP:
203 case PIPE_CAP_PCI_BUS:
204 case PIPE_CAP_PCI_DEVICE:
205 case PIPE_CAP_PCI_FUNCTION:
206 return 0;
207
208 case PIPE_CAP_SM3:
209 case PIPE_CAP_PRIMITIVE_RESTART:
210 case PIPE_CAP_TGSI_INSTANCEID:
211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
212 case PIPE_CAP_INDEP_BLEND_ENABLE:
213 case PIPE_CAP_INDEP_BLEND_FUNC:
214 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
215 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
216 case PIPE_CAP_CONDITIONAL_RENDER:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
218 case PIPE_CAP_FAKE_SW_MSAA:
219 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
220 case PIPE_CAP_DEPTH_CLIP_DISABLE:
221 case PIPE_CAP_CLIP_HALFZ:
222 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
223
224 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
225 return 0;
226 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
227 if (is_a3xx(screen)) return 16;
228 if (is_a4xx(screen)) return 32;
229 if (is_a5xx(screen)) return 32;
230 return 0;
231 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
232 /* We could possibly emulate more by pretending 2d/rect textures and
233 * splitting high bits of index into 2nd dimension..
234 */
235 if (is_a3xx(screen)) return 8192;
236 if (is_a4xx(screen)) return 16384;
237 if (is_a5xx(screen)) return 16384;
238 return 0;
239
240 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
241 case PIPE_CAP_CUBE_MAP_ARRAY:
242 case PIPE_CAP_START_INSTANCE:
243 case PIPE_CAP_SAMPLER_VIEW_TARGET:
244 case PIPE_CAP_TEXTURE_QUERY_LOD:
245 return is_a4xx(screen) || is_a5xx(screen);
246
247 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
248 return 64;
249
250 case PIPE_CAP_GLSL_FEATURE_LEVEL:
251 if (glsl120)
252 return 120;
253 return is_ir3(screen) ? 140 : 120;
254
255 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
256 if (is_a5xx(screen))
257 return 4;
258 return 0;
259
260 /* Unsupported features. */
261 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
262 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
263 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
264 case PIPE_CAP_USER_VERTEX_BUFFERS:
265 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
266 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
267 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
268 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
269 case PIPE_CAP_TEXTURE_GATHER_SM5:
270 case PIPE_CAP_SAMPLE_SHADING:
271 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
272 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
273 case PIPE_CAP_DRAW_INDIRECT:
274 case PIPE_CAP_MULTI_DRAW_INDIRECT:
275 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
276 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
277 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
278 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
279 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
280 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
281 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
282 case PIPE_CAP_DEPTH_BOUNDS_TEST:
283 case PIPE_CAP_TGSI_TXQS:
284 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
285 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
286 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
287 case PIPE_CAP_CLEAR_TEXTURE:
288 case PIPE_CAP_DRAW_PARAMETERS:
289 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
290 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
291 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
292 case PIPE_CAP_INVALIDATE_BUFFER:
293 case PIPE_CAP_GENERATE_MIPMAP:
294 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
295 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
296 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
297 case PIPE_CAP_CULL_DISTANCE:
298 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
299 case PIPE_CAP_TGSI_VOTE:
300 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
301 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
302 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
303 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
304 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
305 case PIPE_CAP_TGSI_FS_FBFETCH:
306 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
307 case PIPE_CAP_DOUBLES:
308 case PIPE_CAP_INT64:
309 case PIPE_CAP_INT64_DIVMOD:
310 case PIPE_CAP_TGSI_TEX_TXF_LZ:
311 case PIPE_CAP_TGSI_CLOCK:
312 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
313 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
314 case PIPE_CAP_TGSI_BALLOT:
315 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
316 return 0;
317
318 case PIPE_CAP_MAX_VIEWPORTS:
319 return 1;
320
321 case PIPE_CAP_SHAREABLE_SHADERS:
322 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
323 /* manage the variants for these ourself, to avoid breaking precompile: */
324 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
325 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
326 if (is_ir3(screen))
327 return 1;
328 return 0;
329
330 /* Stream output. */
331 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
332 if (is_ir3(screen))
333 return PIPE_MAX_SO_BUFFERS;
334 return 0;
335 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
336 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
337 if (is_ir3(screen))
338 return 1;
339 return 0;
340 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
341 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
342 if (is_ir3(screen))
343 return 16 * 4; /* should only be shader out limit? */
344 return 0;
345
346 /* Geometry shader output, unsupported. */
347 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
348 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
349 case PIPE_CAP_MAX_VERTEX_STREAMS:
350 return 0;
351
352 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
353 return 2048;
354
355 /* Texturing. */
356 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
357 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
358 return MAX_MIP_LEVELS;
359 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
360 return 11;
361
362 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
363 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
364
365 /* Render targets. */
366 case PIPE_CAP_MAX_RENDER_TARGETS:
367 return screen->max_rts;
368 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
369 return is_a3xx(screen) ? 1 : 0;
370
371 /* Queries. */
372 case PIPE_CAP_QUERY_BUFFER_OBJECT:
373 return 0;
374 case PIPE_CAP_OCCLUSION_QUERY:
375 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
376 case PIPE_CAP_QUERY_TIMESTAMP:
377 case PIPE_CAP_QUERY_TIME_ELAPSED:
378 /* only a4xx, requires new enough kernel so we know max_freq: */
379 return (screen->max_freq > 0) && is_a4xx(screen);
380
381 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
382 case PIPE_CAP_MIN_TEXEL_OFFSET:
383 return -8;
384
385 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
386 case PIPE_CAP_MAX_TEXEL_OFFSET:
387 return 7;
388
389 case PIPE_CAP_ENDIANNESS:
390 return PIPE_ENDIAN_LITTLE;
391
392 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
393 return 64;
394
395 case PIPE_CAP_VENDOR_ID:
396 return 0x5143;
397 case PIPE_CAP_DEVICE_ID:
398 return 0xFFFFFFFF;
399 case PIPE_CAP_ACCELERATED:
400 return 1;
401 case PIPE_CAP_VIDEO_MEMORY:
402 DBG("FINISHME: The value returned is incorrect\n");
403 return 10;
404 case PIPE_CAP_UMA:
405 return 1;
406 case PIPE_CAP_NATIVE_FENCE_FD:
407 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
408 }
409 debug_printf("unknown param %d\n", param);
410 return 0;
411 }
412
413 static float
414 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
415 {
416 switch (param) {
417 case PIPE_CAPF_MAX_LINE_WIDTH:
418 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
419 /* NOTE: actual value is 127.0f, but this is working around a deqp
420 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
421 * uses too small of a render target size, and gets confused when
422 * the lines start going offscreen.
423 *
424 * See: https://code.google.com/p/android/issues/detail?id=206513
425 */
426 if (fd_mesa_debug & FD_DBG_DEQP)
427 return 48.0f;
428 return 127.0f;
429 case PIPE_CAPF_MAX_POINT_WIDTH:
430 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
431 return 4092.0f;
432 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
433 return 16.0f;
434 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
435 return 15.0f;
436 case PIPE_CAPF_GUARD_BAND_LEFT:
437 case PIPE_CAPF_GUARD_BAND_TOP:
438 case PIPE_CAPF_GUARD_BAND_RIGHT:
439 case PIPE_CAPF_GUARD_BAND_BOTTOM:
440 return 0.0f;
441 }
442 debug_printf("unknown paramf %d\n", param);
443 return 0;
444 }
445
446 static int
447 fd_screen_get_shader_param(struct pipe_screen *pscreen,
448 enum pipe_shader_type shader,
449 enum pipe_shader_cap param)
450 {
451 struct fd_screen *screen = fd_screen(pscreen);
452
453 switch(shader)
454 {
455 case PIPE_SHADER_FRAGMENT:
456 case PIPE_SHADER_VERTEX:
457 break;
458 case PIPE_SHADER_COMPUTE:
459 if (has_compute(screen))
460 break;
461 return 0;
462 case PIPE_SHADER_GEOMETRY:
463 /* maye we could emulate.. */
464 return 0;
465 default:
466 DBG("unknown shader type %d", shader);
467 return 0;
468 }
469
470 /* this is probably not totally correct.. but it's a start: */
471 switch (param) {
472 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
473 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
474 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
475 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
476 return 16384;
477 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
478 return 8; /* XXX */
479 case PIPE_SHADER_CAP_MAX_INPUTS:
480 case PIPE_SHADER_CAP_MAX_OUTPUTS:
481 return 16;
482 case PIPE_SHADER_CAP_MAX_TEMPS:
483 return 64; /* Max native temporaries. */
484 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
485 /* NOTE: seems to be limit for a3xx is actually 512 but
486 * split between VS and FS. Use lower limit of 256 to
487 * avoid getting into impossible situations:
488 */
489 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
490 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
491 return is_ir3(screen) ? 16 : 1;
492 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
493 return 1;
494 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
495 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
496 /* Technically this should be the same as for TEMP/CONST, since
497 * everything is just normal registers. This is just temporary
498 * hack until load_input/store_output handle arrays in a similar
499 * way as load_var/store_var..
500 */
501 return 0;
502 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
503 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
504 /* a2xx compiler doesn't handle indirect: */
505 return is_ir3(screen) ? 1 : 0;
506 case PIPE_SHADER_CAP_SUBROUTINES:
507 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
508 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
509 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
510 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
511 return 0;
512 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
513 return 1;
514 case PIPE_SHADER_CAP_INTEGERS:
515 if (glsl120)
516 return 0;
517 return is_ir3(screen) ? 1 : 0;
518 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
519 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
520 return 16;
521 case PIPE_SHADER_CAP_PREFERRED_IR:
522 switch (shader) {
523 case PIPE_SHADER_FRAGMENT:
524 case PIPE_SHADER_VERTEX:
525 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
526 return PIPE_SHADER_IR_NIR;
527 return PIPE_SHADER_IR_TGSI;
528 default:
529 /* tgsi_to_nir doesn't really support much beyond FS/VS: */
530 debug_assert(is_ir3(screen));
531 return PIPE_SHADER_IR_NIR;
532 }
533 break;
534 case PIPE_SHADER_CAP_SUPPORTED_IRS:
535 if (is_ir3(screen)) {
536 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
537 } else {
538 return (1 << PIPE_SHADER_IR_TGSI);
539 }
540 return 0;
541 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
542 return 32;
543 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
544 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
545 return 0;
546 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
547 if (is_a5xx(screen)) {
548 /* a5xx (and a4xx for that matter) has one state-block
549 * for compute-shader SSBO's and another that is shared
550 * by VS/HS/DS/GS/FS.. so to simplify things for now
551 * just advertise SSBOs for FS and CS. We could possibly
552 * do what blob does, and partition the space for
553 * VS/HS/DS/GS/FS. The blob advertises:
554 *
555 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
556 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
557 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
558 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
559 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
560 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
561 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
562 *
563 * I think that way we could avoid having to patch shaders
564 * for actual SSBO indexes by using a static partitioning.
565 */
566 switch(shader)
567 {
568 case PIPE_SHADER_FRAGMENT:
569 case PIPE_SHADER_COMPUTE:
570 return 24;
571 default:
572 return 0;
573 }
574 }
575 return 0;
576 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
577 /* probably should be same as MAX_SHADRER_BUFFERS but not implemented yet */
578 return 0;
579 }
580 debug_printf("unknown shader param %d\n", param);
581 return 0;
582 }
583
584 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
585 * into per-generation backend?
586 */
587 static int
588 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
589 enum pipe_compute_cap param, void *ret)
590 {
591 struct fd_screen *screen = fd_screen(pscreen);
592 const char *ir = "ir3";
593
594 if (!has_compute(screen))
595 return 0;
596
597 switch (param) {
598 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
599 if (ret) {
600 uint32_t *address_bits = ret;
601 address_bits[0] = 32;
602
603 if (is_a5xx(screen))
604 address_bits[0] = 64;
605 }
606 return 1 * sizeof(uint32_t);
607
608 case PIPE_COMPUTE_CAP_IR_TARGET:
609 if (ret)
610 sprintf(ret, ir);
611 return strlen(ir) * sizeof(char);
612
613 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
614 if (ret) {
615 uint64_t *grid_dimension = ret;
616 grid_dimension[0] = 3;
617 }
618 return 1 * sizeof(uint64_t);
619
620 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
621 if (ret) {
622 uint64_t *grid_size = ret;
623 grid_size[0] = 65535;
624 grid_size[1] = 65535;
625 grid_size[2] = 65535;
626 }
627 return 3 * sizeof(uint64_t) ;
628
629 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
630 if (ret) {
631 uint64_t *grid_size = ret;
632 grid_size[0] = 1024;
633 grid_size[1] = 1024;
634 grid_size[2] = 64;
635 }
636 return 3 * sizeof(uint64_t) ;
637
638 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
639 if (ret) {
640 uint64_t *max_threads_per_block = ret;
641 *max_threads_per_block = 1024;
642 }
643 return sizeof(uint64_t);
644
645 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
646 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
647 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
648 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
649 break;
650 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
651 if (ret) {
652 uint64_t *max = ret;
653 *max = 32768;
654 }
655 return sizeof(uint64_t);
656 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
657 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
658 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
659 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
660 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
661 break;
662 }
663
664 return 0;
665 }
666
667 static const void *
668 fd_get_compiler_options(struct pipe_screen *pscreen,
669 enum pipe_shader_ir ir, unsigned shader)
670 {
671 struct fd_screen *screen = fd_screen(pscreen);
672
673 if (is_ir3(screen))
674 return ir3_get_compiler_options();
675
676 return NULL;
677 }
678
679 boolean
680 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
681 struct fd_bo *bo,
682 unsigned stride,
683 struct winsys_handle *whandle)
684 {
685 whandle->stride = stride;
686
687 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
688 return fd_bo_get_name(bo, &whandle->handle) == 0;
689 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
690 whandle->handle = fd_bo_handle(bo);
691 return TRUE;
692 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
693 whandle->handle = fd_bo_dmabuf(bo);
694 return TRUE;
695 } else {
696 return FALSE;
697 }
698 }
699
700 struct fd_bo *
701 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
702 struct winsys_handle *whandle)
703 {
704 struct fd_screen *screen = fd_screen(pscreen);
705 struct fd_bo *bo;
706
707 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
708 bo = fd_bo_from_name(screen->dev, whandle->handle);
709 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
710 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
711 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
712 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
713 } else {
714 DBG("Attempt to import unsupported handle type %d", whandle->type);
715 return NULL;
716 }
717
718 if (!bo) {
719 DBG("ref name 0x%08x failed", whandle->handle);
720 return NULL;
721 }
722
723 return bo;
724 }
725
726 struct pipe_screen *
727 fd_screen_create(struct fd_device *dev)
728 {
729 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
730 struct pipe_screen *pscreen;
731 uint64_t val;
732
733 fd_mesa_debug = debug_get_option_fd_mesa_debug();
734
735 if (fd_mesa_debug & FD_DBG_NOBIN)
736 fd_binning_enabled = false;
737
738 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
739
740 if (!screen)
741 return NULL;
742
743 pscreen = &screen->base;
744
745 screen->dev = dev;
746 screen->refcnt = 1;
747
748 // maybe this should be in context?
749 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
750 if (!screen->pipe) {
751 DBG("could not create 3d pipe");
752 goto fail;
753 }
754
755 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
756 DBG("could not get GMEM size");
757 goto fail;
758 }
759 screen->gmemsize_bytes = val;
760
761 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
762 DBG("could not get device-id");
763 goto fail;
764 }
765 screen->device_id = val;
766
767 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
768 DBG("could not get gpu freq");
769 /* this limits what performance related queries are
770 * supported but is not fatal
771 */
772 screen->max_freq = 0;
773 } else {
774 screen->max_freq = val;
775 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
776 screen->has_timestamp = true;
777 }
778
779 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
780 DBG("could not get gpu-id");
781 goto fail;
782 }
783 screen->gpu_id = val;
784
785 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
786 DBG("could not get chip-id");
787 /* older kernels may not have this property: */
788 unsigned core = screen->gpu_id / 100;
789 unsigned major = (screen->gpu_id % 100) / 10;
790 unsigned minor = screen->gpu_id % 10;
791 unsigned patch = 0; /* assume the worst */
792 val = (patch & 0xff) | ((minor & 0xff) << 8) |
793 ((major & 0xff) << 16) | ((core & 0xff) << 24);
794 }
795 screen->chip_id = val;
796
797 DBG("Pipe Info:");
798 DBG(" GPU-id: %d", screen->gpu_id);
799 DBG(" Chip-id: 0x%08x", screen->chip_id);
800 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
801
802 /* explicitly checking for GPU revisions that are known to work. This
803 * may be overly conservative for a3xx, where spoofing the gpu_id with
804 * the blob driver seems to generate identical cmdstream dumps. But
805 * on a2xx, there seem to be small differences between the GPU revs
806 * so it is probably better to actually test first on real hardware
807 * before enabling:
808 *
809 * If you have a different adreno version, feel free to add it to one
810 * of the cases below and see what happens. And if it works, please
811 * send a patch ;-)
812 */
813 switch (screen->gpu_id) {
814 case 220:
815 fd2_screen_init(pscreen);
816 break;
817 case 305:
818 case 307:
819 case 320:
820 case 330:
821 fd3_screen_init(pscreen);
822 break;
823 case 420:
824 case 430:
825 fd4_screen_init(pscreen);
826 break;
827 case 530:
828 fd5_screen_init(pscreen);
829 break;
830 default:
831 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
832 goto fail;
833 }
834
835 if (screen->gpu_id >= 500) {
836 screen->gmem_alignw = 64;
837 screen->gmem_alignh = 32;
838 } else {
839 screen->gmem_alignw = 32;
840 screen->gmem_alignh = 32;
841 }
842
843 /* NOTE: don't enable reordering on a2xx, since completely untested.
844 * Also, don't enable if we have too old of a kernel to support
845 * growable cmdstream buffers, since memory requirement for cmdstream
846 * buffers would be too much otherwise.
847 */
848 if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
849 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
850
851 fd_bc_init(&screen->batch_cache);
852
853 (void) mtx_init(&screen->lock, mtx_plain);
854
855 pscreen->destroy = fd_screen_destroy;
856 pscreen->get_param = fd_screen_get_param;
857 pscreen->get_paramf = fd_screen_get_paramf;
858 pscreen->get_shader_param = fd_screen_get_shader_param;
859 pscreen->get_compute_param = fd_get_compute_param;
860 pscreen->get_compiler_options = fd_get_compiler_options;
861
862 fd_resource_screen_init(pscreen);
863 fd_query_screen_init(pscreen);
864
865 pscreen->get_name = fd_screen_get_name;
866 pscreen->get_vendor = fd_screen_get_vendor;
867 pscreen->get_device_vendor = fd_screen_get_device_vendor;
868
869 pscreen->get_timestamp = fd_screen_get_timestamp;
870
871 pscreen->fence_reference = fd_fence_ref;
872 pscreen->fence_finish = fd_fence_finish;
873 pscreen->fence_get_fd = fd_fence_get_fd;
874
875 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
876
877 util_format_s3tc_init();
878
879 return pscreen;
880
881 fail:
882 fd_screen_destroy(pscreen);
883 return NULL;
884 }