src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55
  56 /* XXX this should go away */
  57 #include "state_tracker/drm_driver.h"
  58
  59 static const struct debug_named_value debug_options[] = {
  60                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  61                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  62                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  63                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  64                 {"dscis",     FD_DBG_DSCIS,  "Disable scissor optimization"},
  65                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  66                 {"dbypass",   FD_DBG_DBYPASS,"Disable GMEM bypass"},
  67                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  68                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  69                 {"noopt",     FD_DBG_NOOPT , "Disable optimization passes in compiler"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizater debug messages"},
  71                 {"optdump",   FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
  72                 {"glsl130",   FD_DBG_GLSL130,"Temporary flag to enable GLSL 130 on a3xx+"},
  73                 DEBUG_NAMED_VALUE_END
  74 };
  75
  76 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  77
  78 int fd_mesa_debug = 0;
  79 bool fd_binning_enabled = true;
  80 static bool glsl130 = false;
  81
  82 static const char *
  83 fd_screen_get_name(struct pipe_screen *pscreen)
  84 {
  85         static char buffer[128];
  86         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  87                         fd_screen(pscreen)->device_id);
  88         return buffer;
  89 }
  90
  91 static const char *
  92 fd_screen_get_vendor(struct pipe_screen *pscreen)
  93 {
  94         return "freedreno";
  95 }
  96
  97 static uint64_t
  98 fd_screen_get_timestamp(struct pipe_screen *pscreen)
  99 {
 100         int64_t cpu_time = os_time_get() * 1000;
 101         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 102 }
 103
 104 static void
 105 fd_screen_fence_ref(struct pipe_screen *pscreen,
 106                 struct pipe_fence_handle **ptr,
 107                 struct pipe_fence_handle *pfence)
 108 {
 109         fd_fence_ref(fd_fence(pfence), (struct fd_fence **)ptr);
 110 }
 111
 112 static boolean
 113 fd_screen_fence_signalled(struct pipe_screen *screen,
 114                 struct pipe_fence_handle *pfence)
 115 {
 116         return fd_fence_signalled(fd_fence(pfence));
 117 }
 118
 119 static boolean
 120 fd_screen_fence_finish(struct pipe_screen *screen,
 121                 struct pipe_fence_handle *pfence,
 122                 uint64_t timeout)
 123 {
 124         return fd_fence_wait(fd_fence(pfence));
 125 }
 126
 127 static void
 128 fd_screen_destroy(struct pipe_screen *pscreen)
 129 {
 130         struct fd_screen *screen = fd_screen(pscreen);
 131
 132         if (screen->pipe)
 133                 fd_pipe_del(screen->pipe);
 134
 135         if (screen->dev)
 136                 fd_device_del(screen->dev);
 137
 138         free(screen);
 139 }
 140
 141 /*
 142 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 143 tables for things that differ if the delta is not too much..
 144  */
 145 static int
 146 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 147 {
 148         struct fd_screen *screen = fd_screen(pscreen);
 149
 150         /* this is probably not totally correct.. but it's a start: */
 151         switch (param) {
 152         /* Supported features (boolean caps). */
 153         case PIPE_CAP_NPOT_TEXTURES:
 154         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 155         case PIPE_CAP_TWO_SIDED_STENCIL:
 156         case PIPE_CAP_ANISOTROPIC_FILTER:
 157         case PIPE_CAP_POINT_SPRITE:
 158         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 159         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 160         case PIPE_CAP_TEXTURE_SWIZZLE:
 161         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 162         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 163         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 164         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 165         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 166         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 167         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 168         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 169         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 170         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 171         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 172         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 173                 return 1;
 174
 175         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 176         case PIPE_CAP_TGSI_TEXCOORD:
 177         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 178         case PIPE_CAP_CONDITIONAL_RENDER:
 179         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180         case PIPE_CAP_TEXTURE_BARRIER:
 181         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 182         case PIPE_CAP_CUBE_MAP_ARRAY:
 183         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 184         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 185         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 186         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 187         case PIPE_CAP_TGSI_INSTANCEID:
 188         case PIPE_CAP_START_INSTANCE:
 189         case PIPE_CAP_COMPUTE:
 190                 return 0;
 191
 192         case PIPE_CAP_SM3:
 193         case PIPE_CAP_PRIMITIVE_RESTART:
 194                 return (screen->gpu_id >= 300) ? 1 : 0;
 195
 196         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 197                 return 256;
 198
 199         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 200                 return ((screen->gpu_id >= 300) && glsl130) ? 130 : 120;
 201
 202         /* Unsupported features. */
 203         case PIPE_CAP_INDEP_BLEND_ENABLE:
 204         case PIPE_CAP_INDEP_BLEND_FUNC:
 205         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 206         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 207         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 208         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 209         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 210         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 211         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 212         case PIPE_CAP_USER_VERTEX_BUFFERS:
 213         case PIPE_CAP_USER_INDEX_BUFFERS:
 214         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 215         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 216         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 217         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 218         case PIPE_CAP_TEXTURE_GATHER_SM5:
 219         case PIPE_CAP_FAKE_SW_MSAA:
 220         case PIPE_CAP_TEXTURE_QUERY_LOD:
 221         case PIPE_CAP_SAMPLE_SHADING:
 222         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 223         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 224         case PIPE_CAP_DRAW_INDIRECT:
 225         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 226         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 227         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 228                 return 0;
 229
 230         case PIPE_CAP_MAX_VIEWPORTS:
 231                 return 1;
 232
 233         /* Stream output. */
 234         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 235         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 236         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 237         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 238                 return 0;
 239
 240         /* Geometry shader output, unsupported. */
 241         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 242         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 243         case PIPE_CAP_MAX_VERTEX_STREAMS:
 244                 return 0;
 245
 246         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 247                 return 2048;
 248
 249         /* Texturing. */
 250         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 251         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 252                 return MAX_MIP_LEVELS;
 253         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 254                 return 11;
 255
 256         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 257                 return (screen->gpu_id >= 300) ? 256 : 0;
 258
 259         /* Render targets. */
 260         case PIPE_CAP_MAX_RENDER_TARGETS:
 261                 return 1;
 262
 263         /* Queries. */
 264         case PIPE_CAP_QUERY_TIME_ELAPSED:
 265         case PIPE_CAP_QUERY_TIMESTAMP:
 266                 return 0;
 267         case PIPE_CAP_OCCLUSION_QUERY:
 268                 return (screen->gpu_id >= 300) ? 1 : 0;
 269
 270         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 271         case PIPE_CAP_MIN_TEXEL_OFFSET:
 272                 return -8;
 273
 274         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 275         case PIPE_CAP_MAX_TEXEL_OFFSET:
 276                 return 7;
 277
 278         case PIPE_CAP_ENDIANNESS:
 279                 return PIPE_ENDIAN_LITTLE;
 280
 281         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 282                 return 64;
 283
 284         case PIPE_CAP_VENDOR_ID:
 285                 return 0x5143;
 286         case PIPE_CAP_DEVICE_ID:
 287                 return 0xFFFFFFFF;
 288         case PIPE_CAP_ACCELERATED:
 289                 return 1;
 290         case PIPE_CAP_VIDEO_MEMORY:
 291                 DBG("FINISHME: The value returned is incorrect\n");
 292                 return 10;
 293         case PIPE_CAP_UMA:
 294                 return 1;
 295         }
 296         debug_printf("unknown param %d\n", param);
 297         return 0;
 298 }
 299
 300 static float
 301 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 302 {
 303         switch (param) {
 304         case PIPE_CAPF_MAX_LINE_WIDTH:
 305         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 306         case PIPE_CAPF_MAX_POINT_WIDTH:
 307         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 308                 return 8192.0f;
 309         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 310                 return 16.0f;
 311         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 312                 return 15.0f;
 313         case PIPE_CAPF_GUARD_BAND_LEFT:
 314         case PIPE_CAPF_GUARD_BAND_TOP:
 315         case PIPE_CAPF_GUARD_BAND_RIGHT:
 316         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 317                 return 0.0f;
 318         }
 319         debug_printf("unknown paramf %d\n", param);
 320         return 0;
 321 }
 322
 323 static int
 324 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 325                 enum pipe_shader_cap param)
 326 {
 327         struct fd_screen *screen = fd_screen(pscreen);
 328
 329         switch(shader)
 330         {
 331         case PIPE_SHADER_FRAGMENT:
 332         case PIPE_SHADER_VERTEX:
 333                 break;
 334         case PIPE_SHADER_COMPUTE:
 335         case PIPE_SHADER_GEOMETRY:
 336                 /* maye we could emulate.. */
 337                 return 0;
 338         default:
 339                 DBG("unknown shader type %d", shader);
 340                 return 0;
 341         }
 342
 343         /* this is probably not totally correct.. but it's a start: */
 344         switch (param) {
 345         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 346         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 347         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 348         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 349                 return 16384;
 350         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 351                 return 8; /* XXX */
 352         case PIPE_SHADER_CAP_MAX_INPUTS:
 353                 return 16;
 354         case PIPE_SHADER_CAP_MAX_TEMPS:
 355                 return 64; /* Max native temporaries. */
 356         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 357                 /* NOTE: seems to be limit for a3xx is actually 512 but
 358                  * split between VS and FS.  Use lower limit of 256 to
 359                  * avoid getting into impossible situations:
 360                  */
 361                 return ((screen->gpu_id >= 300) ? 256 : 64) * sizeof(float[4]);
 362         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 363                 return 1;
 364         case PIPE_SHADER_CAP_MAX_PREDS:
 365                 return 0; /* nothing uses this */
 366         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 367                 return 1;
 368         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 369         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 370         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 371         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 372                 return 1;
 373         case PIPE_SHADER_CAP_SUBROUTINES:
 374         case PIPE_SHADER_CAP_DOUBLES:
 375                 return 0;
 376         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 377                 return 1;
 378         case PIPE_SHADER_CAP_INTEGERS:
 379                 /* we should be able to support this on a3xx, but not
 380                  * implemented yet:
 381                  */
 382                 return ((screen->gpu_id >= 300) && glsl130) ? 1 : 0;
 383         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 384         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 385                 return 16;
 386         case PIPE_SHADER_CAP_PREFERRED_IR:
 387                 return PIPE_SHADER_IR_TGSI;
 388         }
 389         debug_printf("unknown shader param %d\n", param);
 390         return 0;
 391 }
 392
 393 boolean
 394 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 395                 struct fd_bo *bo,
 396                 unsigned stride,
 397                 struct winsys_handle *whandle)
 398 {
 399         whandle->stride = stride;
 400
 401         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 402                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 403         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 404                 whandle->handle = fd_bo_handle(bo);
 405                 return TRUE;
 406         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 407                 whandle->handle = fd_bo_dmabuf(bo);
 408                 return TRUE;
 409         } else {
 410                 return FALSE;
 411         }
 412 }
 413
 414 struct fd_bo *
 415 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 416                 struct winsys_handle *whandle,
 417                 unsigned *out_stride)
 418 {
 419         struct fd_screen *screen = fd_screen(pscreen);
 420         struct fd_bo *bo;
 421
 422         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 423                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 424         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 425                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 426         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 427                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 428         } else {
 429                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 430                 return NULL;
 431         }
 432
 433         if (!bo) {
 434                 DBG("ref name 0x%08x failed", whandle->handle);
 435                 return NULL;
 436         }
 437
 438         *out_stride = whandle->stride;
 439
 440         return bo;
 441 }
 442
 443 struct pipe_screen *
 444 fd_screen_create(struct fd_device *dev)
 445 {
 446         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 447         struct pipe_screen *pscreen;
 448         uint64_t val;
 449
 450         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 451
 452         if (fd_mesa_debug & FD_DBG_NOBIN)
 453                 fd_binning_enabled = false;
 454
 455         glsl130 = !!(fd_mesa_debug & FD_DBG_GLSL130);
 456
 457         if (!screen)
 458                 return NULL;
 459
 460         pscreen = &screen->base;
 461
 462         screen->dev = dev;
 463
 464         // maybe this should be in context?
 465         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 466         if (!screen->pipe) {
 467                 DBG("could not create 3d pipe");
 468                 goto fail;
 469         }
 470
 471         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 472                 DBG("could not get GMEM size");
 473                 goto fail;
 474         }
 475         screen->gmemsize_bytes = val;
 476
 477         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 478                 DBG("could not get device-id");
 479                 goto fail;
 480         }
 481         screen->device_id = val;
 482
 483         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 484                 DBG("could not get gpu-id");
 485                 goto fail;
 486         }
 487         screen->gpu_id = val;
 488
 489         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 490                 DBG("could not get chip-id");
 491                 /* older kernels may not have this property: */
 492                 unsigned core  = screen->gpu_id / 100;
 493                 unsigned major = (screen->gpu_id % 100) / 10;
 494                 unsigned minor = screen->gpu_id % 10;
 495                 unsigned patch = 0;  /* assume the worst */
 496                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 497                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 498         }
 499         screen->chip_id = val;
 500
 501         DBG("Pipe Info:");
 502         DBG(" GPU-id:          %d", screen->gpu_id);
 503         DBG(" Chip-id:         0x%08x", screen->chip_id);
 504         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 505
 506         /* explicitly checking for GPU revisions that are known to work.  This
 507          * may be overly conservative for a3xx, where spoofing the gpu_id with
 508          * the blob driver seems to generate identical cmdstream dumps.  But
 509          * on a2xx, there seem to be small differences between the GPU revs
 510          * so it is probably better to actually test first on real hardware
 511          * before enabling:
 512          *
 513          * If you have a different adreno version, feel free to add it to one
 514          * of the two cases below and see what happens.  And if it works, please
 515          * send a patch ;-)
 516          */
 517         switch (screen->gpu_id) {
 518         case 220:
 519                 fd2_screen_init(pscreen);
 520                 break;
 521         case 320:
 522         case 330:
 523                 fd3_screen_init(pscreen);
 524                 break;
 525         default:
 526                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 527                 goto fail;
 528         }
 529
 530         pscreen->destroy = fd_screen_destroy;
 531         pscreen->get_param = fd_screen_get_param;
 532         pscreen->get_paramf = fd_screen_get_paramf;
 533         pscreen->get_shader_param = fd_screen_get_shader_param;
 534
 535         fd_resource_screen_init(pscreen);
 536         fd_query_screen_init(pscreen);
 537
 538         pscreen->get_name = fd_screen_get_name;
 539         pscreen->get_vendor = fd_screen_get_vendor;
 540
 541         pscreen->get_timestamp = fd_screen_get_timestamp;
 542
 543         pscreen->fence_reference = fd_screen_fence_ref;
 544         pscreen->fence_signalled = fd_screen_fence_signalled;
 545         pscreen->fence_finish = fd_screen_fence_finish;
 546
 547         util_format_s3tc_init();
 548
 549         return pscreen;
 550
 551 fail:
 552         fd_screen_destroy(pscreen);
 553         return NULL;
 554 }