2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
45 #include <sys/sysinfo.h>
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57 #include "a6xx/fd6_screen.h"
60 #include "ir3/ir3_nir.h"
62 /* XXX this should go away */
63 #include "state_tracker/drm_driver.h"
65 static const struct debug_named_value debug_options
[] = {
66 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
67 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
68 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
69 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
70 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
71 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
72 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
73 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
74 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
75 {"optmsgs", FD_DBG_OPTMSGS
,"Enable optimizer debug messages"},
76 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
77 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
78 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
79 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
80 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
81 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
82 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
83 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
84 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
85 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
86 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
87 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a5xx)"},
88 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
92 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
94 int fd_mesa_debug
= 0;
95 bool fd_binning_enabled
= true;
96 static bool glsl120
= false;
98 static const struct debug_named_value shader_debug_options
[] = {
99 {"vs", FD_DBG_SHADER_VS
, "Print shader disasm for vertex shaders"},
100 {"fs", FD_DBG_SHADER_FS
, "Print shader disasm for fragment shaders"},
101 {"cs", FD_DBG_SHADER_CS
, "Print shader disasm for compute shaders"},
102 DEBUG_NAMED_VALUE_END
105 DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug
, "FD_SHADER_DEBUG", shader_debug_options
, 0)
107 enum fd_shader_debug fd_shader_debug
= 0;
110 fd_screen_get_name(struct pipe_screen
*pscreen
)
112 static char buffer
[128];
113 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
114 fd_screen(pscreen
)->device_id
);
119 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
125 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
132 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
134 struct fd_screen
*screen
= fd_screen(pscreen
);
136 if (screen
->has_timestamp
) {
138 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
139 debug_assert(screen
->max_freq
> 0);
140 return n
* 1000000000 / screen
->max_freq
;
142 int64_t cpu_time
= os_time_get() * 1000;
143 return cpu_time
+ screen
->cpu_gpu_time_delta
;
149 fd_screen_destroy(struct pipe_screen
*pscreen
)
151 struct fd_screen
*screen
= fd_screen(pscreen
);
154 fd_pipe_del(screen
->pipe
);
157 fd_device_del(screen
->dev
);
159 fd_bc_fini(&screen
->batch_cache
);
161 slab_destroy_parent(&screen
->transfer_pool
);
163 mtx_destroy(&screen
->lock
);
165 ralloc_free(screen
->compiler
);
167 free(screen
->perfcntr_queries
);
172 TODO either move caps to a2xx/a3xx specific code, or maybe have some
173 tables for things that differ if the delta is not too much..
176 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
178 struct fd_screen
*screen
= fd_screen(pscreen
);
180 /* this is probably not totally correct.. but it's a start: */
182 /* Supported features (boolean caps). */
183 case PIPE_CAP_NPOT_TEXTURES
:
184 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
185 case PIPE_CAP_ANISOTROPIC_FILTER
:
186 case PIPE_CAP_POINT_SPRITE
:
187 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
188 case PIPE_CAP_TEXTURE_SWIZZLE
:
189 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
190 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
191 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
192 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
193 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
194 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
195 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
196 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
197 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
198 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
199 case PIPE_CAP_STRING_MARKER
:
200 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
201 case PIPE_CAP_TEXTURE_BARRIER
:
202 case PIPE_CAP_INVALIDATE_BUFFER
:
205 case PIPE_CAP_VERTEXID_NOBASE
:
206 return is_a3xx(screen
) || is_a4xx(screen
);
208 case PIPE_CAP_COMPUTE
:
209 return has_compute(screen
);
211 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
212 case PIPE_CAP_PCI_GROUP
:
213 case PIPE_CAP_PCI_BUS
:
214 case PIPE_CAP_PCI_DEVICE
:
215 case PIPE_CAP_PCI_FUNCTION
:
216 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
220 case PIPE_CAP_PRIMITIVE_RESTART
:
221 case PIPE_CAP_TGSI_INSTANCEID
:
222 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
223 case PIPE_CAP_INDEP_BLEND_ENABLE
:
224 case PIPE_CAP_INDEP_BLEND_FUNC
:
225 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
226 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
227 case PIPE_CAP_CONDITIONAL_RENDER
:
228 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
229 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
230 case PIPE_CAP_CLIP_HALFZ
:
231 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
233 case PIPE_CAP_FAKE_SW_MSAA
:
234 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
236 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
237 return is_a5xx(screen
) || is_a6xx(screen
);
239 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
240 return is_a3xx(screen
) || is_a4xx(screen
);
242 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
243 return is_a5xx(screen
) || is_a6xx(screen
);
245 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
246 if (is_a3xx(screen
)) return 16;
247 if (is_a4xx(screen
)) return 32;
248 if (is_a5xx(screen
)) return 32;
249 if (is_a6xx(screen
)) return 32;
251 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
252 /* We could possibly emulate more by pretending 2d/rect textures and
253 * splitting high bits of index into 2nd dimension..
255 if (is_a3xx(screen
)) return 8192;
256 if (is_a4xx(screen
)) return 16384;
257 if (is_a5xx(screen
)) return 16384;
258 if (is_a6xx(screen
)) return 16384;
261 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
262 case PIPE_CAP_CUBE_MAP_ARRAY
:
263 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
264 case PIPE_CAP_TEXTURE_QUERY_LOD
:
265 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
267 case PIPE_CAP_START_INSTANCE
:
268 /* Note that a5xx can do this, it just can't (at least with
269 * current firmware) do draw_indirect with base_instance.
270 * Since draw_indirect is needed sooner (gles31 and gl40 vs
271 * gl42), hide base_instance on a5xx. :-/
273 return is_a4xx(screen
);
275 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
278 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
279 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
282 return is_ir3(screen
) ? 140 : 120;
284 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
285 if (is_a5xx(screen
) || is_a6xx(screen
))
289 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
290 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
294 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
295 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
298 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
301 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
302 return screen
->priority_mask
;
304 case PIPE_CAP_DRAW_INDIRECT
:
305 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
309 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
310 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
314 case PIPE_CAP_LOAD_CONSTBUF
:
315 /* name is confusing, but this turns on std430 packing */
320 case PIPE_CAP_MAX_VIEWPORTS
:
323 case PIPE_CAP_SHAREABLE_SHADERS
:
324 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
325 /* manage the variants for these ourself, to avoid breaking precompile: */
326 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
327 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
333 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
335 return PIPE_MAX_SO_BUFFERS
;
337 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
338 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
342 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
343 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
345 return 16 * 4; /* should only be shader out limit? */
349 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
350 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
351 return MAX_MIP_LEVELS
;
352 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
355 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
356 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
358 /* Render targets. */
359 case PIPE_CAP_MAX_RENDER_TARGETS
:
360 return screen
->max_rts
;
361 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
362 return is_a3xx(screen
) ? 1 : 0;
365 case PIPE_CAP_OCCLUSION_QUERY
:
366 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
367 case PIPE_CAP_QUERY_TIMESTAMP
:
368 case PIPE_CAP_QUERY_TIME_ELAPSED
:
369 /* only a4xx, requires new enough kernel so we know max_freq: */
370 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
372 case PIPE_CAP_VENDOR_ID
:
374 case PIPE_CAP_DEVICE_ID
:
376 case PIPE_CAP_ACCELERATED
:
378 case PIPE_CAP_VIDEO_MEMORY
:
379 DBG("FINISHME: The value returned is incorrect\n");
383 case PIPE_CAP_NATIVE_FENCE_FD
:
384 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
386 return u_pipe_screen_get_param_defaults(pscreen
, param
);
391 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
394 case PIPE_CAPF_MAX_LINE_WIDTH
:
395 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
396 /* NOTE: actual value is 127.0f, but this is working around a deqp
397 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
398 * uses too small of a render target size, and gets confused when
399 * the lines start going offscreen.
401 * See: https://code.google.com/p/android/issues/detail?id=206513
403 if (fd_mesa_debug
& FD_DBG_DEQP
)
406 case PIPE_CAPF_MAX_POINT_WIDTH
:
407 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
409 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
411 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
413 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
414 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
415 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
418 debug_printf("unknown paramf %d\n", param
);
423 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
424 enum pipe_shader_type shader
,
425 enum pipe_shader_cap param
)
427 struct fd_screen
*screen
= fd_screen(pscreen
);
431 case PIPE_SHADER_FRAGMENT
:
432 case PIPE_SHADER_VERTEX
:
434 case PIPE_SHADER_COMPUTE
:
435 if (has_compute(screen
))
438 case PIPE_SHADER_GEOMETRY
:
439 /* maye we could emulate.. */
442 DBG("unknown shader type %d", shader
);
446 /* this is probably not totally correct.. but it's a start: */
448 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
449 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
450 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
451 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
453 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
455 case PIPE_SHADER_CAP_MAX_INPUTS
:
456 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
458 case PIPE_SHADER_CAP_MAX_TEMPS
:
459 return 64; /* Max native temporaries. */
460 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
461 /* NOTE: seems to be limit for a3xx is actually 512 but
462 * split between VS and FS. Use lower limit of 256 to
463 * avoid getting into impossible situations:
465 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
466 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
467 return is_ir3(screen
) ? 16 : 1;
468 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
470 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
471 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
472 /* Technically this should be the same as for TEMP/CONST, since
473 * everything is just normal registers. This is just temporary
474 * hack until load_input/store_output handle arrays in a similar
475 * way as load_var/store_var..
478 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
479 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
480 /* a2xx compiler doesn't handle indirect: */
481 return is_ir3(screen
) ? 1 : 0;
482 case PIPE_SHADER_CAP_SUBROUTINES
:
483 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
484 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
485 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
486 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
487 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
488 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
489 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
490 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
491 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
493 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
495 case PIPE_SHADER_CAP_INTEGERS
:
498 return is_ir3(screen
) ? 1 : 0;
499 case PIPE_SHADER_CAP_INT64_ATOMICS
:
501 case PIPE_SHADER_CAP_FP16
:
503 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
504 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
506 case PIPE_SHADER_CAP_PREFERRED_IR
:
508 return PIPE_SHADER_IR_NIR
;
509 return PIPE_SHADER_IR_TGSI
;
510 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
511 if (is_ir3(screen
)) {
512 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
514 return (1 << PIPE_SHADER_IR_TGSI
);
517 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
519 case PIPE_SHADER_CAP_SCALAR_ISA
:
520 return is_ir3(screen
) ? 1 : 0;
521 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
522 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
523 if (is_a5xx(screen
) || is_a6xx(screen
)) {
524 /* a5xx (and a4xx for that matter) has one state-block
525 * for compute-shader SSBO's and another that is shared
526 * by VS/HS/DS/GS/FS.. so to simplify things for now
527 * just advertise SSBOs for FS and CS. We could possibly
528 * do what blob does, and partition the space for
529 * VS/HS/DS/GS/FS. The blob advertises:
531 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
532 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
533 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
534 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
535 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
536 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
537 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
539 * I think that way we could avoid having to patch shaders
540 * for actual SSBO indexes by using a static partitioning.
542 * Note same state block is used for images and buffers,
543 * but images also need texture state for read access
548 case PIPE_SHADER_FRAGMENT
:
549 case PIPE_SHADER_COMPUTE
:
557 debug_printf("unknown shader param %d\n", param
);
561 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
562 * into per-generation backend?
565 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
566 enum pipe_compute_cap param
, void *ret
)
568 struct fd_screen
*screen
= fd_screen(pscreen
);
569 const char * const ir
= "ir3";
571 if (!has_compute(screen
))
574 #define RET(x) do { \
576 memcpy(ret, x, sizeof(x)); \
581 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
582 // don't expose 64b pointer support yet, until ir3 supports 64b
583 // math, otherwise spir64 target is used and we get 64b pointer
584 // calculations that we can't do yet
585 // if (is_a5xx(screen))
586 // RET((uint32_t []){ 64 });
587 RET((uint32_t []){ 32 });
589 case PIPE_COMPUTE_CAP_IR_TARGET
:
592 return strlen(ir
) * sizeof(char);
594 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
595 RET((uint64_t []) { 3 });
597 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
598 RET(((uint64_t []) { 65535, 65535, 65535 }));
600 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
601 RET(((uint64_t []) { 1024, 1024, 64 }));
603 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
604 RET((uint64_t []) { 1024 });
606 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
607 RET((uint64_t []) { screen
->ram_size
});
609 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
610 RET((uint64_t []) { 32768 });
612 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
613 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
614 RET((uint64_t []) { 4096 });
616 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
617 RET((uint64_t []) { screen
->ram_size
});
619 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
620 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
622 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
623 RET((uint32_t []) { 9999 }); // TODO
625 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
626 RET((uint32_t []) { 1 });
628 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
629 RET((uint32_t []) { 32 }); // TODO
631 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
632 RET((uint64_t []) { 1024 }); // TODO
639 fd_get_compiler_options(struct pipe_screen
*pscreen
,
640 enum pipe_shader_ir ir
, unsigned shader
)
642 struct fd_screen
*screen
= fd_screen(pscreen
);
645 return ir3_get_compiler_options(screen
->compiler
);
651 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
654 struct winsys_handle
*whandle
)
656 whandle
->stride
= stride
;
658 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
659 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
660 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
661 whandle
->handle
= fd_bo_handle(bo
);
663 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
664 whandle
->handle
= fd_bo_dmabuf(bo
);
672 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
673 struct winsys_handle
*whandle
)
675 struct fd_screen
*screen
= fd_screen(pscreen
);
678 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
679 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
680 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
681 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
682 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
683 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
685 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
690 DBG("ref name 0x%08x failed", whandle
->handle
);
698 fd_screen_create(struct fd_device
*dev
)
700 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
701 struct pipe_screen
*pscreen
;
704 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
705 fd_shader_debug
= debug_get_option_fd_shader_debug();
707 if (fd_mesa_debug
& FD_DBG_NOBIN
)
708 fd_binning_enabled
= false;
710 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
715 pscreen
= &screen
->base
;
720 // maybe this should be in context?
721 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
723 DBG("could not create 3d pipe");
727 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
728 DBG("could not get GMEM size");
731 screen
->gmemsize_bytes
= val
;
733 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
734 DBG("could not get device-id");
737 screen
->device_id
= val
;
739 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
740 DBG("could not get gpu freq");
741 /* this limits what performance related queries are
742 * supported but is not fatal
744 screen
->max_freq
= 0;
746 screen
->max_freq
= val
;
747 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
748 screen
->has_timestamp
= true;
751 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
752 DBG("could not get gpu-id");
755 screen
->gpu_id
= val
;
757 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
758 DBG("could not get chip-id");
759 /* older kernels may not have this property: */
760 unsigned core
= screen
->gpu_id
/ 100;
761 unsigned major
= (screen
->gpu_id
% 100) / 10;
762 unsigned minor
= screen
->gpu_id
% 10;
763 unsigned patch
= 0; /* assume the worst */
764 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
765 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
767 screen
->chip_id
= val
;
769 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
770 DBG("could not get # of rings");
771 screen
->priority_mask
= 0;
773 /* # of rings equates to number of unique priority values: */
774 screen
->priority_mask
= (1 << val
) - 1;
779 screen
->ram_size
= si
.totalram
;
782 DBG(" GPU-id: %d", screen
->gpu_id
);
783 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
784 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
786 /* explicitly checking for GPU revisions that are known to work. This
787 * may be overly conservative for a3xx, where spoofing the gpu_id with
788 * the blob driver seems to generate identical cmdstream dumps. But
789 * on a2xx, there seem to be small differences between the GPU revs
790 * so it is probably better to actually test first on real hardware
793 * If you have a different adreno version, feel free to add it to one
794 * of the cases below and see what happens. And if it works, please
797 switch (screen
->gpu_id
) {
800 fd2_screen_init(pscreen
);
806 fd3_screen_init(pscreen
);
810 fd4_screen_init(pscreen
);
813 fd5_screen_init(pscreen
);
816 fd6_screen_init(pscreen
);
819 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
823 if (screen
->gpu_id
>= 600) {
824 screen
->gmem_alignw
= 32;
825 screen
->gmem_alignh
= 32;
826 screen
->num_vsc_pipes
= 32;
827 } else if (screen
->gpu_id
>= 500) {
828 screen
->gmem_alignw
= 64;
829 screen
->gmem_alignh
= 32;
830 screen
->num_vsc_pipes
= 16;
832 screen
->gmem_alignw
= 32;
833 screen
->gmem_alignh
= 32;
834 screen
->num_vsc_pipes
= 8;
837 /* NOTE: don't enable reordering on a2xx, since completely untested.
838 * Also, don't enable if we have too old of a kernel to support
839 * growable cmdstream buffers, since memory requirement for cmdstream
840 * buffers would be too much otherwise.
842 if ((screen
->gpu_id
>= 300) && (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
))
843 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
845 fd_bc_init(&screen
->batch_cache
);
847 (void) mtx_init(&screen
->lock
, mtx_plain
);
849 pscreen
->destroy
= fd_screen_destroy
;
850 pscreen
->get_param
= fd_screen_get_param
;
851 pscreen
->get_paramf
= fd_screen_get_paramf
;
852 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
853 pscreen
->get_compute_param
= fd_get_compute_param
;
854 pscreen
->get_compiler_options
= fd_get_compiler_options
;
856 fd_resource_screen_init(pscreen
);
857 fd_query_screen_init(pscreen
);
859 pscreen
->get_name
= fd_screen_get_name
;
860 pscreen
->get_vendor
= fd_screen_get_vendor
;
861 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
863 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
865 pscreen
->fence_reference
= fd_fence_ref
;
866 pscreen
->fence_finish
= fd_fence_finish
;
867 pscreen
->fence_get_fd
= fd_fence_get_fd
;
869 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
874 fd_screen_destroy(pscreen
);