66fe0e571cf8013328ee7a4608c3ab13871369c1
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
40
41 #include "os/os_time.h"
42
43 #include <stdio.h>
44 #include <errno.h>
45 #include <stdlib.h>
46
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
52
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56
57 /* XXX this should go away */
58 #include "state_tracker/drm_driver.h"
59
60 static const struct debug_named_value debug_options[] = {
61 {"msgs", FD_DBG_MSGS, "Print debug messages"},
62 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
63 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
64 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
65 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
66 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
67 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
68 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
69 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
70 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
71 {"optdump", FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
72 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 120 (rather than 130) on a3xx+"},
73 {"nocp", FD_DBG_NOCP, "Disable copy-propagation"},
74 DEBUG_NAMED_VALUE_END
75 };
76
77 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
78
79 int fd_mesa_debug = 0;
80 bool fd_binning_enabled = true;
81 static bool glsl120 = false;
82
83 static const char *
84 fd_screen_get_name(struct pipe_screen *pscreen)
85 {
86 static char buffer[128];
87 util_snprintf(buffer, sizeof(buffer), "FD%03d",
88 fd_screen(pscreen)->device_id);
89 return buffer;
90 }
91
92 static const char *
93 fd_screen_get_vendor(struct pipe_screen *pscreen)
94 {
95 return "freedreno";
96 }
97
98 static const char *
99 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
100 {
101 return "Qualcomm";
102 }
103
104
105 static uint64_t
106 fd_screen_get_timestamp(struct pipe_screen *pscreen)
107 {
108 int64_t cpu_time = os_time_get() * 1000;
109 return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
110 }
111
112 static void
113 fd_screen_destroy(struct pipe_screen *pscreen)
114 {
115 struct fd_screen *screen = fd_screen(pscreen);
116
117 if (screen->pipe)
118 fd_pipe_del(screen->pipe);
119
120 if (screen->dev)
121 fd_device_del(screen->dev);
122
123 free(screen);
124 }
125
126 /*
127 TODO either move caps to a2xx/a3xx specific code, or maybe have some
128 tables for things that differ if the delta is not too much..
129 */
130 static int
131 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
132 {
133 struct fd_screen *screen = fd_screen(pscreen);
134
135 /* this is probably not totally correct.. but it's a start: */
136 switch (param) {
137 /* Supported features (boolean caps). */
138 case PIPE_CAP_NPOT_TEXTURES:
139 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
140 case PIPE_CAP_TWO_SIDED_STENCIL:
141 case PIPE_CAP_ANISOTROPIC_FILTER:
142 case PIPE_CAP_POINT_SPRITE:
143 case PIPE_CAP_TEXTURE_SHADOW_MAP:
144 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
145 case PIPE_CAP_TEXTURE_SWIZZLE:
146 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
147 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
148 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
149 case PIPE_CAP_SEAMLESS_CUBE_MAP:
150 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
151 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
152 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
153 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
154 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
155 case PIPE_CAP_USER_CONSTANT_BUFFERS:
156 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
157 case PIPE_CAP_VERTEXID_NOBASE:
158 return 1;
159
160 case PIPE_CAP_SHADER_STENCIL_EXPORT:
161 case PIPE_CAP_TGSI_TEXCOORD:
162 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
163 case PIPE_CAP_CONDITIONAL_RENDER:
164 case PIPE_CAP_TEXTURE_MULTISAMPLE:
165 case PIPE_CAP_TEXTURE_BARRIER:
166 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
167 case PIPE_CAP_CUBE_MAP_ARRAY:
168 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
169 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
170 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
171 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
172 case PIPE_CAP_START_INSTANCE:
173 case PIPE_CAP_COMPUTE:
174 return 0;
175
176 case PIPE_CAP_SM3:
177 case PIPE_CAP_PRIMITIVE_RESTART:
178 case PIPE_CAP_TGSI_INSTANCEID:
179 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
180 return is_a3xx(screen) || is_a4xx(screen);
181
182 case PIPE_CAP_INDEP_BLEND_ENABLE:
183 case PIPE_CAP_INDEP_BLEND_FUNC:
184 return is_a3xx(screen);
185
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
187 return 256;
188
189 case PIPE_CAP_GLSL_FEATURE_LEVEL:
190 if (glsl120)
191 return 120;
192 return (is_a3xx(screen) || is_a4xx(screen)) ? 130 : 120;
193
194 /* Unsupported features. */
195 case PIPE_CAP_DEPTH_CLIP_DISABLE:
196 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
199 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
200 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
201 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
202 case PIPE_CAP_USER_VERTEX_BUFFERS:
203 case PIPE_CAP_USER_INDEX_BUFFERS:
204 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
205 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
206 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
207 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
208 case PIPE_CAP_TEXTURE_GATHER_SM5:
209 case PIPE_CAP_FAKE_SW_MSAA:
210 case PIPE_CAP_TEXTURE_QUERY_LOD:
211 case PIPE_CAP_SAMPLE_SHADING:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
213 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
214 case PIPE_CAP_DRAW_INDIRECT:
215 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
216 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
217 case PIPE_CAP_SAMPLER_VIEW_TARGET:
218 case PIPE_CAP_CLIP_HALFZ:
219 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
220 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
221 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
222 return 0;
223
224 case PIPE_CAP_MAX_VIEWPORTS:
225 return 1;
226
227 /* Stream output. */
228 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
229 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
230 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
231 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
232 return 0;
233
234 /* Geometry shader output, unsupported. */
235 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
236 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
237 case PIPE_CAP_MAX_VERTEX_STREAMS:
238 return 0;
239
240 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
241 return 2048;
242
243 /* Texturing. */
244 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
245 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
246 return MAX_MIP_LEVELS;
247 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
248 return 11;
249
250 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
251 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
252
253 /* Render targets. */
254 case PIPE_CAP_MAX_RENDER_TARGETS:
255 return screen->max_rts;
256
257 /* Queries. */
258 case PIPE_CAP_QUERY_TIME_ELAPSED:
259 case PIPE_CAP_QUERY_TIMESTAMP:
260 return 0;
261 case PIPE_CAP_OCCLUSION_QUERY:
262 /* TODO still missing on a4xx, but we lie to get gl2..
263 * it's not a feature, it's a bug!
264 */
265 return is_a3xx(screen) || is_a4xx(screen);
266
267 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
268 case PIPE_CAP_MIN_TEXEL_OFFSET:
269 return -8;
270
271 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
272 case PIPE_CAP_MAX_TEXEL_OFFSET:
273 return 7;
274
275 case PIPE_CAP_ENDIANNESS:
276 return PIPE_ENDIAN_LITTLE;
277
278 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
279 return 64;
280
281 case PIPE_CAP_VENDOR_ID:
282 return 0x5143;
283 case PIPE_CAP_DEVICE_ID:
284 return 0xFFFFFFFF;
285 case PIPE_CAP_ACCELERATED:
286 return 1;
287 case PIPE_CAP_VIDEO_MEMORY:
288 DBG("FINISHME: The value returned is incorrect\n");
289 return 10;
290 case PIPE_CAP_UMA:
291 return 1;
292 }
293 debug_printf("unknown param %d\n", param);
294 return 0;
295 }
296
297 static float
298 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
299 {
300 switch (param) {
301 case PIPE_CAPF_MAX_LINE_WIDTH:
302 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
303 case PIPE_CAPF_MAX_POINT_WIDTH:
304 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
305 return 4092.0f;
306 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
307 return 16.0f;
308 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
309 return 15.0f;
310 case PIPE_CAPF_GUARD_BAND_LEFT:
311 case PIPE_CAPF_GUARD_BAND_TOP:
312 case PIPE_CAPF_GUARD_BAND_RIGHT:
313 case PIPE_CAPF_GUARD_BAND_BOTTOM:
314 return 0.0f;
315 }
316 debug_printf("unknown paramf %d\n", param);
317 return 0;
318 }
319
320 static int
321 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
322 enum pipe_shader_cap param)
323 {
324 struct fd_screen *screen = fd_screen(pscreen);
325
326 switch(shader)
327 {
328 case PIPE_SHADER_FRAGMENT:
329 case PIPE_SHADER_VERTEX:
330 break;
331 case PIPE_SHADER_COMPUTE:
332 case PIPE_SHADER_GEOMETRY:
333 /* maye we could emulate.. */
334 return 0;
335 default:
336 DBG("unknown shader type %d", shader);
337 return 0;
338 }
339
340 /* this is probably not totally correct.. but it's a start: */
341 switch (param) {
342 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
343 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
344 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
345 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
346 return 16384;
347 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
348 return 8; /* XXX */
349 case PIPE_SHADER_CAP_MAX_INPUTS:
350 case PIPE_SHADER_CAP_MAX_OUTPUTS:
351 return 16;
352 case PIPE_SHADER_CAP_MAX_TEMPS:
353 return 64; /* Max native temporaries. */
354 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
355 /* NOTE: seems to be limit for a3xx is actually 512 but
356 * split between VS and FS. Use lower limit of 256 to
357 * avoid getting into impossible situations:
358 */
359 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
360 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
361 return is_a3xx(screen) ? 16 : 1;
362 case PIPE_SHADER_CAP_MAX_PREDS:
363 return 0; /* nothing uses this */
364 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
365 return 1;
366 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
367 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
368 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
369 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
370 return 1;
371 case PIPE_SHADER_CAP_SUBROUTINES:
372 case PIPE_SHADER_CAP_DOUBLES:
373 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
374 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
375 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
376 return 0;
377 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
378 return 1;
379 case PIPE_SHADER_CAP_INTEGERS:
380 if (glsl120)
381 return 0;
382 return (is_a3xx(screen) || is_a4xx(screen)) ? 1 : 0;
383 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
384 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
385 return 16;
386 case PIPE_SHADER_CAP_PREFERRED_IR:
387 return PIPE_SHADER_IR_TGSI;
388 }
389 debug_printf("unknown shader param %d\n", param);
390 return 0;
391 }
392
393 boolean
394 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
395 struct fd_bo *bo,
396 unsigned stride,
397 struct winsys_handle *whandle)
398 {
399 whandle->stride = stride;
400
401 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
402 return fd_bo_get_name(bo, &whandle->handle) == 0;
403 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
404 whandle->handle = fd_bo_handle(bo);
405 return TRUE;
406 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
407 whandle->handle = fd_bo_dmabuf(bo);
408 return TRUE;
409 } else {
410 return FALSE;
411 }
412 }
413
414 struct fd_bo *
415 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
416 struct winsys_handle *whandle,
417 unsigned *out_stride)
418 {
419 struct fd_screen *screen = fd_screen(pscreen);
420 struct fd_bo *bo;
421
422 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
423 bo = fd_bo_from_name(screen->dev, whandle->handle);
424 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
425 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
426 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
427 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
428 } else {
429 DBG("Attempt to import unsupported handle type %d", whandle->type);
430 return NULL;
431 }
432
433 if (!bo) {
434 DBG("ref name 0x%08x failed", whandle->handle);
435 return NULL;
436 }
437
438 *out_stride = whandle->stride;
439
440 return bo;
441 }
442
443 struct pipe_screen *
444 fd_screen_create(struct fd_device *dev)
445 {
446 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
447 struct pipe_screen *pscreen;
448 uint64_t val;
449
450 fd_mesa_debug = debug_get_option_fd_mesa_debug();
451
452 if (fd_mesa_debug & FD_DBG_NOBIN)
453 fd_binning_enabled = false;
454
455 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
456
457 if (!screen)
458 return NULL;
459
460 pscreen = &screen->base;
461
462 screen->dev = dev;
463
464 // maybe this should be in context?
465 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
466 if (!screen->pipe) {
467 DBG("could not create 3d pipe");
468 goto fail;
469 }
470
471 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
472 DBG("could not get GMEM size");
473 goto fail;
474 }
475 screen->gmemsize_bytes = val;
476
477 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
478 DBG("could not get device-id");
479 goto fail;
480 }
481 screen->device_id = val;
482
483 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
484 DBG("could not get gpu-id");
485 goto fail;
486 }
487 screen->gpu_id = val;
488
489 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
490 DBG("could not get chip-id");
491 /* older kernels may not have this property: */
492 unsigned core = screen->gpu_id / 100;
493 unsigned major = (screen->gpu_id % 100) / 10;
494 unsigned minor = screen->gpu_id % 10;
495 unsigned patch = 0; /* assume the worst */
496 val = (patch & 0xff) | ((minor & 0xff) << 8) |
497 ((major & 0xff) << 16) | ((core & 0xff) << 24);
498 }
499 screen->chip_id = val;
500
501 DBG("Pipe Info:");
502 DBG(" GPU-id: %d", screen->gpu_id);
503 DBG(" Chip-id: 0x%08x", screen->chip_id);
504 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
505
506 /* explicitly checking for GPU revisions that are known to work. This
507 * may be overly conservative for a3xx, where spoofing the gpu_id with
508 * the blob driver seems to generate identical cmdstream dumps. But
509 * on a2xx, there seem to be small differences between the GPU revs
510 * so it is probably better to actually test first on real hardware
511 * before enabling:
512 *
513 * If you have a different adreno version, feel free to add it to one
514 * of the cases below and see what happens. And if it works, please
515 * send a patch ;-)
516 */
517 switch (screen->gpu_id) {
518 case 220:
519 fd2_screen_init(pscreen);
520 break;
521 case 320:
522 case 330:
523 fd3_screen_init(pscreen);
524 break;
525 case 420:
526 fd4_screen_init(pscreen);
527 break;
528 default:
529 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
530 goto fail;
531 }
532
533 pscreen->destroy = fd_screen_destroy;
534 pscreen->get_param = fd_screen_get_param;
535 pscreen->get_paramf = fd_screen_get_paramf;
536 pscreen->get_shader_param = fd_screen_get_shader_param;
537
538 fd_resource_screen_init(pscreen);
539 fd_query_screen_init(pscreen);
540
541 pscreen->get_name = fd_screen_get_name;
542 pscreen->get_vendor = fd_screen_get_vendor;
543 pscreen->get_device_vendor = fd_screen_get_device_vendor;
544
545 pscreen->get_timestamp = fd_screen_get_timestamp;
546
547 pscreen->fence_reference = fd_screen_fence_ref;
548 pscreen->fence_signalled = fd_screen_fence_signalled;
549 pscreen->fence_finish = fd_screen_fence_finish;
550
551 util_format_s3tc_init();
552
553 return pscreen;
554
555 fail:
556 fd_screen_destroy(pscreen);
557 return NULL;
558 }