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6a44d7543d1800a757f1b722e01aefd608a68ed7
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
40
41 #include "util/os_time.h"
42
43 #include <stdio.h>
44 #include <errno.h>
45 #include <stdlib.h>
46
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
52
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57
58 #include "ir3/ir3_nir.h"
59
60 /* XXX this should go away */
61 #include "state_tracker/drm_driver.h"
62
63 static const struct debug_named_value debug_options[] = {
64 {"msgs", FD_DBG_MSGS, "Print debug messages"},
65 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
66 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
67 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
68 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
69 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
70 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
71 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
72 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
73 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
74 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
75 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
76 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
77 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
78 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
79 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
80 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
81 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"},
82 DEBUG_NAMED_VALUE_END
83 };
84
85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
86
87 int fd_mesa_debug = 0;
88 bool fd_binning_enabled = true;
89 static bool glsl120 = false;
90
91 static const char *
92 fd_screen_get_name(struct pipe_screen *pscreen)
93 {
94 static char buffer[128];
95 util_snprintf(buffer, sizeof(buffer), "FD%03d",
96 fd_screen(pscreen)->device_id);
97 return buffer;
98 }
99
100 static const char *
101 fd_screen_get_vendor(struct pipe_screen *pscreen)
102 {
103 return "freedreno";
104 }
105
106 static const char *
107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
108 {
109 return "Qualcomm";
110 }
111
112
113 static uint64_t
114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
115 {
116 struct fd_screen *screen = fd_screen(pscreen);
117
118 if (screen->has_timestamp) {
119 uint64_t n;
120 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
121 debug_assert(screen->max_freq > 0);
122 return n * 1000000000 / screen->max_freq;
123 } else {
124 int64_t cpu_time = os_time_get() * 1000;
125 return cpu_time + screen->cpu_gpu_time_delta;
126 }
127
128 }
129
130 static void
131 fd_screen_destroy(struct pipe_screen *pscreen)
132 {
133 struct fd_screen *screen = fd_screen(pscreen);
134
135 if (screen->pipe)
136 fd_pipe_del(screen->pipe);
137
138 if (screen->dev)
139 fd_device_del(screen->dev);
140
141 fd_bc_fini(&screen->batch_cache);
142
143 slab_destroy_parent(&screen->transfer_pool);
144
145 mtx_destroy(&screen->lock);
146
147 ralloc_free(screen->compiler);
148
149 free(screen);
150 }
151
152 /*
153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
154 tables for things that differ if the delta is not too much..
155 */
156 static int
157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
158 {
159 struct fd_screen *screen = fd_screen(pscreen);
160
161 /* this is probably not totally correct.. but it's a start: */
162 switch (param) {
163 /* Supported features (boolean caps). */
164 case PIPE_CAP_NPOT_TEXTURES:
165 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
166 case PIPE_CAP_TWO_SIDED_STENCIL:
167 case PIPE_CAP_ANISOTROPIC_FILTER:
168 case PIPE_CAP_POINT_SPRITE:
169 case PIPE_CAP_TEXTURE_SHADOW_MAP:
170 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
171 case PIPE_CAP_TEXTURE_SWIZZLE:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
173 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP:
176 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
177 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
178 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
179 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
180 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
182 case PIPE_CAP_STRING_MARKER:
183 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
184 case PIPE_CAP_TEXTURE_BARRIER:
185 case PIPE_CAP_INVALIDATE_BUFFER:
186 return 1;
187
188 case PIPE_CAP_VERTEXID_NOBASE:
189 return is_a3xx(screen) || is_a4xx(screen);
190
191 case PIPE_CAP_USER_CONSTANT_BUFFERS:
192 return is_a4xx(screen) ? 0 : 1;
193
194 case PIPE_CAP_COMPUTE:
195 return has_compute(screen);
196
197 case PIPE_CAP_SHADER_STENCIL_EXPORT:
198 case PIPE_CAP_TGSI_TEXCOORD:
199 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
200 case PIPE_CAP_TEXTURE_MULTISAMPLE:
201 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
202 case PIPE_CAP_QUERY_MEMORY_INFO:
203 case PIPE_CAP_PCI_GROUP:
204 case PIPE_CAP_PCI_BUS:
205 case PIPE_CAP_PCI_DEVICE:
206 case PIPE_CAP_PCI_FUNCTION:
207 return 0;
208
209 case PIPE_CAP_SM3:
210 case PIPE_CAP_PRIMITIVE_RESTART:
211 case PIPE_CAP_TGSI_INSTANCEID:
212 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
213 case PIPE_CAP_INDEP_BLEND_ENABLE:
214 case PIPE_CAP_INDEP_BLEND_FUNC:
215 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
216 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
217 case PIPE_CAP_CONDITIONAL_RENDER:
218 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
219 case PIPE_CAP_FAKE_SW_MSAA:
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
221 case PIPE_CAP_CLIP_HALFZ:
222 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
223
224 case PIPE_CAP_DEPTH_CLIP_DISABLE:
225 return is_a3xx(screen) || is_a4xx(screen);
226
227 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
228 return is_a5xx(screen);
229
230 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
231 return 0;
232 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
233 if (is_a3xx(screen)) return 16;
234 if (is_a4xx(screen)) return 32;
235 if (is_a5xx(screen)) return 32;
236 return 0;
237 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
238 /* We could possibly emulate more by pretending 2d/rect textures and
239 * splitting high bits of index into 2nd dimension..
240 */
241 if (is_a3xx(screen)) return 8192;
242 if (is_a4xx(screen)) return 16384;
243 if (is_a5xx(screen)) return 16384;
244 return 0;
245
246 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
247 case PIPE_CAP_CUBE_MAP_ARRAY:
248 case PIPE_CAP_START_INSTANCE:
249 case PIPE_CAP_SAMPLER_VIEW_TARGET:
250 case PIPE_CAP_TEXTURE_QUERY_LOD:
251 return is_a4xx(screen) || is_a5xx(screen);
252
253 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
254 return 64;
255
256 case PIPE_CAP_GLSL_FEATURE_LEVEL:
257 if (glsl120)
258 return 120;
259 return is_ir3(screen) ? 140 : 120;
260
261 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
262 if (is_a5xx(screen))
263 return 4;
264 return 0;
265
266 /* Unsupported features. */
267 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
268 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
269 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
270 case PIPE_CAP_USER_VERTEX_BUFFERS:
271 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
272 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
273 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
274 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
275 case PIPE_CAP_TEXTURE_GATHER_SM5:
276 case PIPE_CAP_SAMPLE_SHADING:
277 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
278 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
279 case PIPE_CAP_DRAW_INDIRECT:
280 case PIPE_CAP_MULTI_DRAW_INDIRECT:
281 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
282 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
283 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
284 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
285 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
286 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
287 case PIPE_CAP_DEPTH_BOUNDS_TEST:
288 case PIPE_CAP_TGSI_TXQS:
289 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
290 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
291 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
292 case PIPE_CAP_CLEAR_TEXTURE:
293 case PIPE_CAP_DRAW_PARAMETERS:
294 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
295 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
296 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
297 case PIPE_CAP_GENERATE_MIPMAP:
298 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
299 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
300 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
301 case PIPE_CAP_CULL_DISTANCE:
302 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
303 case PIPE_CAP_TGSI_VOTE:
304 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
305 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
306 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
307 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
308 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
309 case PIPE_CAP_TGSI_FS_FBFETCH:
310 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
311 case PIPE_CAP_DOUBLES:
312 case PIPE_CAP_INT64:
313 case PIPE_CAP_INT64_DIVMOD:
314 case PIPE_CAP_TGSI_TEX_TXF_LZ:
315 case PIPE_CAP_TGSI_CLOCK:
316 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
317 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
318 case PIPE_CAP_TGSI_BALLOT:
319 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
320 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
321 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
322 case PIPE_CAP_POST_DEPTH_COVERAGE:
323 case PIPE_CAP_BINDLESS_TEXTURE:
324 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
325 case PIPE_CAP_QUERY_SO_OVERFLOW:
326 case PIPE_CAP_MEMOBJ:
327 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
328 case PIPE_CAP_TILE_RASTER_ORDER:
329 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
330 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
331 return 0;
332
333 case PIPE_CAP_LOAD_CONSTBUF:
334 /* name is confusing, but this turns on std430 packing */
335 if (is_ir3(screen))
336 return 1;
337 return 0;
338
339 case PIPE_CAP_MAX_VIEWPORTS:
340 return 1;
341
342 case PIPE_CAP_SHAREABLE_SHADERS:
343 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
344 /* manage the variants for these ourself, to avoid breaking precompile: */
345 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
346 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
347 if (is_ir3(screen))
348 return 1;
349 return 0;
350
351 /* Stream output. */
352 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
353 if (is_ir3(screen))
354 return PIPE_MAX_SO_BUFFERS;
355 return 0;
356 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
357 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
358 if (is_ir3(screen))
359 return 1;
360 return 0;
361 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
362 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
363 if (is_ir3(screen))
364 return 16 * 4; /* should only be shader out limit? */
365 return 0;
366
367 /* Geometry shader output, unsupported. */
368 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
369 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
370 case PIPE_CAP_MAX_VERTEX_STREAMS:
371 return 0;
372
373 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
374 return 2048;
375
376 /* Texturing. */
377 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
378 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
379 return MAX_MIP_LEVELS;
380 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
381 return 11;
382
383 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
384 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
385
386 /* Render targets. */
387 case PIPE_CAP_MAX_RENDER_TARGETS:
388 return screen->max_rts;
389 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
390 return is_a3xx(screen) ? 1 : 0;
391
392 /* Queries. */
393 case PIPE_CAP_QUERY_BUFFER_OBJECT:
394 return 0;
395 case PIPE_CAP_OCCLUSION_QUERY:
396 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
397 case PIPE_CAP_QUERY_TIMESTAMP:
398 case PIPE_CAP_QUERY_TIME_ELAPSED:
399 /* only a4xx, requires new enough kernel so we know max_freq: */
400 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
401
402 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
403 case PIPE_CAP_MIN_TEXEL_OFFSET:
404 return -8;
405
406 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
407 case PIPE_CAP_MAX_TEXEL_OFFSET:
408 return 7;
409
410 case PIPE_CAP_ENDIANNESS:
411 return PIPE_ENDIAN_LITTLE;
412
413 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
414 return 64;
415
416 case PIPE_CAP_VENDOR_ID:
417 return 0x5143;
418 case PIPE_CAP_DEVICE_ID:
419 return 0xFFFFFFFF;
420 case PIPE_CAP_ACCELERATED:
421 return 1;
422 case PIPE_CAP_VIDEO_MEMORY:
423 DBG("FINISHME: The value returned is incorrect\n");
424 return 10;
425 case PIPE_CAP_UMA:
426 return 1;
427 case PIPE_CAP_NATIVE_FENCE_FD:
428 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
429 }
430 debug_printf("unknown param %d\n", param);
431 return 0;
432 }
433
434 static float
435 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
436 {
437 switch (param) {
438 case PIPE_CAPF_MAX_LINE_WIDTH:
439 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
440 /* NOTE: actual value is 127.0f, but this is working around a deqp
441 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
442 * uses too small of a render target size, and gets confused when
443 * the lines start going offscreen.
444 *
445 * See: https://code.google.com/p/android/issues/detail?id=206513
446 */
447 if (fd_mesa_debug & FD_DBG_DEQP)
448 return 48.0f;
449 return 127.0f;
450 case PIPE_CAPF_MAX_POINT_WIDTH:
451 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
452 return 4092.0f;
453 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
454 return 16.0f;
455 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
456 return 15.0f;
457 case PIPE_CAPF_GUARD_BAND_LEFT:
458 case PIPE_CAPF_GUARD_BAND_TOP:
459 case PIPE_CAPF_GUARD_BAND_RIGHT:
460 case PIPE_CAPF_GUARD_BAND_BOTTOM:
461 return 0.0f;
462 }
463 debug_printf("unknown paramf %d\n", param);
464 return 0;
465 }
466
467 static int
468 fd_screen_get_shader_param(struct pipe_screen *pscreen,
469 enum pipe_shader_type shader,
470 enum pipe_shader_cap param)
471 {
472 struct fd_screen *screen = fd_screen(pscreen);
473
474 switch(shader)
475 {
476 case PIPE_SHADER_FRAGMENT:
477 case PIPE_SHADER_VERTEX:
478 break;
479 case PIPE_SHADER_COMPUTE:
480 if (has_compute(screen))
481 break;
482 return 0;
483 case PIPE_SHADER_GEOMETRY:
484 /* maye we could emulate.. */
485 return 0;
486 default:
487 DBG("unknown shader type %d", shader);
488 return 0;
489 }
490
491 /* this is probably not totally correct.. but it's a start: */
492 switch (param) {
493 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
494 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
495 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
496 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
497 return 16384;
498 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
499 return 8; /* XXX */
500 case PIPE_SHADER_CAP_MAX_INPUTS:
501 case PIPE_SHADER_CAP_MAX_OUTPUTS:
502 return 16;
503 case PIPE_SHADER_CAP_MAX_TEMPS:
504 return 64; /* Max native temporaries. */
505 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
506 /* NOTE: seems to be limit for a3xx is actually 512 but
507 * split between VS and FS. Use lower limit of 256 to
508 * avoid getting into impossible situations:
509 */
510 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
511 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
512 return is_ir3(screen) ? 16 : 1;
513 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
514 return 1;
515 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
516 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
517 /* Technically this should be the same as for TEMP/CONST, since
518 * everything is just normal registers. This is just temporary
519 * hack until load_input/store_output handle arrays in a similar
520 * way as load_var/store_var..
521 */
522 return 0;
523 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
524 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
525 /* a2xx compiler doesn't handle indirect: */
526 return is_ir3(screen) ? 1 : 0;
527 case PIPE_SHADER_CAP_SUBROUTINES:
528 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
529 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
530 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
531 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
532 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
533 return 0;
534 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
535 return 1;
536 case PIPE_SHADER_CAP_INTEGERS:
537 if (glsl120)
538 return 0;
539 return is_ir3(screen) ? 1 : 0;
540 case PIPE_SHADER_CAP_INT64_ATOMICS:
541 return 0;
542 case PIPE_SHADER_CAP_FP16:
543 return 0;
544 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
545 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
546 return 16;
547 case PIPE_SHADER_CAP_PREFERRED_IR:
548 if (is_ir3(screen))
549 return PIPE_SHADER_IR_NIR;
550 return PIPE_SHADER_IR_TGSI;
551 case PIPE_SHADER_CAP_SUPPORTED_IRS:
552 if (is_ir3(screen)) {
553 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
554 } else {
555 return (1 << PIPE_SHADER_IR_TGSI);
556 }
557 return 0;
558 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
559 return 32;
560 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
561 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
562 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
563 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
564 return 0;
565 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
566 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
567 if (is_a5xx(screen)) {
568 /* a5xx (and a4xx for that matter) has one state-block
569 * for compute-shader SSBO's and another that is shared
570 * by VS/HS/DS/GS/FS.. so to simplify things for now
571 * just advertise SSBOs for FS and CS. We could possibly
572 * do what blob does, and partition the space for
573 * VS/HS/DS/GS/FS. The blob advertises:
574 *
575 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
576 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
577 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
578 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
579 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
580 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
581 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
582 *
583 * I think that way we could avoid having to patch shaders
584 * for actual SSBO indexes by using a static partitioning.
585 *
586 * Note same state block is used for images and buffers,
587 * but images also need texture state for read access
588 * (isam/isam.3d)
589 */
590 switch(shader)
591 {
592 case PIPE_SHADER_FRAGMENT:
593 case PIPE_SHADER_COMPUTE:
594 return 24;
595 default:
596 return 0;
597 }
598 }
599 return 0;
600 }
601 debug_printf("unknown shader param %d\n", param);
602 return 0;
603 }
604
605 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
606 * into per-generation backend?
607 */
608 static int
609 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
610 enum pipe_compute_cap param, void *ret)
611 {
612 struct fd_screen *screen = fd_screen(pscreen);
613 const char * const ir = "ir3";
614
615 if (!has_compute(screen))
616 return 0;
617
618 switch (param) {
619 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
620 if (ret) {
621 uint32_t *address_bits = ret;
622 address_bits[0] = 32;
623
624 if (is_a5xx(screen))
625 address_bits[0] = 64;
626 }
627 return 1 * sizeof(uint32_t);
628
629 case PIPE_COMPUTE_CAP_IR_TARGET:
630 if (ret)
631 sprintf(ret, ir);
632 return strlen(ir) * sizeof(char);
633
634 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
635 if (ret) {
636 uint64_t *grid_dimension = ret;
637 grid_dimension[0] = 3;
638 }
639 return 1 * sizeof(uint64_t);
640
641 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
642 if (ret) {
643 uint64_t *grid_size = ret;
644 grid_size[0] = 65535;
645 grid_size[1] = 65535;
646 grid_size[2] = 65535;
647 }
648 return 3 * sizeof(uint64_t) ;
649
650 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
651 if (ret) {
652 uint64_t *block_size = ret;
653 block_size[0] = 1024;
654 block_size[1] = 1024;
655 block_size[2] = 64;
656 }
657 return 3 * sizeof(uint64_t) ;
658
659 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
660 if (ret) {
661 uint64_t *max_threads_per_block = ret;
662 *max_threads_per_block = 1024;
663 }
664 return sizeof(uint64_t);
665
666 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
667 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
668 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
669 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
670 break;
671 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
672 if (ret) {
673 uint64_t *max = ret;
674 *max = 32768;
675 }
676 return sizeof(uint64_t);
677 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
678 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
679 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
680 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
681 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
682 break;
683 }
684
685 return 0;
686 }
687
688 static const void *
689 fd_get_compiler_options(struct pipe_screen *pscreen,
690 enum pipe_shader_ir ir, unsigned shader)
691 {
692 struct fd_screen *screen = fd_screen(pscreen);
693
694 if (is_ir3(screen))
695 return ir3_get_compiler_options(screen->compiler);
696
697 return NULL;
698 }
699
700 boolean
701 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
702 struct fd_bo *bo,
703 unsigned stride,
704 struct winsys_handle *whandle)
705 {
706 whandle->stride = stride;
707
708 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
709 return fd_bo_get_name(bo, &whandle->handle) == 0;
710 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
711 whandle->handle = fd_bo_handle(bo);
712 return TRUE;
713 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
714 whandle->handle = fd_bo_dmabuf(bo);
715 return TRUE;
716 } else {
717 return FALSE;
718 }
719 }
720
721 struct fd_bo *
722 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
723 struct winsys_handle *whandle)
724 {
725 struct fd_screen *screen = fd_screen(pscreen);
726 struct fd_bo *bo;
727
728 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
729 bo = fd_bo_from_name(screen->dev, whandle->handle);
730 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
731 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
732 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
733 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
734 } else {
735 DBG("Attempt to import unsupported handle type %d", whandle->type);
736 return NULL;
737 }
738
739 if (!bo) {
740 DBG("ref name 0x%08x failed", whandle->handle);
741 return NULL;
742 }
743
744 return bo;
745 }
746
747 struct pipe_screen *
748 fd_screen_create(struct fd_device *dev)
749 {
750 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
751 struct pipe_screen *pscreen;
752 uint64_t val;
753
754 fd_mesa_debug = debug_get_option_fd_mesa_debug();
755
756 if (fd_mesa_debug & FD_DBG_NOBIN)
757 fd_binning_enabled = false;
758
759 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
760
761 if (!screen)
762 return NULL;
763
764 pscreen = &screen->base;
765
766 screen->dev = dev;
767 screen->refcnt = 1;
768
769 // maybe this should be in context?
770 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
771 if (!screen->pipe) {
772 DBG("could not create 3d pipe");
773 goto fail;
774 }
775
776 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
777 DBG("could not get GMEM size");
778 goto fail;
779 }
780 screen->gmemsize_bytes = val;
781
782 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
783 DBG("could not get device-id");
784 goto fail;
785 }
786 screen->device_id = val;
787
788 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
789 DBG("could not get gpu freq");
790 /* this limits what performance related queries are
791 * supported but is not fatal
792 */
793 screen->max_freq = 0;
794 } else {
795 screen->max_freq = val;
796 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
797 screen->has_timestamp = true;
798 }
799
800 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
801 DBG("could not get gpu-id");
802 goto fail;
803 }
804 screen->gpu_id = val;
805
806 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
807 DBG("could not get chip-id");
808 /* older kernels may not have this property: */
809 unsigned core = screen->gpu_id / 100;
810 unsigned major = (screen->gpu_id % 100) / 10;
811 unsigned minor = screen->gpu_id % 10;
812 unsigned patch = 0; /* assume the worst */
813 val = (patch & 0xff) | ((minor & 0xff) << 8) |
814 ((major & 0xff) << 16) | ((core & 0xff) << 24);
815 }
816 screen->chip_id = val;
817
818 DBG("Pipe Info:");
819 DBG(" GPU-id: %d", screen->gpu_id);
820 DBG(" Chip-id: 0x%08x", screen->chip_id);
821 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
822
823 /* explicitly checking for GPU revisions that are known to work. This
824 * may be overly conservative for a3xx, where spoofing the gpu_id with
825 * the blob driver seems to generate identical cmdstream dumps. But
826 * on a2xx, there seem to be small differences between the GPU revs
827 * so it is probably better to actually test first on real hardware
828 * before enabling:
829 *
830 * If you have a different adreno version, feel free to add it to one
831 * of the cases below and see what happens. And if it works, please
832 * send a patch ;-)
833 */
834 switch (screen->gpu_id) {
835 case 220:
836 fd2_screen_init(pscreen);
837 break;
838 case 305:
839 case 307:
840 case 320:
841 case 330:
842 fd3_screen_init(pscreen);
843 break;
844 case 420:
845 case 430:
846 fd4_screen_init(pscreen);
847 break;
848 case 530:
849 fd5_screen_init(pscreen);
850 break;
851 default:
852 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
853 goto fail;
854 }
855
856 if (screen->gpu_id >= 500) {
857 screen->gmem_alignw = 64;
858 screen->gmem_alignh = 32;
859 screen->num_vsc_pipes = 16;
860 } else {
861 screen->gmem_alignw = 32;
862 screen->gmem_alignh = 32;
863 screen->num_vsc_pipes = 8;
864 }
865
866 /* NOTE: don't enable reordering on a2xx, since completely untested.
867 * Also, don't enable if we have too old of a kernel to support
868 * growable cmdstream buffers, since memory requirement for cmdstream
869 * buffers would be too much otherwise.
870 */
871 if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
872 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
873
874 fd_bc_init(&screen->batch_cache);
875
876 (void) mtx_init(&screen->lock, mtx_plain);
877
878 pscreen->destroy = fd_screen_destroy;
879 pscreen->get_param = fd_screen_get_param;
880 pscreen->get_paramf = fd_screen_get_paramf;
881 pscreen->get_shader_param = fd_screen_get_shader_param;
882 pscreen->get_compute_param = fd_get_compute_param;
883 pscreen->get_compiler_options = fd_get_compiler_options;
884
885 fd_resource_screen_init(pscreen);
886 fd_query_screen_init(pscreen);
887
888 pscreen->get_name = fd_screen_get_name;
889 pscreen->get_vendor = fd_screen_get_vendor;
890 pscreen->get_device_vendor = fd_screen_get_device_vendor;
891
892 pscreen->get_timestamp = fd_screen_get_timestamp;
893
894 pscreen->fence_reference = fd_fence_ref;
895 pscreen->fence_finish = fd_fence_finish;
896 pscreen->fence_get_fd = fd_fence_get_fd;
897
898 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
899
900 return pscreen;
901
902 fail:
903 fd_screen_destroy(pscreen);
904 return NULL;
905 }