src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 /* XXX this should go away */
  58 #include "state_tracker/drm_driver.h"
  59
  60 static const struct debug_named_value debug_options[] = {
  61                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  62                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  63                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  64                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  65                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  66                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  67                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  68                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  69                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  71                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  72                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  73                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  74                 DEBUG_NAMED_VALUE_END
  75 };
  76
  77 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  78
  79 int fd_mesa_debug = 0;
  80 bool fd_binning_enabled = true;
  81 static bool glsl120 = false;
  82
  83 static const char *
  84 fd_screen_get_name(struct pipe_screen *pscreen)
  85 {
  86         static char buffer[128];
  87         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  88                         fd_screen(pscreen)->device_id);
  89         return buffer;
  90 }
  91
  92 static const char *
  93 fd_screen_get_vendor(struct pipe_screen *pscreen)
  94 {
  95         return "freedreno";
  96 }
  97
  98 static const char *
  99 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 100 {
 101         return "Qualcomm";
 102 }
 103
 104
 105 static uint64_t
 106 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 107 {
 108         int64_t cpu_time = os_time_get() * 1000;
 109         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 110 }
 111
 112 static void
 113 fd_screen_destroy(struct pipe_screen *pscreen)
 114 {
 115         struct fd_screen *screen = fd_screen(pscreen);
 116
 117         if (screen->pipe)
 118                 fd_pipe_del(screen->pipe);
 119
 120         if (screen->dev)
 121                 fd_device_del(screen->dev);
 122
 123         free(screen);
 124 }
 125
 126 /*
 127 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 128 tables for things that differ if the delta is not too much..
 129  */
 130 static int
 131 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         /* this is probably not totally correct.. but it's a start: */
 136         switch (param) {
 137         /* Supported features (boolean caps). */
 138         case PIPE_CAP_NPOT_TEXTURES:
 139         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 140         case PIPE_CAP_TWO_SIDED_STENCIL:
 141         case PIPE_CAP_ANISOTROPIC_FILTER:
 142         case PIPE_CAP_POINT_SPRITE:
 143         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 144         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 145         case PIPE_CAP_TEXTURE_SWIZZLE:
 146         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 148         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 149         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 150         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 151         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 152         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 153         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 154         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 155         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 156         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 157         case PIPE_CAP_VERTEXID_NOBASE:
 158         case PIPE_CAP_STRING_MARKER:
 159                 return 1;
 160
 161         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 162         case PIPE_CAP_TGSI_TEXCOORD:
 163         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 164         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 165         case PIPE_CAP_TEXTURE_BARRIER:
 166         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 167         case PIPE_CAP_COMPUTE:
 168         case PIPE_CAP_QUERY_MEMORY_INFO:
 169         case PIPE_CAP_PCI_GROUP:
 170         case PIPE_CAP_PCI_BUS:
 171         case PIPE_CAP_PCI_DEVICE:
 172         case PIPE_CAP_PCI_FUNCTION:
 173                 return 0;
 174
 175         case PIPE_CAP_SM3:
 176         case PIPE_CAP_PRIMITIVE_RESTART:
 177         case PIPE_CAP_TGSI_INSTANCEID:
 178         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 179         case PIPE_CAP_INDEP_BLEND_ENABLE:
 180         case PIPE_CAP_INDEP_BLEND_FUNC:
 181         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 182         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 183         case PIPE_CAP_CONDITIONAL_RENDER:
 184         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 185         case PIPE_CAP_FAKE_SW_MSAA:
 186         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 187         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 188         case PIPE_CAP_CLIP_HALFZ:
 189                 return is_a3xx(screen) || is_a4xx(screen);
 190
 191         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 192                 return 0;
 193         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 194                 if (is_a3xx(screen)) return 16;
 195                 if (is_a4xx(screen)) return 32;
 196                 return 0;
 197         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 198                 /* We could possibly emulate more by pretending 2d/rect textures and
 199                  * splitting high bits of index into 2nd dimension..
 200                  */
 201                 if (is_a3xx(screen)) return 8192;
 202                 if (is_a4xx(screen)) return 16384;
 203                 return 0;
 204
 205         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 206         case PIPE_CAP_CUBE_MAP_ARRAY:
 207         case PIPE_CAP_START_INSTANCE:
 208         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 209         case PIPE_CAP_TEXTURE_QUERY_LOD:
 210                 return is_a4xx(screen);
 211
 212         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 213                 return 256;
 214
 215         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 216                 if (glsl120)
 217                         return 120;
 218                 return is_ir3(screen) ? 140 : 120;
 219
 220         /* Unsupported features. */
 221         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 222         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 223         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 224         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 225         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 226         case PIPE_CAP_USER_VERTEX_BUFFERS:
 227         case PIPE_CAP_USER_INDEX_BUFFERS:
 228         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 229         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 230         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 231         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 232         case PIPE_CAP_TEXTURE_GATHER_SM5:
 233         case PIPE_CAP_SAMPLE_SHADING:
 234         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 235         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 236         case PIPE_CAP_DRAW_INDIRECT:
 237         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 238         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 239         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 240         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 241         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 242         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 243         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 244         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 245         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 246         case PIPE_CAP_TGSI_TXQS:
 247         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 248         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 249         case PIPE_CAP_CLEAR_TEXTURE:
 250         case PIPE_CAP_DRAW_PARAMETERS:
 251         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 252         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 253         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 254         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 255         case PIPE_CAP_INVALIDATE_BUFFER:
 256         case PIPE_CAP_GENERATE_MIPMAP:
 257         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 258         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 259                 return 0;
 260
 261         case PIPE_CAP_MAX_VIEWPORTS:
 262                 return 1;
 263
 264         case PIPE_CAP_SHAREABLE_SHADERS:
 265                 if (is_ir3(screen))
 266                         return 1;
 267                 return 0;
 268
 269         /* Stream output. */
 270         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 271                 if (is_ir3(screen))
 272                         return PIPE_MAX_SO_BUFFERS;
 273                 return 0;
 274         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 275                 if (is_ir3(screen))
 276                         return 1;
 277                 return 0;
 278         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 279         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 280                 if (is_ir3(screen))
 281                         return 16 * 4;   /* should only be shader out limit? */
 282                 return 0;
 283
 284         /* Geometry shader output, unsupported. */
 285         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 286         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 287         case PIPE_CAP_MAX_VERTEX_STREAMS:
 288                 return 0;
 289
 290         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 291                 return 2048;
 292
 293         /* Texturing. */
 294         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 295         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 296                 return MAX_MIP_LEVELS;
 297         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 298                 return 11;
 299
 300         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 301                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 302
 303         /* Render targets. */
 304         case PIPE_CAP_MAX_RENDER_TARGETS:
 305                 return screen->max_rts;
 306         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 307                 return is_a3xx(screen) ? 1 : 0;
 308
 309         /* Queries. */
 310         case PIPE_CAP_QUERY_TIMESTAMP:
 311         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 312                 return 0;
 313         case PIPE_CAP_OCCLUSION_QUERY:
 314                 return is_a3xx(screen) || is_a4xx(screen);
 315         case PIPE_CAP_QUERY_TIME_ELAPSED:
 316                 /* only a4xx, requires new enough kernel so we know max_freq: */
 317                 return (screen->max_freq > 0) && is_a4xx(screen);
 318
 319         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 320         case PIPE_CAP_MIN_TEXEL_OFFSET:
 321                 return -8;
 322
 323         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 324         case PIPE_CAP_MAX_TEXEL_OFFSET:
 325                 return 7;
 326
 327         case PIPE_CAP_ENDIANNESS:
 328                 return PIPE_ENDIAN_LITTLE;
 329
 330         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 331                 return 64;
 332
 333         case PIPE_CAP_VENDOR_ID:
 334                 return 0x5143;
 335         case PIPE_CAP_DEVICE_ID:
 336                 return 0xFFFFFFFF;
 337         case PIPE_CAP_ACCELERATED:
 338                 return 1;
 339         case PIPE_CAP_VIDEO_MEMORY:
 340                 DBG("FINISHME: The value returned is incorrect\n");
 341                 return 10;
 342         case PIPE_CAP_UMA:
 343                 return 1;
 344         }
 345         debug_printf("unknown param %d\n", param);
 346         return 0;
 347 }
 348
 349 static float
 350 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 351 {
 352         switch (param) {
 353         case PIPE_CAPF_MAX_LINE_WIDTH:
 354         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 355         case PIPE_CAPF_MAX_POINT_WIDTH:
 356         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 357                 return 4092.0f;
 358         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 359                 return 16.0f;
 360         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 361                 return 15.0f;
 362         case PIPE_CAPF_GUARD_BAND_LEFT:
 363         case PIPE_CAPF_GUARD_BAND_TOP:
 364         case PIPE_CAPF_GUARD_BAND_RIGHT:
 365         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 366                 return 0.0f;
 367         }
 368         debug_printf("unknown paramf %d\n", param);
 369         return 0;
 370 }
 371
 372 static int
 373 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 374                 enum pipe_shader_cap param)
 375 {
 376         struct fd_screen *screen = fd_screen(pscreen);
 377
 378         switch(shader)
 379         {
 380         case PIPE_SHADER_FRAGMENT:
 381         case PIPE_SHADER_VERTEX:
 382                 break;
 383         case PIPE_SHADER_COMPUTE:
 384         case PIPE_SHADER_GEOMETRY:
 385                 /* maye we could emulate.. */
 386                 return 0;
 387         default:
 388                 DBG("unknown shader type %d", shader);
 389                 return 0;
 390         }
 391
 392         /* this is probably not totally correct.. but it's a start: */
 393         switch (param) {
 394         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 395         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 396         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 397         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 398                 return 16384;
 399         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 400                 return 8; /* XXX */
 401         case PIPE_SHADER_CAP_MAX_INPUTS:
 402         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 403                 return 16;
 404         case PIPE_SHADER_CAP_MAX_TEMPS:
 405                 return 64; /* Max native temporaries. */
 406         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 407                 /* NOTE: seems to be limit for a3xx is actually 512 but
 408                  * split between VS and FS.  Use lower limit of 256 to
 409                  * avoid getting into impossible situations:
 410                  */
 411                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 412         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 413                 return is_ir3(screen) ? 16 : 1;
 414         case PIPE_SHADER_CAP_MAX_PREDS:
 415                 return 0; /* nothing uses this */
 416         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 417                 return 1;
 418         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 419         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 420                 /* Technically this should be the same as for TEMP/CONST, since
 421                  * everything is just normal registers.  This is just temporary
 422                  * hack until load_input/store_output handle arrays in a similar
 423                  * way as load_var/store_var..
 424                  */
 425                 return 0;
 426         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 427         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 428                 /* a2xx compiler doesn't handle indirect: */
 429                 return is_ir3(screen) ? 1 : 0;
 430         case PIPE_SHADER_CAP_SUBROUTINES:
 431         case PIPE_SHADER_CAP_DOUBLES:
 432         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 433         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 434         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 435         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 436                 return 0;
 437         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 438                 return 1;
 439         case PIPE_SHADER_CAP_INTEGERS:
 440                 if (glsl120)
 441                         return 0;
 442                 return is_ir3(screen) ? 1 : 0;
 443         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 444         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 445                 return 16;
 446         case PIPE_SHADER_CAP_PREFERRED_IR:
 447                 return PIPE_SHADER_IR_TGSI;
 448         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 449                 return 0;
 450         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 451                 return 32;
 452         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 453         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 454                 return 0;
 455         }
 456         debug_printf("unknown shader param %d\n", param);
 457         return 0;
 458 }
 459
 460 boolean
 461 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 462                 struct fd_bo *bo,
 463                 unsigned stride,
 464                 struct winsys_handle *whandle)
 465 {
 466         whandle->stride = stride;
 467
 468         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 469                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 470         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 471                 whandle->handle = fd_bo_handle(bo);
 472                 return TRUE;
 473         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 474                 whandle->handle = fd_bo_dmabuf(bo);
 475                 return TRUE;
 476         } else {
 477                 return FALSE;
 478         }
 479 }
 480
 481 struct fd_bo *
 482 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 483                 struct winsys_handle *whandle,
 484                 unsigned *out_stride)
 485 {
 486         struct fd_screen *screen = fd_screen(pscreen);
 487         struct fd_bo *bo;
 488
 489         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 490                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 491         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 492                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 493         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 494                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 495         } else {
 496                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 497                 return NULL;
 498         }
 499
 500         if (!bo) {
 501                 DBG("ref name 0x%08x failed", whandle->handle);
 502                 return NULL;
 503         }
 504
 505         *out_stride = whandle->stride;
 506
 507         return bo;
 508 }
 509
 510 struct pipe_screen *
 511 fd_screen_create(struct fd_device *dev)
 512 {
 513         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 514         struct pipe_screen *pscreen;
 515         uint64_t val;
 516
 517         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 518
 519         if (fd_mesa_debug & FD_DBG_NOBIN)
 520                 fd_binning_enabled = false;
 521
 522         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 523
 524         if (!screen)
 525                 return NULL;
 526
 527         pscreen = &screen->base;
 528
 529         screen->dev = dev;
 530         screen->refcnt = 1;
 531
 532         // maybe this should be in context?
 533         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 534         if (!screen->pipe) {
 535                 DBG("could not create 3d pipe");
 536                 goto fail;
 537         }
 538
 539         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 540                 DBG("could not get GMEM size");
 541                 goto fail;
 542         }
 543         screen->gmemsize_bytes = val;
 544
 545         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 546                 DBG("could not get device-id");
 547                 goto fail;
 548         }
 549         screen->device_id = val;
 550
 551         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 552                 DBG("could not get gpu freq");
 553                 /* this limits what performance related queries are
 554                  * supported but is not fatal
 555                  */
 556                 screen->max_freq = 0;
 557         } else {
 558                 screen->max_freq = val;
 559         }
 560
 561         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 562                 DBG("could not get gpu-id");
 563                 goto fail;
 564         }
 565         screen->gpu_id = val;
 566
 567         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 568                 DBG("could not get chip-id");
 569                 /* older kernels may not have this property: */
 570                 unsigned core  = screen->gpu_id / 100;
 571                 unsigned major = (screen->gpu_id % 100) / 10;
 572                 unsigned minor = screen->gpu_id % 10;
 573                 unsigned patch = 0;  /* assume the worst */
 574                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 575                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 576         }
 577         screen->chip_id = val;
 578
 579         DBG("Pipe Info:");
 580         DBG(" GPU-id:          %d", screen->gpu_id);
 581         DBG(" Chip-id:         0x%08x", screen->chip_id);
 582         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 583
 584         /* explicitly checking for GPU revisions that are known to work.  This
 585          * may be overly conservative for a3xx, where spoofing the gpu_id with
 586          * the blob driver seems to generate identical cmdstream dumps.  But
 587          * on a2xx, there seem to be small differences between the GPU revs
 588          * so it is probably better to actually test first on real hardware
 589          * before enabling:
 590          *
 591          * If you have a different adreno version, feel free to add it to one
 592          * of the cases below and see what happens.  And if it works, please
 593          * send a patch ;-)
 594          */
 595         switch (screen->gpu_id) {
 596         case 220:
 597                 fd2_screen_init(pscreen);
 598                 break;
 599         case 305:
 600         case 307:
 601         case 320:
 602         case 330:
 603                 fd3_screen_init(pscreen);
 604                 break;
 605         case 420:
 606         case 430:
 607                 fd4_screen_init(pscreen);
 608                 break;
 609         default:
 610                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 611                 goto fail;
 612         }
 613
 614         pscreen->destroy = fd_screen_destroy;
 615         pscreen->get_param = fd_screen_get_param;
 616         pscreen->get_paramf = fd_screen_get_paramf;
 617         pscreen->get_shader_param = fd_screen_get_shader_param;
 618
 619         fd_resource_screen_init(pscreen);
 620         fd_query_screen_init(pscreen);
 621
 622         pscreen->get_name = fd_screen_get_name;
 623         pscreen->get_vendor = fd_screen_get_vendor;
 624         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 625
 626         pscreen->get_timestamp = fd_screen_get_timestamp;
 627
 628         pscreen->fence_reference = fd_screen_fence_ref;
 629         pscreen->fence_finish = fd_screen_fence_finish;
 630
 631         util_format_s3tc_init();
 632
 633         return pscreen;
 634
 635 fail:
 636         fd_screen_destroy(pscreen);
 637         return NULL;
 638 }