src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  81                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  82                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  83                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  84                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  85                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  86                 DEBUG_NAMED_VALUE_END
  87 };
  88
  89 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  90
  91 int fd_mesa_debug = 0;
  92 bool fd_binning_enabled = true;
  93 static bool glsl120 = false;
  94
  95 static const char *
  96 fd_screen_get_name(struct pipe_screen *pscreen)
  97 {
  98         static char buffer[128];
  99         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 100                         fd_screen(pscreen)->device_id);
 101         return buffer;
 102 }
 103
 104 static const char *
 105 fd_screen_get_vendor(struct pipe_screen *pscreen)
 106 {
 107         return "freedreno";
 108 }
 109
 110 static const char *
 111 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 112 {
 113         return "Qualcomm";
 114 }
 115
 116
 117 static uint64_t
 118 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 119 {
 120         struct fd_screen *screen = fd_screen(pscreen);
 121
 122         if (screen->has_timestamp) {
 123                 uint64_t n;
 124                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 125                 debug_assert(screen->max_freq > 0);
 126                 return n * 1000000000 / screen->max_freq;
 127         } else {
 128                 int64_t cpu_time = os_time_get() * 1000;
 129                 return cpu_time + screen->cpu_gpu_time_delta;
 130         }
 131
 132 }
 133
 134 static void
 135 fd_screen_destroy(struct pipe_screen *pscreen)
 136 {
 137         struct fd_screen *screen = fd_screen(pscreen);
 138
 139         if (screen->pipe)
 140                 fd_pipe_del(screen->pipe);
 141
 142         if (screen->dev)
 143                 fd_device_del(screen->dev);
 144
 145         fd_bc_fini(&screen->batch_cache);
 146
 147         slab_destroy_parent(&screen->transfer_pool);
 148
 149         mtx_destroy(&screen->lock);
 150
 151         ralloc_free(screen->compiler);
 152
 153         free(screen);
 154 }
 155
 156 /*
 157 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 158 tables for things that differ if the delta is not too much..
 159  */
 160 static int
 161 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 162 {
 163         struct fd_screen *screen = fd_screen(pscreen);
 164
 165         /* this is probably not totally correct.. but it's a start: */
 166         switch (param) {
 167         /* Supported features (boolean caps). */
 168         case PIPE_CAP_NPOT_TEXTURES:
 169         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 170         case PIPE_CAP_ANISOTROPIC_FILTER:
 171         case PIPE_CAP_POINT_SPRITE:
 172         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 173         case PIPE_CAP_TEXTURE_SWIZZLE:
 174         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 175         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 176         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 177         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 178         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 179         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 180         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 182         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 183         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 184         case PIPE_CAP_STRING_MARKER:
 185         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 186         case PIPE_CAP_TEXTURE_BARRIER:
 187         case PIPE_CAP_INVALIDATE_BUFFER:
 188                 return 1;
 189
 190         case PIPE_CAP_VERTEXID_NOBASE:
 191                 return is_a3xx(screen) || is_a4xx(screen);
 192
 193         case PIPE_CAP_COMPUTE:
 194                 return has_compute(screen);
 195
 196         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 197         case PIPE_CAP_TGSI_TEXCOORD:
 198         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 199         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 200         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 201         case PIPE_CAP_QUERY_MEMORY_INFO:
 202         case PIPE_CAP_PCI_GROUP:
 203         case PIPE_CAP_PCI_BUS:
 204         case PIPE_CAP_PCI_DEVICE:
 205         case PIPE_CAP_PCI_FUNCTION:
 206                 return 0;
 207
 208         case PIPE_CAP_SM3:
 209         case PIPE_CAP_PRIMITIVE_RESTART:
 210         case PIPE_CAP_TGSI_INSTANCEID:
 211         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 212         case PIPE_CAP_INDEP_BLEND_ENABLE:
 213         case PIPE_CAP_INDEP_BLEND_FUNC:
 214         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 215         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216         case PIPE_CAP_CONDITIONAL_RENDER:
 217         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 218         case PIPE_CAP_FAKE_SW_MSAA:
 219         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 220         case PIPE_CAP_CLIP_HALFZ:
 221                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 222
 223         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 224                 return is_a3xx(screen) || is_a4xx(screen);
 225
 226         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 227                 return is_a5xx(screen);
 228
 229         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 230                 return 0;
 231         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 232                 if (is_a3xx(screen)) return 16;
 233                 if (is_a4xx(screen)) return 32;
 234                 if (is_a5xx(screen)) return 32;
 235                 return 0;
 236         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 237                 /* We could possibly emulate more by pretending 2d/rect textures and
 238                  * splitting high bits of index into 2nd dimension..
 239                  */
 240                 if (is_a3xx(screen)) return 8192;
 241                 if (is_a4xx(screen)) return 16384;
 242                 if (is_a5xx(screen)) return 16384;
 243                 return 0;
 244
 245         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 246         case PIPE_CAP_CUBE_MAP_ARRAY:
 247         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 248         case PIPE_CAP_TEXTURE_QUERY_LOD:
 249                 return is_a4xx(screen) || is_a5xx(screen);
 250
 251         case PIPE_CAP_START_INSTANCE:
 252                 /* Note that a5xx can do this, it just can't (at least with
 253                  * current firmware) do draw_indirect with base_instance.
 254                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 255                  * gl42), hide base_instance on a5xx.  :-/
 256                  */
 257                 return is_a4xx(screen);
 258
 259         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 260                 return 64;
 261
 262         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 263                 if (glsl120)
 264                         return 120;
 265                 return is_ir3(screen) ? 140 : 120;
 266
 267         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 268                 if (is_a5xx(screen))
 269                         return 4;
 270                 return 0;
 271
 272         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 273                 if (is_a4xx(screen) || is_a5xx(screen))
 274                         return 4;
 275                 return 0;
 276
 277         /* Unsupported features. */
 278         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 279         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 280         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 281         case PIPE_CAP_USER_VERTEX_BUFFERS:
 282         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 283         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 284         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 285         case PIPE_CAP_TEXTURE_GATHER_SM5:
 286         case PIPE_CAP_SAMPLE_SHADING:
 287         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 288         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 289         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 290         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 291         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 292         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 293         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 294         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 295         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 296         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 297         case PIPE_CAP_TGSI_TXQS:
 298         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 299         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 300         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 301         case PIPE_CAP_CLEAR_TEXTURE:
 302         case PIPE_CAP_DRAW_PARAMETERS:
 303         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 304         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 305         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 306         case PIPE_CAP_GENERATE_MIPMAP:
 307         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 308         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 309         case PIPE_CAP_CULL_DISTANCE:
 310         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 311         case PIPE_CAP_TGSI_VOTE:
 312         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 313         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 314         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 315         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 316         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 317         case PIPE_CAP_TGSI_FS_FBFETCH:
 318         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 319         case PIPE_CAP_DOUBLES:
 320         case PIPE_CAP_INT64:
 321         case PIPE_CAP_INT64_DIVMOD:
 322         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 323         case PIPE_CAP_TGSI_CLOCK:
 324         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 325         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 326         case PIPE_CAP_TGSI_BALLOT:
 327         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 328         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 329         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 330         case PIPE_CAP_POST_DEPTH_COVERAGE:
 331         case PIPE_CAP_BINDLESS_TEXTURE:
 332         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 333         case PIPE_CAP_QUERY_SO_OVERFLOW:
 334         case PIPE_CAP_MEMOBJ:
 335         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 336         case PIPE_CAP_TILE_RASTER_ORDER:
 337         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 338         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 339         case PIPE_CAP_FENCE_SIGNAL:
 340         case PIPE_CAP_CONSTBUF0_FLAGS:
 341                 return 0;
 342
 343         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 344                 return screen->priority_mask;
 345
 346         case PIPE_CAP_DRAW_INDIRECT:
 347                 if (is_a4xx(screen) || is_a5xx(screen))
 348                         return 1;
 349                 return 0;
 350
 351         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 352                 if (is_a4xx(screen) || is_a5xx(screen))
 353                         return 1;
 354                 return 0;
 355
 356         case PIPE_CAP_LOAD_CONSTBUF:
 357                 /* name is confusing, but this turns on std430 packing */
 358                 if (is_ir3(screen))
 359                         return 1;
 360                 return 0;
 361
 362         case PIPE_CAP_MAX_VIEWPORTS:
 363                 return 1;
 364
 365         case PIPE_CAP_SHAREABLE_SHADERS:
 366         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 367         /* manage the variants for these ourself, to avoid breaking precompile: */
 368         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 369         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 370                 if (is_ir3(screen))
 371                         return 1;
 372                 return 0;
 373
 374         /* Stream output. */
 375         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 376                 if (is_ir3(screen))
 377                         return PIPE_MAX_SO_BUFFERS;
 378                 return 0;
 379         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 380         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 381                 if (is_ir3(screen))
 382                         return 1;
 383                 return 0;
 384         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 385         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 386                 if (is_ir3(screen))
 387                         return 16 * 4;   /* should only be shader out limit? */
 388                 return 0;
 389
 390         /* Geometry shader output, unsupported. */
 391         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 392         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 393         case PIPE_CAP_MAX_VERTEX_STREAMS:
 394                 return 0;
 395
 396         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 397                 return 2048;
 398
 399         /* Texturing. */
 400         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 401         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 402                 return MAX_MIP_LEVELS;
 403         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 404                 return 11;
 405
 406         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 407                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 408
 409         /* Render targets. */
 410         case PIPE_CAP_MAX_RENDER_TARGETS:
 411                 return screen->max_rts;
 412         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 413                 return is_a3xx(screen) ? 1 : 0;
 414
 415         /* Queries. */
 416         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 417                 return 0;
 418         case PIPE_CAP_OCCLUSION_QUERY:
 419                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 420         case PIPE_CAP_QUERY_TIMESTAMP:
 421         case PIPE_CAP_QUERY_TIME_ELAPSED:
 422                 /* only a4xx, requires new enough kernel so we know max_freq: */
 423                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 424
 425         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 426         case PIPE_CAP_MIN_TEXEL_OFFSET:
 427                 return -8;
 428
 429         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 430         case PIPE_CAP_MAX_TEXEL_OFFSET:
 431                 return 7;
 432
 433         case PIPE_CAP_ENDIANNESS:
 434                 return PIPE_ENDIAN_LITTLE;
 435
 436         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 437                 return 64;
 438
 439         case PIPE_CAP_VENDOR_ID:
 440                 return 0x5143;
 441         case PIPE_CAP_DEVICE_ID:
 442                 return 0xFFFFFFFF;
 443         case PIPE_CAP_ACCELERATED:
 444                 return 1;
 445         case PIPE_CAP_VIDEO_MEMORY:
 446                 DBG("FINISHME: The value returned is incorrect\n");
 447                 return 10;
 448         case PIPE_CAP_UMA:
 449                 return 1;
 450         case PIPE_CAP_NATIVE_FENCE_FD:
 451                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 452         }
 453         debug_printf("unknown param %d\n", param);
 454         return 0;
 455 }
 456
 457 static float
 458 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 459 {
 460         switch (param) {
 461         case PIPE_CAPF_MAX_LINE_WIDTH:
 462         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 463                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 464                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 465                  * uses too small of a render target size, and gets confused when
 466                  * the lines start going offscreen.
 467                  *
 468                  * See: https://code.google.com/p/android/issues/detail?id=206513
 469                  */
 470                 if (fd_mesa_debug & FD_DBG_DEQP)
 471                         return 48.0f;
 472                 return 127.0f;
 473         case PIPE_CAPF_MAX_POINT_WIDTH:
 474         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 475                 return 4092.0f;
 476         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 477                 return 16.0f;
 478         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 479                 return 15.0f;
 480         }
 481         debug_printf("unknown paramf %d\n", param);
 482         return 0;
 483 }
 484
 485 static int
 486 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 487                 enum pipe_shader_type shader,
 488                 enum pipe_shader_cap param)
 489 {
 490         struct fd_screen *screen = fd_screen(pscreen);
 491
 492         switch(shader)
 493         {
 494         case PIPE_SHADER_FRAGMENT:
 495         case PIPE_SHADER_VERTEX:
 496                 break;
 497         case PIPE_SHADER_COMPUTE:
 498                 if (has_compute(screen))
 499                         break;
 500                 return 0;
 501         case PIPE_SHADER_GEOMETRY:
 502                 /* maye we could emulate.. */
 503                 return 0;
 504         default:
 505                 DBG("unknown shader type %d", shader);
 506                 return 0;
 507         }
 508
 509         /* this is probably not totally correct.. but it's a start: */
 510         switch (param) {
 511         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 512         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 513         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 514         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 515                 return 16384;
 516         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 517                 return 8; /* XXX */
 518         case PIPE_SHADER_CAP_MAX_INPUTS:
 519         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 520                 return 16;
 521         case PIPE_SHADER_CAP_MAX_TEMPS:
 522                 return 64; /* Max native temporaries. */
 523         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 524                 /* NOTE: seems to be limit for a3xx is actually 512 but
 525                  * split between VS and FS.  Use lower limit of 256 to
 526                  * avoid getting into impossible situations:
 527                  */
 528                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 529         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 530                 return is_ir3(screen) ? 16 : 1;
 531         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 532                 return 1;
 533         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 534         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 535                 /* Technically this should be the same as for TEMP/CONST, since
 536                  * everything is just normal registers.  This is just temporary
 537                  * hack until load_input/store_output handle arrays in a similar
 538                  * way as load_var/store_var..
 539                  */
 540                 return 0;
 541         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 542         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 543                 /* a2xx compiler doesn't handle indirect: */
 544                 return is_ir3(screen) ? 1 : 0;
 545         case PIPE_SHADER_CAP_SUBROUTINES:
 546         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 547         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 548         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 549         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 550         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 551                 return 0;
 552         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 553                 return 1;
 554         case PIPE_SHADER_CAP_INTEGERS:
 555                 if (glsl120)
 556                         return 0;
 557                 return is_ir3(screen) ? 1 : 0;
 558         case PIPE_SHADER_CAP_INT64_ATOMICS:
 559                 return 0;
 560         case PIPE_SHADER_CAP_FP16:
 561                 return 0;
 562         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 563         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 564                 return 16;
 565         case PIPE_SHADER_CAP_PREFERRED_IR:
 566                 if (is_ir3(screen))
 567                         return PIPE_SHADER_IR_NIR;
 568                 return PIPE_SHADER_IR_TGSI;
 569         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 570                 if (is_ir3(screen)) {
 571                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 572                 } else {
 573                         return (1 << PIPE_SHADER_IR_TGSI);
 574                 }
 575                 return 0;
 576         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 577                 return 32;
 578         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 579         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 580         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 581         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 582                 return 0;
 583         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 584         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 585                 if (is_a5xx(screen)) {
 586                         /* a5xx (and a4xx for that matter) has one state-block
 587                          * for compute-shader SSBO's and another that is shared
 588                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 589                          * just advertise SSBOs for FS and CS.  We could possibly
 590                          * do what blob does, and partition the space for
 591                          * VS/HS/DS/GS/FS.  The blob advertises:
 592                          *
 593                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 594                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 595                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 596                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 597                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 598                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 599                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 600                          *
 601                          * I think that way we could avoid having to patch shaders
 602                          * for actual SSBO indexes by using a static partitioning.
 603                          *
 604                          * Note same state block is used for images and buffers,
 605                          * but images also need texture state for read access
 606                          * (isam/isam.3d)
 607                          */
 608                         switch(shader)
 609                         {
 610                         case PIPE_SHADER_FRAGMENT:
 611                         case PIPE_SHADER_COMPUTE:
 612                                 return 24;
 613                         default:
 614                                 return 0;
 615                         }
 616                 }
 617                 return 0;
 618         }
 619         debug_printf("unknown shader param %d\n", param);
 620         return 0;
 621 }
 622
 623 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 624  * into per-generation backend?
 625  */
 626 static int
 627 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 628                 enum pipe_compute_cap param, void *ret)
 629 {
 630         struct fd_screen *screen = fd_screen(pscreen);
 631         const char * const ir = "ir3";
 632
 633         if (!has_compute(screen))
 634                 return 0;
 635
 636 #define RET(x) do {                  \
 637    if (ret)                          \
 638       memcpy(ret, x, sizeof(x));     \
 639    return sizeof(x);                 \
 640 } while (0)
 641
 642         switch (param) {
 643         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 644 // don't expose 64b pointer support yet, until ir3 supports 64b
 645 // math, otherwise spir64 target is used and we get 64b pointer
 646 // calculations that we can't do yet
 647 //              if (is_a5xx(screen))
 648 //                      RET((uint32_t []){ 64 });
 649                 RET((uint32_t []){ 32 });
 650
 651         case PIPE_COMPUTE_CAP_IR_TARGET:
 652                 if (ret)
 653                         sprintf(ret, ir);
 654                 return strlen(ir) * sizeof(char);
 655
 656         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 657                 RET((uint64_t []) { 3 });
 658
 659         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 660                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 661
 662         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 663                 RET(((uint64_t []) { 1024, 1024, 64 }));
 664
 665         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 666                 RET((uint64_t []) { 1024 });
 667
 668         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 669         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 670                 RET((uint64_t []) { 32768 });
 671
 672         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 673         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 674                 break;
 675         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 676                 RET((uint64_t []) { 32768 });
 677
 678         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 679         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 680         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 681         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 682         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 683                 break;
 684         }
 685
 686         return 0;
 687 }
 688
 689 static const void *
 690 fd_get_compiler_options(struct pipe_screen *pscreen,
 691                 enum pipe_shader_ir ir, unsigned shader)
 692 {
 693         struct fd_screen *screen = fd_screen(pscreen);
 694
 695         if (is_ir3(screen))
 696                 return ir3_get_compiler_options(screen->compiler);
 697
 698         return NULL;
 699 }
 700
 701 boolean
 702 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 703                 struct fd_bo *bo,
 704                 unsigned stride,
 705                 struct winsys_handle *whandle)
 706 {
 707         whandle->stride = stride;
 708
 709         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 710                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 711         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 712                 whandle->handle = fd_bo_handle(bo);
 713                 return TRUE;
 714         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 715                 whandle->handle = fd_bo_dmabuf(bo);
 716                 return TRUE;
 717         } else {
 718                 return FALSE;
 719         }
 720 }
 721
 722 struct fd_bo *
 723 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 724                 struct winsys_handle *whandle)
 725 {
 726         struct fd_screen *screen = fd_screen(pscreen);
 727         struct fd_bo *bo;
 728
 729         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 730                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 731         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 732                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 733         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 734                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 735         } else {
 736                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 737                 return NULL;
 738         }
 739
 740         if (!bo) {
 741                 DBG("ref name 0x%08x failed", whandle->handle);
 742                 return NULL;
 743         }
 744
 745         return bo;
 746 }
 747
 748 struct pipe_screen *
 749 fd_screen_create(struct fd_device *dev)
 750 {
 751         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 752         struct pipe_screen *pscreen;
 753         uint64_t val;
 754
 755         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 756
 757         if (fd_mesa_debug & FD_DBG_NOBIN)
 758                 fd_binning_enabled = false;
 759
 760         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 761
 762         if (!screen)
 763                 return NULL;
 764
 765         pscreen = &screen->base;
 766
 767         screen->dev = dev;
 768         screen->refcnt = 1;
 769
 770         // maybe this should be in context?
 771         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 772         if (!screen->pipe) {
 773                 DBG("could not create 3d pipe");
 774                 goto fail;
 775         }
 776
 777         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 778                 DBG("could not get GMEM size");
 779                 goto fail;
 780         }
 781         screen->gmemsize_bytes = val;
 782
 783         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 784                 DBG("could not get device-id");
 785                 goto fail;
 786         }
 787         screen->device_id = val;
 788
 789         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 790                 DBG("could not get gpu freq");
 791                 /* this limits what performance related queries are
 792                  * supported but is not fatal
 793                  */
 794                 screen->max_freq = 0;
 795         } else {
 796                 screen->max_freq = val;
 797                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 798                         screen->has_timestamp = true;
 799         }
 800
 801         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 802                 DBG("could not get gpu-id");
 803                 goto fail;
 804         }
 805         screen->gpu_id = val;
 806
 807         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 808                 DBG("could not get chip-id");
 809                 /* older kernels may not have this property: */
 810                 unsigned core  = screen->gpu_id / 100;
 811                 unsigned major = (screen->gpu_id % 100) / 10;
 812                 unsigned minor = screen->gpu_id % 10;
 813                 unsigned patch = 0;  /* assume the worst */
 814                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 815                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 816         }
 817         screen->chip_id = val;
 818
 819         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 820                 DBG("could not get # of rings");
 821                 screen->priority_mask = 0;
 822         } else {
 823                 /* # of rings equates to number of unique priority values: */
 824                 screen->priority_mask = (1 << val) - 1;
 825         }
 826
 827         DBG("Pipe Info:");
 828         DBG(" GPU-id:          %d", screen->gpu_id);
 829         DBG(" Chip-id:         0x%08x", screen->chip_id);
 830         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 831
 832         /* explicitly checking for GPU revisions that are known to work.  This
 833          * may be overly conservative for a3xx, where spoofing the gpu_id with
 834          * the blob driver seems to generate identical cmdstream dumps.  But
 835          * on a2xx, there seem to be small differences between the GPU revs
 836          * so it is probably better to actually test first on real hardware
 837          * before enabling:
 838          *
 839          * If you have a different adreno version, feel free to add it to one
 840          * of the cases below and see what happens.  And if it works, please
 841          * send a patch ;-)
 842          */
 843         switch (screen->gpu_id) {
 844         case 220:
 845                 fd2_screen_init(pscreen);
 846                 break;
 847         case 305:
 848         case 307:
 849         case 320:
 850         case 330:
 851                 fd3_screen_init(pscreen);
 852                 break;
 853         case 420:
 854         case 430:
 855                 fd4_screen_init(pscreen);
 856                 break;
 857         case 530:
 858                 fd5_screen_init(pscreen);
 859                 break;
 860         default:
 861                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 862                 goto fail;
 863         }
 864
 865         if (screen->gpu_id >= 500) {
 866                 screen->gmem_alignw = 64;
 867                 screen->gmem_alignh = 32;
 868                 screen->num_vsc_pipes = 16;
 869         } else {
 870                 screen->gmem_alignw = 32;
 871                 screen->gmem_alignh = 32;
 872                 screen->num_vsc_pipes = 8;
 873         }
 874
 875         /* NOTE: don't enable reordering on a2xx, since completely untested.
 876          * Also, don't enable if we have too old of a kernel to support
 877          * growable cmdstream buffers, since memory requirement for cmdstream
 878          * buffers would be too much otherwise.
 879          */
 880         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 881                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 882
 883         fd_bc_init(&screen->batch_cache);
 884
 885         (void) mtx_init(&screen->lock, mtx_plain);
 886
 887         pscreen->destroy = fd_screen_destroy;
 888         pscreen->get_param = fd_screen_get_param;
 889         pscreen->get_paramf = fd_screen_get_paramf;
 890         pscreen->get_shader_param = fd_screen_get_shader_param;
 891         pscreen->get_compute_param = fd_get_compute_param;
 892         pscreen->get_compiler_options = fd_get_compiler_options;
 893
 894         fd_resource_screen_init(pscreen);
 895         fd_query_screen_init(pscreen);
 896
 897         pscreen->get_name = fd_screen_get_name;
 898         pscreen->get_vendor = fd_screen_get_vendor;
 899         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 900
 901         pscreen->get_timestamp = fd_screen_get_timestamp;
 902
 903         pscreen->fence_reference = fd_fence_ref;
 904         pscreen->fence_finish = fd_fence_finish;
 905         pscreen->fence_get_fd = fd_fence_get_fd;
 906
 907         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 908
 909         return pscreen;
 910
 911 fail:
 912         fd_screen_destroy(pscreen);
 913         return NULL;
 914 }