gallium: add PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
40
41 #include "os/os_time.h"
42
43 #include <stdio.h>
44 #include <errno.h>
45 #include <stdlib.h>
46
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_util.h"
51
52 #include "fd2_screen.h"
53 #include "fd3_screen.h"
54
55 /* XXX this should go away */
56 #include "state_tracker/drm_driver.h"
57
58 static const struct debug_named_value debug_options[] = {
59 {"msgs", FD_DBG_MSGS, "Print debug messages"},
60 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
61 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
62 {"dgmem", FD_DBG_DGMEM, "Mark all state dirty after GMEM tile pass"},
63 {"dscis", FD_DBG_DSCIS, "Disable scissor optimization"},
64 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
65 {"dbypass", FD_DBG_DBYPASS,"Disable GMEM bypass"},
66 DEBUG_NAMED_VALUE_END
67 };
68
69 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
70
71 int fd_mesa_debug = 0;
72
73 static const char *
74 fd_screen_get_name(struct pipe_screen *pscreen)
75 {
76 static char buffer[128];
77 util_snprintf(buffer, sizeof(buffer), "FD%03d",
78 fd_screen(pscreen)->device_id);
79 return buffer;
80 }
81
82 static const char *
83 fd_screen_get_vendor(struct pipe_screen *pscreen)
84 {
85 return "freedreno";
86 }
87
88 static uint64_t
89 fd_screen_get_timestamp(struct pipe_screen *pscreen)
90 {
91 int64_t cpu_time = os_time_get() * 1000;
92 return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
93 }
94
95 static void
96 fd_screen_fence_ref(struct pipe_screen *pscreen,
97 struct pipe_fence_handle **ptr,
98 struct pipe_fence_handle *pfence)
99 {
100 fd_fence_ref(fd_fence(pfence), (struct fd_fence **)ptr);
101 }
102
103 static boolean
104 fd_screen_fence_signalled(struct pipe_screen *screen,
105 struct pipe_fence_handle *pfence)
106 {
107 return fd_fence_signalled(fd_fence(pfence));
108 }
109
110 static boolean
111 fd_screen_fence_finish(struct pipe_screen *screen,
112 struct pipe_fence_handle *pfence,
113 uint64_t timeout)
114 {
115 return fd_fence_wait(fd_fence(pfence));
116 }
117
118 static void
119 fd_screen_destroy(struct pipe_screen *pscreen)
120 {
121 struct fd_screen *screen = fd_screen(pscreen);
122
123 if (screen->pipe)
124 fd_pipe_del(screen->pipe);
125
126 if (screen->dev)
127 fd_device_del(screen->dev);
128
129 free(screen);
130 }
131
132 /*
133 TODO either move caps to a2xx/a3xx specific code, or maybe have some
134 tables for things that differ if the delta is not too much..
135 */
136 static int
137 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
138 {
139 /* this is probably not totally correct.. but it's a start: */
140 switch (param) {
141 /* Supported features (boolean caps). */
142 case PIPE_CAP_NPOT_TEXTURES:
143 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
144 case PIPE_CAP_TWO_SIDED_STENCIL:
145 case PIPE_CAP_ANISOTROPIC_FILTER:
146 case PIPE_CAP_POINT_SPRITE:
147 case PIPE_CAP_TEXTURE_SHADOW_MAP:
148 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
149 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
150 case PIPE_CAP_TEXTURE_SWIZZLE:
151 case PIPE_CAP_SHADER_STENCIL_EXPORT:
152 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
153 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_SM3:
157 case PIPE_CAP_SEAMLESS_CUBE_MAP:
158 case PIPE_CAP_PRIMITIVE_RESTART:
159 case PIPE_CAP_CONDITIONAL_RENDER:
160 case PIPE_CAP_TEXTURE_BARRIER:
161 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_TGSI_INSTANCEID:
164 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
165 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
166 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
167 case PIPE_CAP_COMPUTE:
168 case PIPE_CAP_START_INSTANCE:
169 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
170 case PIPE_CAP_TEXTURE_MULTISAMPLE:
171 case PIPE_CAP_USER_CONSTANT_BUFFERS:
172 return 1;
173
174 case PIPE_CAP_TGSI_TEXCOORD:
175 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
176 return 0;
177
178 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
179 return 256;
180
181 case PIPE_CAP_GLSL_FEATURE_LEVEL:
182 return 120;
183
184 /* Unsupported features. */
185 case PIPE_CAP_INDEP_BLEND_ENABLE:
186 case PIPE_CAP_INDEP_BLEND_FUNC:
187 case PIPE_CAP_DEPTH_CLIP_DISABLE:
188 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
189 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
190 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
191 case PIPE_CAP_SCALED_RESOLVE:
192 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
193 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
194 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
195 case PIPE_CAP_USER_VERTEX_BUFFERS:
196 case PIPE_CAP_USER_INDEX_BUFFERS:
197 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
198 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
199 return 0;
200
201 /* Stream output. */
202 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
203 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
204 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
205 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
206 return 0;
207
208 /* Texturing. */
209 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
210 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
211 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
212 return MAX_MIP_LEVELS;
213 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
214 return 9192;
215 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
216 return 20;
217
218 /* Render targets. */
219 case PIPE_CAP_MAX_RENDER_TARGETS:
220 return 1;
221
222 /* Timer queries. */
223 case PIPE_CAP_QUERY_TIME_ELAPSED:
224 case PIPE_CAP_OCCLUSION_QUERY:
225 case PIPE_CAP_QUERY_TIMESTAMP:
226 return 0;
227
228 case PIPE_CAP_MIN_TEXEL_OFFSET:
229 return -8;
230
231 case PIPE_CAP_MAX_TEXEL_OFFSET:
232 return 7;
233
234 case PIPE_CAP_ENDIANNESS:
235 return PIPE_ENDIAN_LITTLE;
236
237 default:
238 DBG("unknown param %d", param);
239 return 0;
240 }
241 }
242
243 static float
244 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
245 {
246 switch (param) {
247 case PIPE_CAPF_MAX_LINE_WIDTH:
248 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
249 case PIPE_CAPF_MAX_POINT_WIDTH:
250 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
251 return 8192.0f;
252 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
253 return 16.0f;
254 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
255 return 16.0f;
256 case PIPE_CAPF_GUARD_BAND_LEFT:
257 case PIPE_CAPF_GUARD_BAND_TOP:
258 case PIPE_CAPF_GUARD_BAND_RIGHT:
259 case PIPE_CAPF_GUARD_BAND_BOTTOM:
260 return 0.0f;
261 default:
262 DBG("unknown paramf %d", param);
263 return 0;
264 }
265 }
266
267 static int
268 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
269 enum pipe_shader_cap param)
270 {
271 struct fd_screen *screen = fd_screen(pscreen);
272
273 switch(shader)
274 {
275 case PIPE_SHADER_FRAGMENT:
276 case PIPE_SHADER_VERTEX:
277 break;
278 case PIPE_SHADER_COMPUTE:
279 case PIPE_SHADER_GEOMETRY:
280 /* maye we could emulate.. */
281 return 0;
282 default:
283 DBG("unknown shader type %d", shader);
284 return 0;
285 }
286
287 /* this is probably not totally correct.. but it's a start: */
288 switch (param) {
289 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
290 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
291 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
292 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
293 return 16384;
294 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
295 return 8; /* XXX */
296 case PIPE_SHADER_CAP_MAX_INPUTS:
297 return 32;
298 case PIPE_SHADER_CAP_MAX_TEMPS:
299 return 64; /* Max native temporaries. */
300 case PIPE_SHADER_CAP_MAX_ADDRS:
301 return 1; /* Max native address registers */
302 case PIPE_SHADER_CAP_MAX_CONSTS:
303 return (screen->gpu_id >= 300) ? 1024 : 64;
304 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
305 return 1;
306 case PIPE_SHADER_CAP_MAX_PREDS:
307 return 0; /* nothing uses this */
308 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
309 return 1;
310 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
311 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
312 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
313 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
314 return 1;
315 case PIPE_SHADER_CAP_SUBROUTINES:
316 return 0;
317 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
318 case PIPE_SHADER_CAP_INTEGERS:
319 return 0;
320 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
321 return 16;
322 case PIPE_SHADER_CAP_PREFERRED_IR:
323 return PIPE_SHADER_IR_TGSI;
324 default:
325 DBG("unknown shader param %d", param);
326 return 0;
327 }
328 return 0;
329 }
330
331 boolean
332 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
333 struct fd_bo *bo,
334 unsigned stride,
335 struct winsys_handle *whandle)
336 {
337 whandle->stride = stride;
338
339 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
340 return fd_bo_get_name(bo, &whandle->handle) == 0;
341 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
342 whandle->handle = fd_bo_handle(bo);
343 return TRUE;
344 } else {
345 return FALSE;
346 }
347 }
348
349 struct fd_bo *
350 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
351 struct winsys_handle *whandle,
352 unsigned *out_stride)
353 {
354 struct fd_screen *screen = fd_screen(pscreen);
355 struct fd_bo *bo;
356
357 bo = fd_bo_from_name(screen->dev, whandle->handle);
358 if (!bo) {
359 DBG("ref name 0x%08x failed", whandle->handle);
360 return NULL;
361 }
362
363 *out_stride = whandle->stride;
364
365 return bo;
366 }
367
368 struct pipe_screen *
369 fd_screen_create(struct fd_device *dev)
370 {
371 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
372 struct pipe_screen *pscreen;
373 uint64_t val;
374
375 fd_mesa_debug = debug_get_option_fd_mesa_debug();
376
377 if (!screen)
378 return NULL;
379
380 pscreen = &screen->base;
381
382 screen->dev = dev;
383
384 // maybe this should be in context?
385 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
386 if (!screen->pipe) {
387 DBG("could not create 3d pipe");
388 goto fail;
389 }
390
391 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
392 DBG("could not get GMEM size");
393 goto fail;
394 }
395 screen->gmemsize_bytes = val;
396
397 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
398 DBG("could not get device-id");
399 goto fail;
400 }
401 screen->device_id = val;
402
403 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
404 DBG("could not get gpu-id");
405 goto fail;
406 }
407 screen->gpu_id = val;
408
409 /* explicitly checking for GPU revisions that are known to work. This
410 * may be overly conservative for a3xx, where spoofing the gpu_id with
411 * the blob driver seems to generate identical cmdstream dumps. But
412 * on a2xx, there seem to be small differences between the GPU revs
413 * so it is probably better to actually test first on real hardware
414 * before enabling:
415 *
416 * If you have a different adreno version, feel free to add it to one
417 * of the two cases below and see what happens. And if it works, please
418 * send a patch ;-)
419 */
420 switch (screen->gpu_id) {
421 case 220:
422 fd2_screen_init(pscreen);
423 break;
424 case 320:
425 fd3_screen_init(pscreen);
426 break;
427 default:
428 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
429 goto fail;
430 }
431
432 pscreen->destroy = fd_screen_destroy;
433 pscreen->get_param = fd_screen_get_param;
434 pscreen->get_paramf = fd_screen_get_paramf;
435 pscreen->get_shader_param = fd_screen_get_shader_param;
436
437 fd_resource_screen_init(pscreen);
438
439 pscreen->get_name = fd_screen_get_name;
440 pscreen->get_vendor = fd_screen_get_vendor;
441
442 pscreen->get_timestamp = fd_screen_get_timestamp;
443
444 pscreen->fence_reference = fd_screen_fence_ref;
445 pscreen->fence_signalled = fd_screen_fence_signalled;
446 pscreen->fence_finish = fd_screen_fence_finish;
447
448 util_format_s3tc_init();
449
450 return pscreen;
451
452 fail:
453 fd_screen_destroy(pscreen);
454 return NULL;
455 }