src/gallium/drivers/freedreno/freedreno_screen.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_format.h"
  35 #include "util/u_format_s3tc.h"
  36 #include "util/u_screen.h"
  37 #include "util/u_string.h"
  38 #include "util/u_debug.h"
  39
  40 #include "util/os_time.h"
  41
  42 #include "drm-uapi/drm_fourcc.h"
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58 #include "a6xx/fd6_screen.h"
  59
  60
  61 #include "ir3/ir3_nir.h"
  62 #include "a2xx/ir2.h"
  63
  64 /* XXX this should go away */
  65 #include "state_tracker/drm_driver.h"
  66
  67 static const struct debug_named_value debug_options[] = {
  68                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  69                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
  70                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  71                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  72                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  73                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  74                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  75                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  76                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  77                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  78                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  79                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  80                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  81                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  82                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  83                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  84                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  85                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  86                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  87                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  88                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a2xx/a3xx/a5xx)"},
  89                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  90                 {"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
  91                 DEBUG_NAMED_VALUE_END
  92 };
  93
  94 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  95
  96 int fd_mesa_debug = 0;
  97 bool fd_binning_enabled = true;
  98 static bool glsl120 = false;
  99
 100 static const char *
 101 fd_screen_get_name(struct pipe_screen *pscreen)
 102 {
 103         static char buffer[128];
 104         snprintf(buffer, sizeof(buffer), "FD%03d",
 105                         fd_screen(pscreen)->device_id);
 106         return buffer;
 107 }
 108
 109 static const char *
 110 fd_screen_get_vendor(struct pipe_screen *pscreen)
 111 {
 112         return "freedreno";
 113 }
 114
 115 static const char *
 116 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 117 {
 118         return "Qualcomm";
 119 }
 120
 121
 122 static uint64_t
 123 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 124 {
 125         struct fd_screen *screen = fd_screen(pscreen);
 126
 127         if (screen->has_timestamp) {
 128                 uint64_t n;
 129                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 130                 debug_assert(screen->max_freq > 0);
 131                 return n * 1000000000 / screen->max_freq;
 132         } else {
 133                 int64_t cpu_time = os_time_get() * 1000;
 134                 return cpu_time + screen->cpu_gpu_time_delta;
 135         }
 136
 137 }
 138
 139 static void
 140 fd_screen_destroy(struct pipe_screen *pscreen)
 141 {
 142         struct fd_screen *screen = fd_screen(pscreen);
 143
 144         if (screen->pipe)
 145                 fd_pipe_del(screen->pipe);
 146
 147         if (screen->dev)
 148                 fd_device_del(screen->dev);
 149
 150         if (screen->ro)
 151                 FREE(screen->ro);
 152
 153         fd_bc_fini(&screen->batch_cache);
 154
 155         slab_destroy_parent(&screen->transfer_pool);
 156
 157         mtx_destroy(&screen->lock);
 158
 159         ralloc_free(screen->compiler);
 160
 161         free(screen->perfcntr_queries);
 162         free(screen);
 163 }
 164
 165 /*
 166 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 167 tables for things that differ if the delta is not too much..
 168  */
 169 static int
 170 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 171 {
 172         struct fd_screen *screen = fd_screen(pscreen);
 173
 174         /* this is probably not totally correct.. but it's a start: */
 175         switch (param) {
 176         /* Supported features (boolean caps). */
 177         case PIPE_CAP_NPOT_TEXTURES:
 178         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 179         case PIPE_CAP_ANISOTROPIC_FILTER:
 180         case PIPE_CAP_POINT_SPRITE:
 181         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 182         case PIPE_CAP_TEXTURE_SWIZZLE:
 183         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 184         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 185         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 187         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 188         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 189         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 190         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 191         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 192         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 193         case PIPE_CAP_STRING_MARKER:
 194         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 195         case PIPE_CAP_TEXTURE_BARRIER:
 196         case PIPE_CAP_INVALIDATE_BUFFER:
 197                 return 1;
 198
 199         case PIPE_CAP_PACKED_UNIFORMS:
 200                 return !is_a2xx(screen);
 201
 202         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 203         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 204                 return screen->has_robustness;
 205
 206         case PIPE_CAP_VERTEXID_NOBASE:
 207                 return is_a3xx(screen) || is_a4xx(screen);
 208
 209         case PIPE_CAP_COMPUTE:
 210                 return has_compute(screen);
 211
 212         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 213         case PIPE_CAP_PCI_GROUP:
 214         case PIPE_CAP_PCI_BUS:
 215         case PIPE_CAP_PCI_DEVICE:
 216         case PIPE_CAP_PCI_FUNCTION:
 217         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 218                 return 0;
 219
 220         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 221         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 222         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 223         case PIPE_CAP_PRIMITIVE_RESTART:
 224         case PIPE_CAP_TGSI_INSTANCEID:
 225         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 226         case PIPE_CAP_INDEP_BLEND_ENABLE:
 227         case PIPE_CAP_INDEP_BLEND_FUNC:
 228         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 229         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 230         case PIPE_CAP_CONDITIONAL_RENDER:
 231         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 232         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 233         case PIPE_CAP_CLIP_HALFZ:
 234                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 235
 236         case PIPE_CAP_FAKE_SW_MSAA:
 237                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 238
 239         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 240                 return is_a5xx(screen) || is_a6xx(screen);
 241
 242         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 243                 return is_a6xx(screen);
 244
 245         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 246                 return is_a3xx(screen) || is_a4xx(screen);
 247
 248         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 249                 return is_a5xx(screen) || is_a6xx(screen);
 250
 251         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 252                 if (is_a3xx(screen)) return 16;
 253                 if (is_a4xx(screen)) return 32;
 254                 if (is_a5xx(screen)) return 32;
 255                 if (is_a6xx(screen)) return 64;
 256                 return 0;
 257         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 258                 /* We could possibly emulate more by pretending 2d/rect textures and
 259                  * splitting high bits of index into 2nd dimension..
 260                  */
 261                 if (is_a3xx(screen)) return 8192;
 262                 if (is_a4xx(screen)) return 16384;
 263                 if (is_a5xx(screen)) return 16384;
 264                 if (is_a6xx(screen)) return 1 << 27;
 265                 return 0;
 266
 267         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 268         case PIPE_CAP_CUBE_MAP_ARRAY:
 269         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 270         case PIPE_CAP_TEXTURE_QUERY_LOD:
 271                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 272
 273         case PIPE_CAP_START_INSTANCE:
 274                 /* Note that a5xx can do this, it just can't (at least with
 275                  * current firmware) do draw_indirect with base_instance.
 276                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 277                  * gl42), hide base_instance on a5xx.  :-/
 278                  */
 279                 return is_a4xx(screen);
 280
 281         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 282                 return 64;
 283
 284         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 285         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 286                 if (glsl120)
 287                         return 120;
 288                 return is_ir3(screen) ? 140 : 120;
 289
 290         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 291                 /* we can probably enable 320 for a5xx too, but need to test: */
 292                 if (is_a6xx(screen)) return 320;
 293                 if (is_a5xx(screen)) return 310;
 294                 if (is_ir3(screen))  return 300;
 295                 return 120;
 296
 297         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 298                 if (is_a6xx(screen)) return 64;
 299                 if (is_a5xx(screen)) return 4;
 300                 return 0;
 301
 302         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 303                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 304                         return 4;
 305                 return 0;
 306
 307         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 308         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 309                 return 0;
 310
 311         case PIPE_CAP_FBFETCH:
 312                 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
 313                                 is_a6xx(screen))
 314                         return 1;
 315                 return 0;
 316         case PIPE_CAP_SAMPLE_SHADING:
 317                 if (is_a6xx(screen)) return 1;
 318                 return 0;
 319
 320         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 321                 return 0;
 322
 323         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 324                 return screen->priority_mask;
 325
 326         case PIPE_CAP_DRAW_INDIRECT:
 327                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 328                         return 1;
 329                 return 0;
 330
 331         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 332                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 333                         return 1;
 334                 return 0;
 335
 336         case PIPE_CAP_LOAD_CONSTBUF:
 337                 /* name is confusing, but this turns on std430 packing */
 338                 if (is_ir3(screen))
 339                         return 1;
 340                 return 0;
 341
 342         case PIPE_CAP_MAX_VIEWPORTS:
 343                 return 1;
 344
 345         case PIPE_CAP_MAX_VARYINGS:
 346                 return 16;
 347
 348         case PIPE_CAP_SHAREABLE_SHADERS:
 349         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 350         /* manage the variants for these ourself, to avoid breaking precompile: */
 351         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 352         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 353                 if (is_ir3(screen))
 354                         return 1;
 355                 return 0;
 356
 357         /* Stream output. */
 358         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 359                 if (is_ir3(screen))
 360                         return PIPE_MAX_SO_BUFFERS;
 361                 return 0;
 362         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 363         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 364         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 365                 if (is_ir3(screen))
 366                         return 1;
 367                 return 0;
 368         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 369                 return 1;
 370         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 371         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 372                 if (is_ir3(screen))
 373                         return 16 * 4;   /* should only be shader out limit? */
 374                 return 0;
 375
 376         /* Texturing. */
 377         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 378                 return 1 << (MAX_MIP_LEVELS - 1);
 379         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 380                 return MAX_MIP_LEVELS;
 381         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 382                 return 11;
 383
 384         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 385                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 386
 387         /* Render targets. */
 388         case PIPE_CAP_MAX_RENDER_TARGETS:
 389                 return screen->max_rts;
 390         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 391                 return is_a3xx(screen) ? 1 : 0;
 392
 393         /* Queries. */
 394         case PIPE_CAP_OCCLUSION_QUERY:
 395                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 396         case PIPE_CAP_QUERY_TIMESTAMP:
 397         case PIPE_CAP_QUERY_TIME_ELAPSED:
 398                 /* only a4xx, requires new enough kernel so we know max_freq: */
 399                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 400
 401         case PIPE_CAP_VENDOR_ID:
 402                 return 0x5143;
 403         case PIPE_CAP_DEVICE_ID:
 404                 return 0xFFFFFFFF;
 405         case PIPE_CAP_ACCELERATED:
 406                 return 1;
 407         case PIPE_CAP_VIDEO_MEMORY:
 408                 DBG("FINISHME: The value returned is incorrect\n");
 409                 return 10;
 410         case PIPE_CAP_UMA:
 411                 return 1;
 412         case PIPE_CAP_NATIVE_FENCE_FD:
 413                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 414         default:
 415                 return u_pipe_screen_get_param_defaults(pscreen, param);
 416         }
 417 }
 418
 419 static float
 420 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 421 {
 422         switch (param) {
 423         case PIPE_CAPF_MAX_LINE_WIDTH:
 424         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 425                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 426                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 427                  * uses too small of a render target size, and gets confused when
 428                  * the lines start going offscreen.
 429                  *
 430                  * See: https://code.google.com/p/android/issues/detail?id=206513
 431                  */
 432                 if (fd_mesa_debug & FD_DBG_DEQP)
 433                         return 48.0f;
 434                 return 127.0f;
 435         case PIPE_CAPF_MAX_POINT_WIDTH:
 436         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 437                 return 4092.0f;
 438         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 439                 return 16.0f;
 440         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 441                 return 15.0f;
 442         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 443         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 444         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 445                 return 0.0f;
 446         }
 447         debug_printf("unknown paramf %d\n", param);
 448         return 0;
 449 }
 450
 451 static int
 452 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 453                 enum pipe_shader_type shader,
 454                 enum pipe_shader_cap param)
 455 {
 456         struct fd_screen *screen = fd_screen(pscreen);
 457
 458         switch(shader)
 459         {
 460         case PIPE_SHADER_FRAGMENT:
 461         case PIPE_SHADER_VERTEX:
 462                 break;
 463         case PIPE_SHADER_COMPUTE:
 464                 if (has_compute(screen))
 465                         break;
 466                 return 0;
 467         case PIPE_SHADER_GEOMETRY:
 468                 /* maye we could emulate.. */
 469                 return 0;
 470         default:
 471                 DBG("unknown shader type %d", shader);
 472                 return 0;
 473         }
 474
 475         /* this is probably not totally correct.. but it's a start: */
 476         switch (param) {
 477         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 478         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 480         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 481                 return 16384;
 482         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 483                 return 8; /* XXX */
 484         case PIPE_SHADER_CAP_MAX_INPUTS:
 485         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 486                 return 16;
 487         case PIPE_SHADER_CAP_MAX_TEMPS:
 488                 return 64; /* Max native temporaries. */
 489         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 490                 /* NOTE: seems to be limit for a3xx is actually 512 but
 491                  * split between VS and FS.  Use lower limit of 256 to
 492                  * avoid getting into impossible situations:
 493                  */
 494                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 495         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 496                 return is_ir3(screen) ? 16 : 1;
 497         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 498                 return 1;
 499         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 500         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 501                 /* Technically this should be the same as for TEMP/CONST, since
 502                  * everything is just normal registers.  This is just temporary
 503                  * hack until load_input/store_output handle arrays in a similar
 504                  * way as load_var/store_var..
 505                  */
 506                 return 0;
 507         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 508         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 509                 /* a2xx compiler doesn't handle indirect: */
 510                 return is_ir3(screen) ? 1 : 0;
 511         case PIPE_SHADER_CAP_SUBROUTINES:
 512         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 513         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 514         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 515         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 516         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 517         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 518         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 519         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 520         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 521                 return 0;
 522         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 523                 return 1;
 524         case PIPE_SHADER_CAP_INTEGERS:
 525                 if (glsl120)
 526                         return 0;
 527                 return is_ir3(screen) ? 1 : 0;
 528         case PIPE_SHADER_CAP_INT64_ATOMICS:
 529                 return 0;
 530         case PIPE_SHADER_CAP_FP16:
 531                 return 0;
 532         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 533         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 534                 return 16;
 535         case PIPE_SHADER_CAP_PREFERRED_IR:
 536                 return PIPE_SHADER_IR_NIR;
 537         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 538                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 539         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 540                 return 32;
 541         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 542         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 543                 if (is_a5xx(screen) || is_a6xx(screen)) {
 544                         /* a5xx (and a4xx for that matter) has one state-block
 545                          * for compute-shader SSBO's and another that is shared
 546                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 547                          * just advertise SSBOs for FS and CS.  We could possibly
 548                          * do what blob does, and partition the space for
 549                          * VS/HS/DS/GS/FS.  The blob advertises:
 550                          *
 551                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 552                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 553                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 554                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 555                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 556                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 557                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 558                          *
 559                          * I think that way we could avoid having to patch shaders
 560                          * for actual SSBO indexes by using a static partitioning.
 561                          *
 562                          * Note same state block is used for images and buffers,
 563                          * but images also need texture state for read access
 564                          * (isam/isam.3d)
 565                          */
 566                         switch(shader)
 567                         {
 568                         case PIPE_SHADER_FRAGMENT:
 569                         case PIPE_SHADER_COMPUTE:
 570                                 return 24;
 571                         default:
 572                                 return 0;
 573                         }
 574                 }
 575                 return 0;
 576         }
 577         debug_printf("unknown shader param %d\n", param);
 578         return 0;
 579 }
 580
 581 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 582  * into per-generation backend?
 583  */
 584 static int
 585 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 586                 enum pipe_compute_cap param, void *ret)
 587 {
 588         struct fd_screen *screen = fd_screen(pscreen);
 589         const char * const ir = "ir3";
 590
 591         if (!has_compute(screen))
 592                 return 0;
 593
 594 #define RET(x) do {                  \
 595    if (ret)                          \
 596       memcpy(ret, x, sizeof(x));     \
 597    return sizeof(x);                 \
 598 } while (0)
 599
 600         switch (param) {
 601         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 602 // don't expose 64b pointer support yet, until ir3 supports 64b
 603 // math, otherwise spir64 target is used and we get 64b pointer
 604 // calculations that we can't do yet
 605 //              if (is_a5xx(screen))
 606 //                      RET((uint32_t []){ 64 });
 607                 RET((uint32_t []){ 32 });
 608
 609         case PIPE_COMPUTE_CAP_IR_TARGET:
 610                 if (ret)
 611                         sprintf(ret, "%s", ir);
 612                 return strlen(ir) * sizeof(char);
 613
 614         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 615                 RET((uint64_t []) { 3 });
 616
 617         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 618                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 619
 620         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 621                 RET(((uint64_t []) { 1024, 1024, 64 }));
 622
 623         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 624                 RET((uint64_t []) { 1024 });
 625
 626         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 627                 RET((uint64_t []) { screen->ram_size });
 628
 629         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 630                 RET((uint64_t []) { 32768 });
 631
 632         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 633         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 634                 RET((uint64_t []) { 4096 });
 635
 636         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 637                 RET((uint64_t []) { screen->ram_size });
 638
 639         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 640                 RET((uint32_t []) { screen->max_freq / 1000000 });
 641
 642         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 643                 RET((uint32_t []) { 9999 });  // TODO
 644
 645         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 646                 RET((uint32_t []) { 1 });
 647
 648         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 649                 RET((uint32_t []) { 32 });  // TODO
 650
 651         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 652                 RET((uint64_t []) { 1024 }); // TODO
 653         }
 654
 655         return 0;
 656 }
 657
 658 static const void *
 659 fd_get_compiler_options(struct pipe_screen *pscreen,
 660                 enum pipe_shader_ir ir, unsigned shader)
 661 {
 662         struct fd_screen *screen = fd_screen(pscreen);
 663
 664         if (is_ir3(screen))
 665                 return ir3_get_compiler_options(screen->compiler);
 666
 667         return ir2_get_compiler_options();
 668 }
 669
 670 bool
 671 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 672                 struct fd_bo *bo,
 673                 struct renderonly_scanout *scanout,
 674                 unsigned stride,
 675                 struct winsys_handle *whandle)
 676 {
 677         whandle->stride = stride;
 678
 679         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 680                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 681         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 682                 if (renderonly_get_handle(scanout, whandle))
 683                         return true;
 684                 whandle->handle = fd_bo_handle(bo);
 685                 return true;
 686         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 687                 whandle->handle = fd_bo_dmabuf(bo);
 688                 return true;
 689         } else {
 690                 return false;
 691         }
 692 }
 693
 694 static void
 695 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 696                 enum pipe_format format,
 697                 int max, uint64_t *modifiers,
 698                 unsigned int *external_only,
 699                 int *count)
 700 {
 701         struct fd_screen *screen = fd_screen(pscreen);
 702         int i, num = 0;
 703
 704         max = MIN2(max, screen->num_supported_modifiers);
 705
 706         if (!max) {
 707                 max = screen->num_supported_modifiers;
 708                 external_only = NULL;
 709                 modifiers = NULL;
 710         }
 711
 712         for (i = 0; i < max; i++) {
 713                 if (modifiers)
 714                         modifiers[num] = screen->supported_modifiers[i];
 715
 716                 if (external_only)
 717                         external_only[num] = 0;
 718
 719                 num++;
 720         }
 721
 722         *count = num;
 723 }
 724
 725 struct fd_bo *
 726 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 727                 struct winsys_handle *whandle)
 728 {
 729         struct fd_screen *screen = fd_screen(pscreen);
 730         struct fd_bo *bo;
 731
 732         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 733                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 734         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 735                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 736         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 737                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 738         } else {
 739                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 740                 return NULL;
 741         }
 742
 743         if (!bo) {
 744                 DBG("ref name 0x%08x failed", whandle->handle);
 745                 return NULL;
 746         }
 747
 748         return bo;
 749 }
 750
 751 static void _fd_fence_ref(struct pipe_screen *pscreen,
 752                 struct pipe_fence_handle **ptr,
 753                 struct pipe_fence_handle *pfence)
 754 {
 755         fd_fence_ref(ptr, pfence);
 756 }
 757
 758 struct pipe_screen *
 759 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 760 {
 761         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 762         struct pipe_screen *pscreen;
 763         uint64_t val;
 764
 765         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 766
 767         if (fd_mesa_debug & FD_DBG_NOBIN)
 768                 fd_binning_enabled = false;
 769
 770         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 771
 772         if (!screen)
 773                 return NULL;
 774
 775         pscreen = &screen->base;
 776
 777         screen->dev = dev;
 778         screen->refcnt = 1;
 779
 780         if (ro) {
 781                 screen->ro = renderonly_dup(ro);
 782                 if (!screen->ro) {
 783                         DBG("could not create renderonly object");
 784                         goto fail;
 785                 }
 786         }
 787
 788         // maybe this should be in context?
 789         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 790         if (!screen->pipe) {
 791                 DBG("could not create 3d pipe");
 792                 goto fail;
 793         }
 794
 795         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 796                 DBG("could not get GMEM size");
 797                 goto fail;
 798         }
 799         screen->gmemsize_bytes = val;
 800
 801         if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
 802                 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
 803         }
 804
 805         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 806                 DBG("could not get device-id");
 807                 goto fail;
 808         }
 809         screen->device_id = val;
 810
 811         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 812                 DBG("could not get gpu freq");
 813                 /* this limits what performance related queries are
 814                  * supported but is not fatal
 815                  */
 816                 screen->max_freq = 0;
 817         } else {
 818                 screen->max_freq = val;
 819                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 820                         screen->has_timestamp = true;
 821         }
 822
 823         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 824                 DBG("could not get gpu-id");
 825                 goto fail;
 826         }
 827         screen->gpu_id = val;
 828
 829         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 830                 DBG("could not get chip-id");
 831                 /* older kernels may not have this property: */
 832                 unsigned core  = screen->gpu_id / 100;
 833                 unsigned major = (screen->gpu_id % 100) / 10;
 834                 unsigned minor = screen->gpu_id % 10;
 835                 unsigned patch = 0;  /* assume the worst */
 836                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 837                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 838         }
 839         screen->chip_id = val;
 840
 841         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 842                 DBG("could not get # of rings");
 843                 screen->priority_mask = 0;
 844         } else {
 845                 /* # of rings equates to number of unique priority values: */
 846                 screen->priority_mask = (1 << val) - 1;
 847         }
 848
 849         if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) &&
 850                         (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) {
 851                 screen->has_robustness = val;
 852         }
 853
 854         struct sysinfo si;
 855         sysinfo(&si);
 856         screen->ram_size = si.totalram;
 857
 858         DBG("Pipe Info:");
 859         DBG(" GPU-id:          %d", screen->gpu_id);
 860         DBG(" Chip-id:         0x%08x", screen->chip_id);
 861         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 862
 863         /* explicitly checking for GPU revisions that are known to work.  This
 864          * may be overly conservative for a3xx, where spoofing the gpu_id with
 865          * the blob driver seems to generate identical cmdstream dumps.  But
 866          * on a2xx, there seem to be small differences between the GPU revs
 867          * so it is probably better to actually test first on real hardware
 868          * before enabling:
 869          *
 870          * If you have a different adreno version, feel free to add it to one
 871          * of the cases below and see what happens.  And if it works, please
 872          * send a patch ;-)
 873          */
 874         switch (screen->gpu_id) {
 875         case 200:
 876         case 201:
 877         case 205:
 878         case 220:
 879                 fd2_screen_init(pscreen);
 880                 break;
 881         case 305:
 882         case 307:
 883         case 320:
 884         case 330:
 885                 fd3_screen_init(pscreen);
 886                 break;
 887         case 420:
 888         case 430:
 889                 fd4_screen_init(pscreen);
 890                 break;
 891         case 530:
 892         case 540:
 893                 fd5_screen_init(pscreen);
 894                 break;
 895         case 630:
 896                 fd6_screen_init(pscreen);
 897                 break;
 898         default:
 899                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 900                 goto fail;
 901         }
 902
 903         if (screen->gpu_id >= 600) {
 904                 screen->gmem_alignw = 32;
 905                 screen->gmem_alignh = 32;
 906                 screen->num_vsc_pipes = 32;
 907         } else if (screen->gpu_id >= 500) {
 908                 screen->gmem_alignw = 64;
 909                 screen->gmem_alignh = 32;
 910                 screen->num_vsc_pipes = 16;
 911         } else {
 912                 screen->gmem_alignw = 32;
 913                 screen->gmem_alignh = 32;
 914                 screen->num_vsc_pipes = 8;
 915         }
 916
 917         /* NOTE: don't enable if we have too old of a kernel to support
 918          * growable cmdstream buffers, since memory requirement for cmdstream
 919          * buffers would be too much otherwise.
 920          */
 921         if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
 922                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 923
 924         fd_bc_init(&screen->batch_cache);
 925
 926         (void) mtx_init(&screen->lock, mtx_plain);
 927
 928         pscreen->destroy = fd_screen_destroy;
 929         pscreen->get_param = fd_screen_get_param;
 930         pscreen->get_paramf = fd_screen_get_paramf;
 931         pscreen->get_shader_param = fd_screen_get_shader_param;
 932         pscreen->get_compute_param = fd_get_compute_param;
 933         pscreen->get_compiler_options = fd_get_compiler_options;
 934
 935         fd_resource_screen_init(pscreen);
 936         fd_query_screen_init(pscreen);
 937
 938         pscreen->get_name = fd_screen_get_name;
 939         pscreen->get_vendor = fd_screen_get_vendor;
 940         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 941
 942         pscreen->get_timestamp = fd_screen_get_timestamp;
 943
 944         pscreen->fence_reference = _fd_fence_ref;
 945         pscreen->fence_finish = fd_fence_finish;
 946         pscreen->fence_get_fd = fd_fence_get_fd;
 947
 948         pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
 949
 950         if (!screen->supported_modifiers) {
 951                 static const uint64_t supported_modifiers[] = {
 952                         DRM_FORMAT_MOD_LINEAR,
 953                 };
 954
 955                 screen->supported_modifiers = supported_modifiers;
 956                 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
 957         }
 958
 959         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 960
 961         return pscreen;
 962
 963 fail:
 964         fd_screen_destroy(pscreen);
 965         return NULL;
 966 }