src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "fd2_screen.h"
  54 #include "fd3_screen.h"
  55
  56 /* XXX this should go away */
  57 #include "state_tracker/drm_driver.h"
  58
  59 static const struct debug_named_value debug_options[] = {
  60                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  61                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  62                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  63                 {"dgmem",     FD_DBG_DGMEM,  "Mark all state dirty after GMEM tile pass"},
  64                 {"dscis",     FD_DBG_DSCIS,  "Disable scissor optimization"},
  65                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  66                 {"dbypass",   FD_DBG_DBYPASS,"Disable GMEM bypass"},
  67                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  68                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  69                 {"noopt",     FD_DBG_NOOPT , "Disable optimization passes in compiler"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizater debug messages"},
  71                 {"optdump",   FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
  72                 DEBUG_NAMED_VALUE_END
  73 };
  74
  75 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  76
  77 int fd_mesa_debug = 0;
  78 bool fd_binning_enabled = true;
  79
  80 static const char *
  81 fd_screen_get_name(struct pipe_screen *pscreen)
  82 {
  83         static char buffer[128];
  84         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  85                         fd_screen(pscreen)->device_id);
  86         return buffer;
  87 }
  88
  89 static const char *
  90 fd_screen_get_vendor(struct pipe_screen *pscreen)
  91 {
  92         return "freedreno";
  93 }
  94
  95 static uint64_t
  96 fd_screen_get_timestamp(struct pipe_screen *pscreen)
  97 {
  98         int64_t cpu_time = os_time_get() * 1000;
  99         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 100 }
 101
 102 static void
 103 fd_screen_fence_ref(struct pipe_screen *pscreen,
 104                 struct pipe_fence_handle **ptr,
 105                 struct pipe_fence_handle *pfence)
 106 {
 107         fd_fence_ref(fd_fence(pfence), (struct fd_fence **)ptr);
 108 }
 109
 110 static boolean
 111 fd_screen_fence_signalled(struct pipe_screen *screen,
 112                 struct pipe_fence_handle *pfence)
 113 {
 114         return fd_fence_signalled(fd_fence(pfence));
 115 }
 116
 117 static boolean
 118 fd_screen_fence_finish(struct pipe_screen *screen,
 119                 struct pipe_fence_handle *pfence,
 120                 uint64_t timeout)
 121 {
 122         return fd_fence_wait(fd_fence(pfence));
 123 }
 124
 125 static void
 126 fd_screen_destroy(struct pipe_screen *pscreen)
 127 {
 128         struct fd_screen *screen = fd_screen(pscreen);
 129
 130         if (screen->pipe)
 131                 fd_pipe_del(screen->pipe);
 132
 133         if (screen->dev)
 134                 fd_device_del(screen->dev);
 135
 136         free(screen);
 137 }
 138
 139 /*
 140 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 141 tables for things that differ if the delta is not too much..
 142  */
 143 static int
 144 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 145 {
 146         /* this is probably not totally correct.. but it's a start: */
 147         switch (param) {
 148         /* Supported features (boolean caps). */
 149         case PIPE_CAP_NPOT_TEXTURES:
 150         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151         case PIPE_CAP_TWO_SIDED_STENCIL:
 152         case PIPE_CAP_ANISOTROPIC_FILTER:
 153         case PIPE_CAP_POINT_SPRITE:
 154         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 155         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 156         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 157         case PIPE_CAP_TEXTURE_SWIZZLE:
 158         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 159         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 160         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 161         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 162         case PIPE_CAP_SM3:
 163         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 164         case PIPE_CAP_PRIMITIVE_RESTART:
 165         case PIPE_CAP_CONDITIONAL_RENDER:
 166         case PIPE_CAP_TEXTURE_BARRIER:
 167         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 168         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 169         case PIPE_CAP_TGSI_INSTANCEID:
 170         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 171         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 172         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 173         case PIPE_CAP_COMPUTE:
 174         case PIPE_CAP_START_INSTANCE:
 175         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 176         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 177         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 178                 return 1;
 179
 180         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 181         case PIPE_CAP_TGSI_TEXCOORD:
 182         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 183                 return 0;
 184
 185         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 186                 return 256;
 187
 188         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 189                 return 120;
 190
 191         /* Unsupported features. */
 192         case PIPE_CAP_INDEP_BLEND_ENABLE:
 193         case PIPE_CAP_INDEP_BLEND_FUNC:
 194         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 195         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 196         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 197         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 198         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 199         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 200         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 201         case PIPE_CAP_USER_VERTEX_BUFFERS:
 202         case PIPE_CAP_USER_INDEX_BUFFERS:
 203         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 204         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 205         case PIPE_CAP_TGSI_VS_LAYER:
 206                 return 0;
 207
 208         /* Stream output. */
 209         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 210         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 211         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 212         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 213                 return 0;
 214
 215         /* Texturing. */
 216         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 217         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 218         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 219                 return MAX_MIP_LEVELS;
 220         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 221                 return 9192;
 222
 223         /* Render targets. */
 224         case PIPE_CAP_MAX_RENDER_TARGETS:
 225                 return 1;
 226
 227         /* Timer queries. */
 228         case PIPE_CAP_QUERY_TIME_ELAPSED:
 229         case PIPE_CAP_OCCLUSION_QUERY:
 230         case PIPE_CAP_QUERY_TIMESTAMP:
 231                 return 0;
 232
 233         case PIPE_CAP_MIN_TEXEL_OFFSET:
 234                 return -8;
 235
 236         case PIPE_CAP_MAX_TEXEL_OFFSET:
 237                 return 7;
 238
 239         case PIPE_CAP_ENDIANNESS:
 240                 return PIPE_ENDIAN_LITTLE;
 241
 242         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 243                 return 64;
 244
 245         default:
 246                 DBG("unknown param %d", param);
 247                 return 0;
 248         }
 249 }
 250
 251 static float
 252 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 253 {
 254         switch (param) {
 255         case PIPE_CAPF_MAX_LINE_WIDTH:
 256         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 257         case PIPE_CAPF_MAX_POINT_WIDTH:
 258         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 259                 return 8192.0f;
 260         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 261                 return 16.0f;
 262         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 263                 return 16.0f;
 264         case PIPE_CAPF_GUARD_BAND_LEFT:
 265         case PIPE_CAPF_GUARD_BAND_TOP:
 266         case PIPE_CAPF_GUARD_BAND_RIGHT:
 267         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 268                 return 0.0f;
 269         default:
 270                 DBG("unknown paramf %d", param);
 271                 return 0;
 272         }
 273 }
 274
 275 static int
 276 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 277                 enum pipe_shader_cap param)
 278 {
 279         struct fd_screen *screen = fd_screen(pscreen);
 280
 281         switch(shader)
 282         {
 283         case PIPE_SHADER_FRAGMENT:
 284         case PIPE_SHADER_VERTEX:
 285                 break;
 286         case PIPE_SHADER_COMPUTE:
 287         case PIPE_SHADER_GEOMETRY:
 288                 /* maye we could emulate.. */
 289                 return 0;
 290         default:
 291                 DBG("unknown shader type %d", shader);
 292                 return 0;
 293         }
 294
 295         /* this is probably not totally correct.. but it's a start: */
 296         switch (param) {
 297         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 298         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 299         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 300         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 301                 return 16384;
 302         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 303                 return 8; /* XXX */
 304         case PIPE_SHADER_CAP_MAX_INPUTS:
 305                 return 32;
 306         case PIPE_SHADER_CAP_MAX_TEMPS:
 307                 return 64; /* Max native temporaries. */
 308         case PIPE_SHADER_CAP_MAX_ADDRS:
 309                 return 1; /* Max native address registers */
 310         case PIPE_SHADER_CAP_MAX_CONSTS:
 311                 return (screen->gpu_id >= 300) ? 1024 : 64;
 312         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 313                 return 1;
 314         case PIPE_SHADER_CAP_MAX_PREDS:
 315                 return 0; /* nothing uses this */
 316         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 317                 return 1;
 318         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 319         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 320         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 321         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 322                 return 1;
 323         case PIPE_SHADER_CAP_SUBROUTINES:
 324                 return 0;
 325         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 326                 return 1;
 327         case PIPE_SHADER_CAP_INTEGERS:
 328                 /* we should be able to support this on a3xx, but not
 329                  * implemented yet:
 330                  */
 331                 return 0;
 332         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 333         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 334                 return 16;
 335         case PIPE_SHADER_CAP_PREFERRED_IR:
 336                 return PIPE_SHADER_IR_TGSI;
 337         default:
 338                 DBG("unknown shader param %d", param);
 339                 return 0;
 340         }
 341         return 0;
 342 }
 343
 344 boolean
 345 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 346                 struct fd_bo *bo,
 347                 unsigned stride,
 348                 struct winsys_handle *whandle)
 349 {
 350         whandle->stride = stride;
 351
 352         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 353                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 354         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 355                 whandle->handle = fd_bo_handle(bo);
 356                 return TRUE;
 357         } else {
 358                 return FALSE;
 359         }
 360 }
 361
 362 struct fd_bo *
 363 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 364                 struct winsys_handle *whandle,
 365                 unsigned *out_stride)
 366 {
 367         struct fd_screen *screen = fd_screen(pscreen);
 368         struct fd_bo *bo;
 369
 370         if (whandle->type != DRM_API_HANDLE_TYPE_SHARED) {
 371                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 372                 return NULL;
 373         }
 374
 375         bo = fd_bo_from_name(screen->dev, whandle->handle);
 376         if (!bo) {
 377                 DBG("ref name 0x%08x failed", whandle->handle);
 378                 return NULL;
 379         }
 380
 381         *out_stride = whandle->stride;
 382
 383         return bo;
 384 }
 385
 386 struct pipe_screen *
 387 fd_screen_create(struct fd_device *dev)
 388 {
 389         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 390         struct pipe_screen *pscreen;
 391         uint64_t val;
 392
 393         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 394
 395         if (fd_mesa_debug & FD_DBG_NOBIN)
 396                 fd_binning_enabled = false;
 397
 398         if (!screen)
 399                 return NULL;
 400
 401         pscreen = &screen->base;
 402
 403         screen->dev = dev;
 404
 405         // maybe this should be in context?
 406         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 407         if (!screen->pipe) {
 408                 DBG("could not create 3d pipe");
 409                 goto fail;
 410         }
 411
 412         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 413                 DBG("could not get GMEM size");
 414                 goto fail;
 415         }
 416         screen->gmemsize_bytes = val;
 417
 418         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 419                 DBG("could not get device-id");
 420                 goto fail;
 421         }
 422         screen->device_id = val;
 423
 424         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 425                 DBG("could not get gpu-id");
 426                 goto fail;
 427         }
 428         screen->gpu_id = val;
 429
 430         /* explicitly checking for GPU revisions that are known to work.  This
 431          * may be overly conservative for a3xx, where spoofing the gpu_id with
 432          * the blob driver seems to generate identical cmdstream dumps.  But
 433          * on a2xx, there seem to be small differences between the GPU revs
 434          * so it is probably better to actually test first on real hardware
 435          * before enabling:
 436          *
 437          * If you have a different adreno version, feel free to add it to one
 438          * of the two cases below and see what happens.  And if it works, please
 439          * send a patch ;-)
 440          */
 441         switch (screen->gpu_id) {
 442         case 220:
 443                 fd2_screen_init(pscreen);
 444                 break;
 445         case 320:
 446         case 330:
 447                 fd3_screen_init(pscreen);
 448                 break;
 449         default:
 450                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 451                 goto fail;
 452         }
 453
 454         pscreen->destroy = fd_screen_destroy;
 455         pscreen->get_param = fd_screen_get_param;
 456         pscreen->get_paramf = fd_screen_get_paramf;
 457         pscreen->get_shader_param = fd_screen_get_shader_param;
 458
 459         fd_resource_screen_init(pscreen);
 460         fd_query_screen_init(pscreen);
 461
 462         pscreen->get_name = fd_screen_get_name;
 463         pscreen->get_vendor = fd_screen_get_vendor;
 464
 465         pscreen->get_timestamp = fd_screen_get_timestamp;
 466
 467         pscreen->fence_reference = fd_screen_fence_ref;
 468         pscreen->fence_signalled = fd_screen_fence_signalled;
 469         pscreen->fence_finish = fd_screen_fence_finish;
 470
 471         util_format_s3tc_init();
 472
 473         return pscreen;
 474
 475 fail:
 476         fd_screen_destroy(pscreen);
 477         return NULL;
 478 }