1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
41 #include "os/os_time.h"
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
56 /* XXX this should go away */
57 #include "state_tracker/drm_driver.h"
59 static const struct debug_named_value debug_options
[] = {
60 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
61 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
62 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
63 {"dgmem", FD_DBG_DGMEM
, "Mark all state dirty after GMEM tile pass"},
64 {"dscis", FD_DBG_DSCIS
, "Disable scissor optimization"},
65 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
66 {"dbypass", FD_DBG_DBYPASS
,"Disable GMEM bypass"},
67 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
68 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
69 {"noopt", FD_DBG_NOOPT
, "Disable optimization passes in compiler"},
70 {"optmsgs", FD_DBG_OPTMSGS
,"Enable optimizater debug messages"},
71 {"optdump", FD_DBG_OPTDUMP
,"Dump shader DAG to .dot files"},
72 {"glsl130", FD_DBG_GLSL130
,"Temporary flag to enable GLSL 130 on a3xx+"},
76 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
78 int fd_mesa_debug
= 0;
79 bool fd_binning_enabled
= true;
80 static bool glsl130
= false;
83 fd_screen_get_name(struct pipe_screen
*pscreen
)
85 static char buffer
[128];
86 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
87 fd_screen(pscreen
)->device_id
);
92 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
98 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
100 int64_t cpu_time
= os_time_get() * 1000;
101 return cpu_time
+ fd_screen(pscreen
)->cpu_gpu_time_delta
;
105 fd_screen_fence_ref(struct pipe_screen
*pscreen
,
106 struct pipe_fence_handle
**ptr
,
107 struct pipe_fence_handle
*pfence
)
109 fd_fence_ref(fd_fence(pfence
), (struct fd_fence
**)ptr
);
113 fd_screen_fence_signalled(struct pipe_screen
*screen
,
114 struct pipe_fence_handle
*pfence
)
116 return fd_fence_signalled(fd_fence(pfence
));
120 fd_screen_fence_finish(struct pipe_screen
*screen
,
121 struct pipe_fence_handle
*pfence
,
124 return fd_fence_wait(fd_fence(pfence
));
128 fd_screen_destroy(struct pipe_screen
*pscreen
)
130 struct fd_screen
*screen
= fd_screen(pscreen
);
133 fd_pipe_del(screen
->pipe
);
136 fd_device_del(screen
->dev
);
142 TODO either move caps to a2xx/a3xx specific code, or maybe have some
143 tables for things that differ if the delta is not too much..
146 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
148 struct fd_screen
*screen
= fd_screen(pscreen
);
150 /* this is probably not totally correct.. but it's a start: */
152 /* Supported features (boolean caps). */
153 case PIPE_CAP_NPOT_TEXTURES
:
154 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
155 case PIPE_CAP_TWO_SIDED_STENCIL
:
156 case PIPE_CAP_ANISOTROPIC_FILTER
:
157 case PIPE_CAP_POINT_SPRITE
:
158 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
159 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
160 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
161 case PIPE_CAP_TEXTURE_SWIZZLE
:
162 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
163 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
164 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
165 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
166 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
167 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
168 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
169 case PIPE_CAP_TGSI_INSTANCEID
:
170 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
171 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
172 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
173 case PIPE_CAP_COMPUTE
:
174 case PIPE_CAP_START_INSTANCE
:
175 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
176 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
177 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
180 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
181 case PIPE_CAP_TGSI_TEXCOORD
:
182 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
183 case PIPE_CAP_CONDITIONAL_RENDER
:
184 case PIPE_CAP_PRIMITIVE_RESTART
:
185 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
186 case PIPE_CAP_TEXTURE_BARRIER
:
190 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
193 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
194 return ((screen
->gpu_id
>= 300) && glsl130
) ? 130 : 120;
196 /* Unsupported features. */
197 case PIPE_CAP_INDEP_BLEND_ENABLE
:
198 case PIPE_CAP_INDEP_BLEND_FUNC
:
199 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
200 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
203 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
204 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
205 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
206 case PIPE_CAP_USER_VERTEX_BUFFERS
:
207 case PIPE_CAP_USER_INDEX_BUFFERS
:
208 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
209 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
210 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
211 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
212 case PIPE_CAP_TEXTURE_GATHER_SM5
:
213 case PIPE_CAP_FAKE_SW_MSAA
:
214 case PIPE_CAP_TEXTURE_QUERY_LOD
:
215 case PIPE_CAP_SAMPLE_SHADING
:
216 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
217 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
218 case PIPE_CAP_DRAW_INDIRECT
:
219 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
220 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
224 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
225 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
226 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
227 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
230 /* Geometry shader output, unsupported. */
231 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
232 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
233 case PIPE_CAP_MAX_VERTEX_STREAMS
:
237 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
238 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
239 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
240 return MAX_MIP_LEVELS
;
241 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
242 return 0; /* TODO: a3xx+ should support (required in gles3) */
244 /* Render targets. */
245 case PIPE_CAP_MAX_RENDER_TARGETS
:
249 case PIPE_CAP_QUERY_TIME_ELAPSED
:
250 case PIPE_CAP_QUERY_TIMESTAMP
:
252 case PIPE_CAP_OCCLUSION_QUERY
:
253 return (screen
->gpu_id
>= 300) ? 1 : 0;
255 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
256 case PIPE_CAP_MIN_TEXEL_OFFSET
:
259 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
260 case PIPE_CAP_MAX_TEXEL_OFFSET
:
263 case PIPE_CAP_ENDIANNESS
:
264 return PIPE_ENDIAN_LITTLE
;
266 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
269 case PIPE_CAP_VENDOR_ID
:
271 case PIPE_CAP_DEVICE_ID
:
273 case PIPE_CAP_ACCELERATED
:
275 case PIPE_CAP_VIDEO_MEMORY
:
276 DBG("FINISHME: The value returned is incorrect\n");
282 DBG("unknown param %d", param
);
288 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
291 case PIPE_CAPF_MAX_LINE_WIDTH
:
292 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
293 case PIPE_CAPF_MAX_POINT_WIDTH
:
294 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
296 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
298 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
300 case PIPE_CAPF_GUARD_BAND_LEFT
:
301 case PIPE_CAPF_GUARD_BAND_TOP
:
302 case PIPE_CAPF_GUARD_BAND_RIGHT
:
303 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
306 DBG("unknown paramf %d", param
);
312 fd_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
313 enum pipe_shader_cap param
)
315 struct fd_screen
*screen
= fd_screen(pscreen
);
319 case PIPE_SHADER_FRAGMENT
:
320 case PIPE_SHADER_VERTEX
:
322 case PIPE_SHADER_COMPUTE
:
323 case PIPE_SHADER_GEOMETRY
:
324 /* maye we could emulate.. */
327 DBG("unknown shader type %d", shader
);
331 /* this is probably not totally correct.. but it's a start: */
333 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
334 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
335 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
336 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
338 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
340 case PIPE_SHADER_CAP_MAX_INPUTS
:
342 case PIPE_SHADER_CAP_MAX_TEMPS
:
343 return 64; /* Max native temporaries. */
344 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
345 return ((screen
->gpu_id
>= 300) ? 1024 : 64) * sizeof(float[4]);
346 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
348 case PIPE_SHADER_CAP_MAX_PREDS
:
349 return 0; /* nothing uses this */
350 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
352 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
353 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
354 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
355 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
357 case PIPE_SHADER_CAP_SUBROUTINES
:
359 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
361 case PIPE_SHADER_CAP_INTEGERS
:
362 /* we should be able to support this on a3xx, but not
365 return ((screen
->gpu_id
>= 300) && glsl130
) ? 1 : 0;
366 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
367 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
369 case PIPE_SHADER_CAP_PREFERRED_IR
:
370 return PIPE_SHADER_IR_TGSI
;
372 DBG("unknown shader param %d", param
);
379 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
382 struct winsys_handle
*whandle
)
384 whandle
->stride
= stride
;
386 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
387 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
388 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
389 whandle
->handle
= fd_bo_handle(bo
);
397 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
398 struct winsys_handle
*whandle
,
399 unsigned *out_stride
)
401 struct fd_screen
*screen
= fd_screen(pscreen
);
404 if (whandle
->type
!= DRM_API_HANDLE_TYPE_SHARED
) {
405 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
409 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
411 DBG("ref name 0x%08x failed", whandle
->handle
);
415 *out_stride
= whandle
->stride
;
421 fd_screen_create(struct fd_device
*dev
)
423 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
424 struct pipe_screen
*pscreen
;
427 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
429 if (fd_mesa_debug
& FD_DBG_NOBIN
)
430 fd_binning_enabled
= false;
432 glsl130
= !!(fd_mesa_debug
& FD_DBG_GLSL130
);
437 pscreen
= &screen
->base
;
441 // maybe this should be in context?
442 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
444 DBG("could not create 3d pipe");
448 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
449 DBG("could not get GMEM size");
452 screen
->gmemsize_bytes
= val
;
454 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
455 DBG("could not get device-id");
458 screen
->device_id
= val
;
460 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
461 DBG("could not get gpu-id");
464 screen
->gpu_id
= val
;
466 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
467 DBG("could not get chip-id");
468 /* older kernels may not have this property: */
469 unsigned core
= screen
->gpu_id
/ 100;
470 unsigned major
= (screen
->gpu_id
% 100) / 10;
471 unsigned minor
= screen
->gpu_id
% 10;
472 unsigned patch
= 0; /* assume the worst */
473 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
474 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
476 screen
->chip_id
= val
;
479 DBG(" GPU-id: %d", screen
->gpu_id
);
480 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
481 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
483 /* explicitly checking for GPU revisions that are known to work. This
484 * may be overly conservative for a3xx, where spoofing the gpu_id with
485 * the blob driver seems to generate identical cmdstream dumps. But
486 * on a2xx, there seem to be small differences between the GPU revs
487 * so it is probably better to actually test first on real hardware
490 * If you have a different adreno version, feel free to add it to one
491 * of the two cases below and see what happens. And if it works, please
494 switch (screen
->gpu_id
) {
496 fd2_screen_init(pscreen
);
500 fd3_screen_init(pscreen
);
503 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
507 pscreen
->destroy
= fd_screen_destroy
;
508 pscreen
->get_param
= fd_screen_get_param
;
509 pscreen
->get_paramf
= fd_screen_get_paramf
;
510 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
512 fd_resource_screen_init(pscreen
);
513 fd_query_screen_init(pscreen
);
515 pscreen
->get_name
= fd_screen_get_name
;
516 pscreen
->get_vendor
= fd_screen_get_vendor
;
518 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
520 pscreen
->fence_reference
= fd_screen_fence_ref
;
521 pscreen
->fence_signalled
= fd_screen_fence_signalled
;
522 pscreen
->fence_finish
= fd_screen_fence_finish
;
524 util_format_s3tc_init();
529 fd_screen_destroy(pscreen
);