src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 #include "ir3/ir3_nir.h"
  58
  59 /* XXX this should go away */
  60 #include "state_tracker/drm_driver.h"
  61
  62 static const struct debug_named_value debug_options[] = {
  63                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  64                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  65                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  66                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  67                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  68                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  69                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  70                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  71                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  72                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  73                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  74                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  75                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  76                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  77                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  78                 DEBUG_NAMED_VALUE_END
  79 };
  80
  81 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  82
  83 int fd_mesa_debug = 0;
  84 bool fd_binning_enabled = true;
  85 static bool glsl120 = false;
  86
  87 static const char *
  88 fd_screen_get_name(struct pipe_screen *pscreen)
  89 {
  90         static char buffer[128];
  91         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  92                         fd_screen(pscreen)->device_id);
  93         return buffer;
  94 }
  95
  96 static const char *
  97 fd_screen_get_vendor(struct pipe_screen *pscreen)
  98 {
  99         return "freedreno";
 100 }
 101
 102 static const char *
 103 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 104 {
 105         return "Qualcomm";
 106 }
 107
 108
 109 static uint64_t
 110 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 111 {
 112         int64_t cpu_time = os_time_get() * 1000;
 113         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 114 }
 115
 116 static void
 117 fd_screen_destroy(struct pipe_screen *pscreen)
 118 {
 119         struct fd_screen *screen = fd_screen(pscreen);
 120
 121         if (screen->pipe)
 122                 fd_pipe_del(screen->pipe);
 123
 124         if (screen->dev)
 125                 fd_device_del(screen->dev);
 126
 127         free(screen);
 128 }
 129
 130 /*
 131 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 132 tables for things that differ if the delta is not too much..
 133  */
 134 static int
 135 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 136 {
 137         struct fd_screen *screen = fd_screen(pscreen);
 138
 139         /* this is probably not totally correct.. but it's a start: */
 140         switch (param) {
 141         /* Supported features (boolean caps). */
 142         case PIPE_CAP_NPOT_TEXTURES:
 143         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 144         case PIPE_CAP_TWO_SIDED_STENCIL:
 145         case PIPE_CAP_ANISOTROPIC_FILTER:
 146         case PIPE_CAP_POINT_SPRITE:
 147         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 148         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149         case PIPE_CAP_TEXTURE_SWIZZLE:
 150         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 152         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 153         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 154         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 155         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 156         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 157         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 158         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 159         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 160         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 161         case PIPE_CAP_VERTEXID_NOBASE:
 162         case PIPE_CAP_STRING_MARKER:
 163                 return 1;
 164
 165         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 166         case PIPE_CAP_TGSI_TEXCOORD:
 167         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 168         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 169         case PIPE_CAP_TEXTURE_BARRIER:
 170         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 171         case PIPE_CAP_COMPUTE:
 172         case PIPE_CAP_QUERY_MEMORY_INFO:
 173         case PIPE_CAP_PCI_GROUP:
 174         case PIPE_CAP_PCI_BUS:
 175         case PIPE_CAP_PCI_DEVICE:
 176         case PIPE_CAP_PCI_FUNCTION:
 177                 return 0;
 178
 179         case PIPE_CAP_SM3:
 180         case PIPE_CAP_PRIMITIVE_RESTART:
 181         case PIPE_CAP_TGSI_INSTANCEID:
 182         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 183         case PIPE_CAP_INDEP_BLEND_ENABLE:
 184         case PIPE_CAP_INDEP_BLEND_FUNC:
 185         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 186         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 187         case PIPE_CAP_CONDITIONAL_RENDER:
 188         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 189         case PIPE_CAP_FAKE_SW_MSAA:
 190         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 191         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 192         case PIPE_CAP_CLIP_HALFZ:
 193                 return is_a3xx(screen) || is_a4xx(screen);
 194
 195         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 196                 return 0;
 197         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 198                 if (is_a3xx(screen)) return 16;
 199                 if (is_a4xx(screen)) return 32;
 200                 return 0;
 201         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 202                 /* We could possibly emulate more by pretending 2d/rect textures and
 203                  * splitting high bits of index into 2nd dimension..
 204                  */
 205                 if (is_a3xx(screen)) return 8192;
 206                 if (is_a4xx(screen)) return 16384;
 207                 return 0;
 208
 209         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 210         case PIPE_CAP_CUBE_MAP_ARRAY:
 211         case PIPE_CAP_START_INSTANCE:
 212         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 213         case PIPE_CAP_TEXTURE_QUERY_LOD:
 214                 return is_a4xx(screen);
 215
 216         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 217                 return 256;
 218
 219         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 220                 if (glsl120)
 221                         return 120;
 222                 return is_ir3(screen) ? 140 : 120;
 223
 224         /* Unsupported features. */
 225         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 226         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 227         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 228         case PIPE_CAP_USER_VERTEX_BUFFERS:
 229         case PIPE_CAP_USER_INDEX_BUFFERS:
 230         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 231         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 232         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 233         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 234         case PIPE_CAP_TEXTURE_GATHER_SM5:
 235         case PIPE_CAP_SAMPLE_SHADING:
 236         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 237         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 238         case PIPE_CAP_DRAW_INDIRECT:
 239         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 240         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 241         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 242         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 243         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 244         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 245         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 246         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 247         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 248         case PIPE_CAP_TGSI_TXQS:
 249         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 250         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 251         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 252         case PIPE_CAP_CLEAR_TEXTURE:
 253         case PIPE_CAP_DRAW_PARAMETERS:
 254         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 255         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 256         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 257         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 258         case PIPE_CAP_INVALIDATE_BUFFER:
 259         case PIPE_CAP_GENERATE_MIPMAP:
 260         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 261         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 262         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 263         case PIPE_CAP_CULL_DISTANCE:
 264         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 265                 return 0;
 266
 267         case PIPE_CAP_MAX_VIEWPORTS:
 268                 return 1;
 269
 270         case PIPE_CAP_SHAREABLE_SHADERS:
 271         /* manage the variants for these ourself, to avoid breaking precompile: */
 272         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 273         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 274                 if (is_ir3(screen))
 275                         return 1;
 276                 return 0;
 277
 278         /* Stream output. */
 279         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 280                 if (is_ir3(screen))
 281                         return PIPE_MAX_SO_BUFFERS;
 282                 return 0;
 283         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 284                 if (is_ir3(screen))
 285                         return 1;
 286                 return 0;
 287         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 288         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 289                 if (is_ir3(screen))
 290                         return 16 * 4;   /* should only be shader out limit? */
 291                 return 0;
 292
 293         /* Geometry shader output, unsupported. */
 294         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 295         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 296         case PIPE_CAP_MAX_VERTEX_STREAMS:
 297                 return 0;
 298
 299         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 300                 return 2048;
 301
 302         /* Texturing. */
 303         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 304         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 305                 return MAX_MIP_LEVELS;
 306         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 307                 return 11;
 308
 309         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 310                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 311
 312         /* Render targets. */
 313         case PIPE_CAP_MAX_RENDER_TARGETS:
 314                 return screen->max_rts;
 315         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 316                 return is_a3xx(screen) ? 1 : 0;
 317
 318         /* Queries. */
 319         case PIPE_CAP_QUERY_TIMESTAMP:
 320         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 321                 return 0;
 322         case PIPE_CAP_OCCLUSION_QUERY:
 323                 return is_a3xx(screen) || is_a4xx(screen);
 324         case PIPE_CAP_QUERY_TIME_ELAPSED:
 325                 /* only a4xx, requires new enough kernel so we know max_freq: */
 326                 return (screen->max_freq > 0) && is_a4xx(screen);
 327
 328         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 329         case PIPE_CAP_MIN_TEXEL_OFFSET:
 330                 return -8;
 331
 332         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 333         case PIPE_CAP_MAX_TEXEL_OFFSET:
 334                 return 7;
 335
 336         case PIPE_CAP_ENDIANNESS:
 337                 return PIPE_ENDIAN_LITTLE;
 338
 339         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 340                 return 64;
 341
 342         case PIPE_CAP_VENDOR_ID:
 343                 return 0x5143;
 344         case PIPE_CAP_DEVICE_ID:
 345                 return 0xFFFFFFFF;
 346         case PIPE_CAP_ACCELERATED:
 347                 return 1;
 348         case PIPE_CAP_VIDEO_MEMORY:
 349                 DBG("FINISHME: The value returned is incorrect\n");
 350                 return 10;
 351         case PIPE_CAP_UMA:
 352                 return 1;
 353         }
 354         debug_printf("unknown param %d\n", param);
 355         return 0;
 356 }
 357
 358 static float
 359 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 360 {
 361         switch (param) {
 362         case PIPE_CAPF_MAX_LINE_WIDTH:
 363         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 364                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 365                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 366                  * uses too small of a render target size, and gets confused when
 367                  * the lines start going offscreen.
 368                  *
 369                  * See: https://code.google.com/p/android/issues/detail?id=206513
 370                  */
 371                 if (fd_mesa_debug & FD_DBG_DEQP)
 372                         return 48.0f;
 373                 return 127.0f;
 374         case PIPE_CAPF_MAX_POINT_WIDTH:
 375         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 376                 return 4092.0f;
 377         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 378                 return 16.0f;
 379         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 380                 return 15.0f;
 381         case PIPE_CAPF_GUARD_BAND_LEFT:
 382         case PIPE_CAPF_GUARD_BAND_TOP:
 383         case PIPE_CAPF_GUARD_BAND_RIGHT:
 384         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 385                 return 0.0f;
 386         }
 387         debug_printf("unknown paramf %d\n", param);
 388         return 0;
 389 }
 390
 391 static int
 392 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 393                 enum pipe_shader_cap param)
 394 {
 395         struct fd_screen *screen = fd_screen(pscreen);
 396
 397         switch(shader)
 398         {
 399         case PIPE_SHADER_FRAGMENT:
 400         case PIPE_SHADER_VERTEX:
 401                 break;
 402         case PIPE_SHADER_COMPUTE:
 403         case PIPE_SHADER_GEOMETRY:
 404                 /* maye we could emulate.. */
 405                 return 0;
 406         default:
 407                 DBG("unknown shader type %d", shader);
 408                 return 0;
 409         }
 410
 411         /* this is probably not totally correct.. but it's a start: */
 412         switch (param) {
 413         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 414         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 415         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 416         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 417                 return 16384;
 418         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 419                 return 8; /* XXX */
 420         case PIPE_SHADER_CAP_MAX_INPUTS:
 421         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 422                 return 16;
 423         case PIPE_SHADER_CAP_MAX_TEMPS:
 424                 return 64; /* Max native temporaries. */
 425         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 426                 /* NOTE: seems to be limit for a3xx is actually 512 but
 427                  * split between VS and FS.  Use lower limit of 256 to
 428                  * avoid getting into impossible situations:
 429                  */
 430                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 431         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 432                 return is_ir3(screen) ? 16 : 1;
 433         case PIPE_SHADER_CAP_MAX_PREDS:
 434                 return 0; /* nothing uses this */
 435         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 436                 return 1;
 437         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 438         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 439                 /* Technically this should be the same as for TEMP/CONST, since
 440                  * everything is just normal registers.  This is just temporary
 441                  * hack until load_input/store_output handle arrays in a similar
 442                  * way as load_var/store_var..
 443                  */
 444                 return 0;
 445         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 446         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 447                 /* a2xx compiler doesn't handle indirect: */
 448                 return is_ir3(screen) ? 1 : 0;
 449         case PIPE_SHADER_CAP_SUBROUTINES:
 450         case PIPE_SHADER_CAP_DOUBLES:
 451         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 452         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 453         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 454         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 455                 return 0;
 456         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 457                 return 1;
 458         case PIPE_SHADER_CAP_INTEGERS:
 459                 if (glsl120)
 460                         return 0;
 461                 return is_ir3(screen) ? 1 : 0;
 462         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 463         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 464                 return 16;
 465         case PIPE_SHADER_CAP_PREFERRED_IR:
 466                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 467                         return PIPE_SHADER_IR_NIR;
 468                 return PIPE_SHADER_IR_TGSI;
 469         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 470                 return 0;
 471         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 472                 return 32;
 473         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 474         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 475                 return 0;
 476         }
 477         debug_printf("unknown shader param %d\n", param);
 478         return 0;
 479 }
 480
 481 static const void *
 482 fd_get_compiler_options(struct pipe_screen *pscreen,
 483                 enum pipe_shader_ir ir, unsigned shader)
 484 {
 485         struct fd_screen *screen = fd_screen(pscreen);
 486
 487         if (is_ir3(screen))
 488                 return ir3_get_compiler_options();
 489
 490         return NULL;
 491 }
 492
 493 boolean
 494 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 495                 struct fd_bo *bo,
 496                 unsigned stride,
 497                 struct winsys_handle *whandle)
 498 {
 499         whandle->stride = stride;
 500
 501         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 502                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 503         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 504                 whandle->handle = fd_bo_handle(bo);
 505                 return TRUE;
 506         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 507                 whandle->handle = fd_bo_dmabuf(bo);
 508                 return TRUE;
 509         } else {
 510                 return FALSE;
 511         }
 512 }
 513
 514 struct fd_bo *
 515 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 516                 struct winsys_handle *whandle,
 517                 unsigned *out_stride)
 518 {
 519         struct fd_screen *screen = fd_screen(pscreen);
 520         struct fd_bo *bo;
 521
 522         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 523                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 524         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 525                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 526         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 527                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 528         } else {
 529                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 530                 return NULL;
 531         }
 532
 533         if (!bo) {
 534                 DBG("ref name 0x%08x failed", whandle->handle);
 535                 return NULL;
 536         }
 537
 538         *out_stride = whandle->stride;
 539
 540         return bo;
 541 }
 542
 543 struct pipe_screen *
 544 fd_screen_create(struct fd_device *dev)
 545 {
 546         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 547         struct pipe_screen *pscreen;
 548         uint64_t val;
 549
 550         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 551
 552         if (fd_mesa_debug & FD_DBG_NOBIN)
 553                 fd_binning_enabled = false;
 554
 555         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 556
 557         if (!screen)
 558                 return NULL;
 559
 560         pscreen = &screen->base;
 561
 562         screen->dev = dev;
 563         screen->refcnt = 1;
 564
 565         // maybe this should be in context?
 566         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 567         if (!screen->pipe) {
 568                 DBG("could not create 3d pipe");
 569                 goto fail;
 570         }
 571
 572         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 573                 DBG("could not get GMEM size");
 574                 goto fail;
 575         }
 576         screen->gmemsize_bytes = val;
 577
 578         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 579                 DBG("could not get device-id");
 580                 goto fail;
 581         }
 582         screen->device_id = val;
 583
 584         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 585                 DBG("could not get gpu freq");
 586                 /* this limits what performance related queries are
 587                  * supported but is not fatal
 588                  */
 589                 screen->max_freq = 0;
 590         } else {
 591                 screen->max_freq = val;
 592         }
 593
 594         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 595                 DBG("could not get gpu-id");
 596                 goto fail;
 597         }
 598         screen->gpu_id = val;
 599
 600         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 601                 DBG("could not get chip-id");
 602                 /* older kernels may not have this property: */
 603                 unsigned core  = screen->gpu_id / 100;
 604                 unsigned major = (screen->gpu_id % 100) / 10;
 605                 unsigned minor = screen->gpu_id % 10;
 606                 unsigned patch = 0;  /* assume the worst */
 607                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 608                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 609         }
 610         screen->chip_id = val;
 611
 612         DBG("Pipe Info:");
 613         DBG(" GPU-id:          %d", screen->gpu_id);
 614         DBG(" Chip-id:         0x%08x", screen->chip_id);
 615         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 616
 617         /* explicitly checking for GPU revisions that are known to work.  This
 618          * may be overly conservative for a3xx, where spoofing the gpu_id with
 619          * the blob driver seems to generate identical cmdstream dumps.  But
 620          * on a2xx, there seem to be small differences between the GPU revs
 621          * so it is probably better to actually test first on real hardware
 622          * before enabling:
 623          *
 624          * If you have a different adreno version, feel free to add it to one
 625          * of the cases below and see what happens.  And if it works, please
 626          * send a patch ;-)
 627          */
 628         switch (screen->gpu_id) {
 629         case 220:
 630                 fd2_screen_init(pscreen);
 631                 break;
 632         case 305:
 633         case 307:
 634         case 320:
 635         case 330:
 636                 fd3_screen_init(pscreen);
 637                 break;
 638         case 420:
 639         case 430:
 640                 fd4_screen_init(pscreen);
 641                 break;
 642         default:
 643                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 644                 goto fail;
 645         }
 646
 647         pscreen->destroy = fd_screen_destroy;
 648         pscreen->get_param = fd_screen_get_param;
 649         pscreen->get_paramf = fd_screen_get_paramf;
 650         pscreen->get_shader_param = fd_screen_get_shader_param;
 651         pscreen->get_compiler_options = fd_get_compiler_options;
 652
 653         fd_resource_screen_init(pscreen);
 654         fd_query_screen_init(pscreen);
 655
 656         pscreen->get_name = fd_screen_get_name;
 657         pscreen->get_vendor = fd_screen_get_vendor;
 658         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 659
 660         pscreen->get_timestamp = fd_screen_get_timestamp;
 661
 662         pscreen->fence_reference = fd_screen_fence_ref;
 663         pscreen->fence_finish = fd_screen_fence_finish;
 664
 665         util_format_s3tc_init();
 666
 667         return pscreen;
 668
 669 fail:
 670         fd_screen_destroy(pscreen);
 671         return NULL;
 672 }