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aea56a180af13710667e05088bce1f580bb7367b
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
40
41 #include "util/os_time.h"
42
43 #include <stdio.h>
44 #include <errno.h>
45 #include <stdlib.h>
46
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
52
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57
58 #include "ir3/ir3_nir.h"
59
60 /* XXX this should go away */
61 #include "state_tracker/drm_driver.h"
62
63 static const struct debug_named_value debug_options[] = {
64 {"msgs", FD_DBG_MSGS, "Print debug messages"},
65 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
66 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
67 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
68 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
69 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
70 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
71 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
72 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
73 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
74 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
75 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
76 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
77 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
78 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
79 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
80 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
81 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"},
82 DEBUG_NAMED_VALUE_END
83 };
84
85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
86
87 int fd_mesa_debug = 0;
88 bool fd_binning_enabled = true;
89 static bool glsl120 = false;
90
91 static const char *
92 fd_screen_get_name(struct pipe_screen *pscreen)
93 {
94 static char buffer[128];
95 util_snprintf(buffer, sizeof(buffer), "FD%03d",
96 fd_screen(pscreen)->device_id);
97 return buffer;
98 }
99
100 static const char *
101 fd_screen_get_vendor(struct pipe_screen *pscreen)
102 {
103 return "freedreno";
104 }
105
106 static const char *
107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
108 {
109 return "Qualcomm";
110 }
111
112
113 static uint64_t
114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
115 {
116 struct fd_screen *screen = fd_screen(pscreen);
117
118 if (screen->has_timestamp) {
119 uint64_t n;
120 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
121 debug_assert(screen->max_freq > 0);
122 return n * 1000000000 / screen->max_freq;
123 } else {
124 int64_t cpu_time = os_time_get() * 1000;
125 return cpu_time + screen->cpu_gpu_time_delta;
126 }
127
128 }
129
130 static void
131 fd_screen_destroy(struct pipe_screen *pscreen)
132 {
133 struct fd_screen *screen = fd_screen(pscreen);
134
135 if (screen->pipe)
136 fd_pipe_del(screen->pipe);
137
138 if (screen->dev)
139 fd_device_del(screen->dev);
140
141 fd_bc_fini(&screen->batch_cache);
142
143 slab_destroy_parent(&screen->transfer_pool);
144
145 mtx_destroy(&screen->lock);
146
147 ralloc_free(screen->compiler);
148
149 free(screen);
150 }
151
152 /*
153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
154 tables for things that differ if the delta is not too much..
155 */
156 static int
157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
158 {
159 struct fd_screen *screen = fd_screen(pscreen);
160
161 /* this is probably not totally correct.. but it's a start: */
162 switch (param) {
163 /* Supported features (boolean caps). */
164 case PIPE_CAP_NPOT_TEXTURES:
165 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
166 case PIPE_CAP_TWO_SIDED_STENCIL:
167 case PIPE_CAP_ANISOTROPIC_FILTER:
168 case PIPE_CAP_POINT_SPRITE:
169 case PIPE_CAP_TEXTURE_SHADOW_MAP:
170 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
171 case PIPE_CAP_TEXTURE_SWIZZLE:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
173 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP:
176 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
177 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
178 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
179 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
180 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
182 case PIPE_CAP_STRING_MARKER:
183 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
184 case PIPE_CAP_TEXTURE_BARRIER:
185 case PIPE_CAP_INVALIDATE_BUFFER:
186 return 1;
187
188 case PIPE_CAP_VERTEXID_NOBASE:
189 return is_a3xx(screen) || is_a4xx(screen);
190
191 case PIPE_CAP_USER_CONSTANT_BUFFERS:
192 return is_a4xx(screen) ? 0 : 1;
193
194 case PIPE_CAP_COMPUTE:
195 return has_compute(screen);
196
197 case PIPE_CAP_SHADER_STENCIL_EXPORT:
198 case PIPE_CAP_TGSI_TEXCOORD:
199 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
200 case PIPE_CAP_TEXTURE_MULTISAMPLE:
201 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
202 case PIPE_CAP_QUERY_MEMORY_INFO:
203 case PIPE_CAP_PCI_GROUP:
204 case PIPE_CAP_PCI_BUS:
205 case PIPE_CAP_PCI_DEVICE:
206 case PIPE_CAP_PCI_FUNCTION:
207 return 0;
208
209 case PIPE_CAP_SM3:
210 case PIPE_CAP_PRIMITIVE_RESTART:
211 case PIPE_CAP_TGSI_INSTANCEID:
212 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
213 case PIPE_CAP_INDEP_BLEND_ENABLE:
214 case PIPE_CAP_INDEP_BLEND_FUNC:
215 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
216 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
217 case PIPE_CAP_CONDITIONAL_RENDER:
218 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
219 case PIPE_CAP_FAKE_SW_MSAA:
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
221 case PIPE_CAP_CLIP_HALFZ:
222 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
223
224 case PIPE_CAP_DEPTH_CLIP_DISABLE:
225 return is_a3xx(screen) || is_a4xx(screen);
226
227 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
228 return is_a5xx(screen);
229
230 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
231 return 0;
232 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
233 if (is_a3xx(screen)) return 16;
234 if (is_a4xx(screen)) return 32;
235 if (is_a5xx(screen)) return 32;
236 return 0;
237 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
238 /* We could possibly emulate more by pretending 2d/rect textures and
239 * splitting high bits of index into 2nd dimension..
240 */
241 if (is_a3xx(screen)) return 8192;
242 if (is_a4xx(screen)) return 16384;
243 if (is_a5xx(screen)) return 16384;
244 return 0;
245
246 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
247 case PIPE_CAP_CUBE_MAP_ARRAY:
248 case PIPE_CAP_START_INSTANCE:
249 case PIPE_CAP_SAMPLER_VIEW_TARGET:
250 case PIPE_CAP_TEXTURE_QUERY_LOD:
251 return is_a4xx(screen) || is_a5xx(screen);
252
253 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
254 return 64;
255
256 case PIPE_CAP_GLSL_FEATURE_LEVEL:
257 if (glsl120)
258 return 120;
259 return is_ir3(screen) ? 140 : 120;
260
261 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
262 if (is_a5xx(screen))
263 return 4;
264 return 0;
265
266 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
267 if (is_a4xx(screen) || is_a5xx(screen))
268 return 4;
269 return 0;
270
271 /* Unsupported features. */
272 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
273 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
274 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
275 case PIPE_CAP_USER_VERTEX_BUFFERS:
276 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
277 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
278 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
279 case PIPE_CAP_TEXTURE_GATHER_SM5:
280 case PIPE_CAP_SAMPLE_SHADING:
281 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
282 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
283 case PIPE_CAP_MULTI_DRAW_INDIRECT:
284 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
285 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
286 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
287 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
288 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
289 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
290 case PIPE_CAP_DEPTH_BOUNDS_TEST:
291 case PIPE_CAP_TGSI_TXQS:
292 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
293 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
294 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
295 case PIPE_CAP_CLEAR_TEXTURE:
296 case PIPE_CAP_DRAW_PARAMETERS:
297 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
298 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
299 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
300 case PIPE_CAP_GENERATE_MIPMAP:
301 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
302 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
303 case PIPE_CAP_CULL_DISTANCE:
304 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
305 case PIPE_CAP_TGSI_VOTE:
306 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
307 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
308 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
309 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
310 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
311 case PIPE_CAP_TGSI_FS_FBFETCH:
312 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
313 case PIPE_CAP_DOUBLES:
314 case PIPE_CAP_INT64:
315 case PIPE_CAP_INT64_DIVMOD:
316 case PIPE_CAP_TGSI_TEX_TXF_LZ:
317 case PIPE_CAP_TGSI_CLOCK:
318 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
319 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
320 case PIPE_CAP_TGSI_BALLOT:
321 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
322 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
323 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
324 case PIPE_CAP_POST_DEPTH_COVERAGE:
325 case PIPE_CAP_BINDLESS_TEXTURE:
326 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
327 case PIPE_CAP_QUERY_SO_OVERFLOW:
328 case PIPE_CAP_MEMOBJ:
329 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
330 case PIPE_CAP_TILE_RASTER_ORDER:
331 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
332 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
333 return 0;
334
335 case PIPE_CAP_DRAW_INDIRECT:
336 if (is_a4xx(screen) || is_a5xx(screen))
337 return 1;
338 return 0;
339
340 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
341 if (is_a4xx(screen) || is_a5xx(screen))
342 return 1;
343 return 0;
344
345 case PIPE_CAP_LOAD_CONSTBUF:
346 /* name is confusing, but this turns on std430 packing */
347 if (is_ir3(screen))
348 return 1;
349 return 0;
350
351 case PIPE_CAP_MAX_VIEWPORTS:
352 return 1;
353
354 case PIPE_CAP_SHAREABLE_SHADERS:
355 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
356 /* manage the variants for these ourself, to avoid breaking precompile: */
357 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
358 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
359 if (is_ir3(screen))
360 return 1;
361 return 0;
362
363 /* Stream output. */
364 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
365 if (is_ir3(screen))
366 return PIPE_MAX_SO_BUFFERS;
367 return 0;
368 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
369 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
370 if (is_ir3(screen))
371 return 1;
372 return 0;
373 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
374 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
375 if (is_ir3(screen))
376 return 16 * 4; /* should only be shader out limit? */
377 return 0;
378
379 /* Geometry shader output, unsupported. */
380 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
381 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
382 case PIPE_CAP_MAX_VERTEX_STREAMS:
383 return 0;
384
385 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
386 return 2048;
387
388 /* Texturing. */
389 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
390 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
391 return MAX_MIP_LEVELS;
392 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
393 return 11;
394
395 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
396 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
397
398 /* Render targets. */
399 case PIPE_CAP_MAX_RENDER_TARGETS:
400 return screen->max_rts;
401 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
402 return is_a3xx(screen) ? 1 : 0;
403
404 /* Queries. */
405 case PIPE_CAP_QUERY_BUFFER_OBJECT:
406 return 0;
407 case PIPE_CAP_OCCLUSION_QUERY:
408 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
409 case PIPE_CAP_QUERY_TIMESTAMP:
410 case PIPE_CAP_QUERY_TIME_ELAPSED:
411 /* only a4xx, requires new enough kernel so we know max_freq: */
412 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
413
414 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
415 case PIPE_CAP_MIN_TEXEL_OFFSET:
416 return -8;
417
418 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
419 case PIPE_CAP_MAX_TEXEL_OFFSET:
420 return 7;
421
422 case PIPE_CAP_ENDIANNESS:
423 return PIPE_ENDIAN_LITTLE;
424
425 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
426 return 64;
427
428 case PIPE_CAP_VENDOR_ID:
429 return 0x5143;
430 case PIPE_CAP_DEVICE_ID:
431 return 0xFFFFFFFF;
432 case PIPE_CAP_ACCELERATED:
433 return 1;
434 case PIPE_CAP_VIDEO_MEMORY:
435 DBG("FINISHME: The value returned is incorrect\n");
436 return 10;
437 case PIPE_CAP_UMA:
438 return 1;
439 case PIPE_CAP_NATIVE_FENCE_FD:
440 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
441 }
442 debug_printf("unknown param %d\n", param);
443 return 0;
444 }
445
446 static float
447 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
448 {
449 switch (param) {
450 case PIPE_CAPF_MAX_LINE_WIDTH:
451 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
452 /* NOTE: actual value is 127.0f, but this is working around a deqp
453 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
454 * uses too small of a render target size, and gets confused when
455 * the lines start going offscreen.
456 *
457 * See: https://code.google.com/p/android/issues/detail?id=206513
458 */
459 if (fd_mesa_debug & FD_DBG_DEQP)
460 return 48.0f;
461 return 127.0f;
462 case PIPE_CAPF_MAX_POINT_WIDTH:
463 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
464 return 4092.0f;
465 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
466 return 16.0f;
467 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
468 return 15.0f;
469 case PIPE_CAPF_GUARD_BAND_LEFT:
470 case PIPE_CAPF_GUARD_BAND_TOP:
471 case PIPE_CAPF_GUARD_BAND_RIGHT:
472 case PIPE_CAPF_GUARD_BAND_BOTTOM:
473 return 0.0f;
474 }
475 debug_printf("unknown paramf %d\n", param);
476 return 0;
477 }
478
479 static int
480 fd_screen_get_shader_param(struct pipe_screen *pscreen,
481 enum pipe_shader_type shader,
482 enum pipe_shader_cap param)
483 {
484 struct fd_screen *screen = fd_screen(pscreen);
485
486 switch(shader)
487 {
488 case PIPE_SHADER_FRAGMENT:
489 case PIPE_SHADER_VERTEX:
490 break;
491 case PIPE_SHADER_COMPUTE:
492 if (has_compute(screen))
493 break;
494 return 0;
495 case PIPE_SHADER_GEOMETRY:
496 /* maye we could emulate.. */
497 return 0;
498 default:
499 DBG("unknown shader type %d", shader);
500 return 0;
501 }
502
503 /* this is probably not totally correct.. but it's a start: */
504 switch (param) {
505 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
506 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
507 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
508 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
509 return 16384;
510 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
511 return 8; /* XXX */
512 case PIPE_SHADER_CAP_MAX_INPUTS:
513 case PIPE_SHADER_CAP_MAX_OUTPUTS:
514 return 16;
515 case PIPE_SHADER_CAP_MAX_TEMPS:
516 return 64; /* Max native temporaries. */
517 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
518 /* NOTE: seems to be limit for a3xx is actually 512 but
519 * split between VS and FS. Use lower limit of 256 to
520 * avoid getting into impossible situations:
521 */
522 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
523 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
524 return is_ir3(screen) ? 16 : 1;
525 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
526 return 1;
527 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
528 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
529 /* Technically this should be the same as for TEMP/CONST, since
530 * everything is just normal registers. This is just temporary
531 * hack until load_input/store_output handle arrays in a similar
532 * way as load_var/store_var..
533 */
534 return 0;
535 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
536 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
537 /* a2xx compiler doesn't handle indirect: */
538 return is_ir3(screen) ? 1 : 0;
539 case PIPE_SHADER_CAP_SUBROUTINES:
540 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
541 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
542 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
543 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
544 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
545 return 0;
546 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
547 return 1;
548 case PIPE_SHADER_CAP_INTEGERS:
549 if (glsl120)
550 return 0;
551 return is_ir3(screen) ? 1 : 0;
552 case PIPE_SHADER_CAP_INT64_ATOMICS:
553 return 0;
554 case PIPE_SHADER_CAP_FP16:
555 return 0;
556 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
557 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
558 return 16;
559 case PIPE_SHADER_CAP_PREFERRED_IR:
560 if (is_ir3(screen))
561 return PIPE_SHADER_IR_NIR;
562 return PIPE_SHADER_IR_TGSI;
563 case PIPE_SHADER_CAP_SUPPORTED_IRS:
564 if (is_ir3(screen)) {
565 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
566 } else {
567 return (1 << PIPE_SHADER_IR_TGSI);
568 }
569 return 0;
570 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
571 return 32;
572 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
573 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
574 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
575 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
576 return 0;
577 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
578 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
579 if (is_a5xx(screen)) {
580 /* a5xx (and a4xx for that matter) has one state-block
581 * for compute-shader SSBO's and another that is shared
582 * by VS/HS/DS/GS/FS.. so to simplify things for now
583 * just advertise SSBOs for FS and CS. We could possibly
584 * do what blob does, and partition the space for
585 * VS/HS/DS/GS/FS. The blob advertises:
586 *
587 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
588 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
589 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
590 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
591 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
592 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
593 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
594 *
595 * I think that way we could avoid having to patch shaders
596 * for actual SSBO indexes by using a static partitioning.
597 *
598 * Note same state block is used for images and buffers,
599 * but images also need texture state for read access
600 * (isam/isam.3d)
601 */
602 switch(shader)
603 {
604 case PIPE_SHADER_FRAGMENT:
605 case PIPE_SHADER_COMPUTE:
606 return 24;
607 default:
608 return 0;
609 }
610 }
611 return 0;
612 }
613 debug_printf("unknown shader param %d\n", param);
614 return 0;
615 }
616
617 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
618 * into per-generation backend?
619 */
620 static int
621 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
622 enum pipe_compute_cap param, void *ret)
623 {
624 struct fd_screen *screen = fd_screen(pscreen);
625 const char * const ir = "ir3";
626
627 if (!has_compute(screen))
628 return 0;
629
630 switch (param) {
631 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
632 if (ret) {
633 uint32_t *address_bits = ret;
634 address_bits[0] = 32;
635
636 if (is_a5xx(screen))
637 address_bits[0] = 64;
638 }
639 return 1 * sizeof(uint32_t);
640
641 case PIPE_COMPUTE_CAP_IR_TARGET:
642 if (ret)
643 sprintf(ret, ir);
644 return strlen(ir) * sizeof(char);
645
646 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
647 if (ret) {
648 uint64_t *grid_dimension = ret;
649 grid_dimension[0] = 3;
650 }
651 return 1 * sizeof(uint64_t);
652
653 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
654 if (ret) {
655 uint64_t *grid_size = ret;
656 grid_size[0] = 65535;
657 grid_size[1] = 65535;
658 grid_size[2] = 65535;
659 }
660 return 3 * sizeof(uint64_t) ;
661
662 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
663 if (ret) {
664 uint64_t *block_size = ret;
665 block_size[0] = 1024;
666 block_size[1] = 1024;
667 block_size[2] = 64;
668 }
669 return 3 * sizeof(uint64_t) ;
670
671 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
672 if (ret) {
673 uint64_t *max_threads_per_block = ret;
674 *max_threads_per_block = 1024;
675 }
676 return sizeof(uint64_t);
677
678 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
679 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
680 if (ret) {
681 uint64_t *local_size = ret;
682 *local_size = 32768;
683 }
684 return sizeof(uint64_t);
685 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
686 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
687 break;
688 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
689 if (ret) {
690 uint64_t *max = ret;
691 *max = 32768;
692 }
693 return sizeof(uint64_t);
694 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
695 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
696 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
697 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
698 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
699 break;
700 }
701
702 return 0;
703 }
704
705 static const void *
706 fd_get_compiler_options(struct pipe_screen *pscreen,
707 enum pipe_shader_ir ir, unsigned shader)
708 {
709 struct fd_screen *screen = fd_screen(pscreen);
710
711 if (is_ir3(screen))
712 return ir3_get_compiler_options(screen->compiler);
713
714 return NULL;
715 }
716
717 boolean
718 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
719 struct fd_bo *bo,
720 unsigned stride,
721 struct winsys_handle *whandle)
722 {
723 whandle->stride = stride;
724
725 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
726 return fd_bo_get_name(bo, &whandle->handle) == 0;
727 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
728 whandle->handle = fd_bo_handle(bo);
729 return TRUE;
730 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
731 whandle->handle = fd_bo_dmabuf(bo);
732 return TRUE;
733 } else {
734 return FALSE;
735 }
736 }
737
738 struct fd_bo *
739 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
740 struct winsys_handle *whandle)
741 {
742 struct fd_screen *screen = fd_screen(pscreen);
743 struct fd_bo *bo;
744
745 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
746 bo = fd_bo_from_name(screen->dev, whandle->handle);
747 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
748 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
749 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
750 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
751 } else {
752 DBG("Attempt to import unsupported handle type %d", whandle->type);
753 return NULL;
754 }
755
756 if (!bo) {
757 DBG("ref name 0x%08x failed", whandle->handle);
758 return NULL;
759 }
760
761 return bo;
762 }
763
764 struct pipe_screen *
765 fd_screen_create(struct fd_device *dev)
766 {
767 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
768 struct pipe_screen *pscreen;
769 uint64_t val;
770
771 fd_mesa_debug = debug_get_option_fd_mesa_debug();
772
773 if (fd_mesa_debug & FD_DBG_NOBIN)
774 fd_binning_enabled = false;
775
776 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
777
778 if (!screen)
779 return NULL;
780
781 pscreen = &screen->base;
782
783 screen->dev = dev;
784 screen->refcnt = 1;
785
786 // maybe this should be in context?
787 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
788 if (!screen->pipe) {
789 DBG("could not create 3d pipe");
790 goto fail;
791 }
792
793 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
794 DBG("could not get GMEM size");
795 goto fail;
796 }
797 screen->gmemsize_bytes = val;
798
799 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
800 DBG("could not get device-id");
801 goto fail;
802 }
803 screen->device_id = val;
804
805 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
806 DBG("could not get gpu freq");
807 /* this limits what performance related queries are
808 * supported but is not fatal
809 */
810 screen->max_freq = 0;
811 } else {
812 screen->max_freq = val;
813 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
814 screen->has_timestamp = true;
815 }
816
817 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
818 DBG("could not get gpu-id");
819 goto fail;
820 }
821 screen->gpu_id = val;
822
823 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
824 DBG("could not get chip-id");
825 /* older kernels may not have this property: */
826 unsigned core = screen->gpu_id / 100;
827 unsigned major = (screen->gpu_id % 100) / 10;
828 unsigned minor = screen->gpu_id % 10;
829 unsigned patch = 0; /* assume the worst */
830 val = (patch & 0xff) | ((minor & 0xff) << 8) |
831 ((major & 0xff) << 16) | ((core & 0xff) << 24);
832 }
833 screen->chip_id = val;
834
835 DBG("Pipe Info:");
836 DBG(" GPU-id: %d", screen->gpu_id);
837 DBG(" Chip-id: 0x%08x", screen->chip_id);
838 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
839
840 /* explicitly checking for GPU revisions that are known to work. This
841 * may be overly conservative for a3xx, where spoofing the gpu_id with
842 * the blob driver seems to generate identical cmdstream dumps. But
843 * on a2xx, there seem to be small differences between the GPU revs
844 * so it is probably better to actually test first on real hardware
845 * before enabling:
846 *
847 * If you have a different adreno version, feel free to add it to one
848 * of the cases below and see what happens. And if it works, please
849 * send a patch ;-)
850 */
851 switch (screen->gpu_id) {
852 case 220:
853 fd2_screen_init(pscreen);
854 break;
855 case 305:
856 case 307:
857 case 320:
858 case 330:
859 fd3_screen_init(pscreen);
860 break;
861 case 420:
862 case 430:
863 fd4_screen_init(pscreen);
864 break;
865 case 530:
866 fd5_screen_init(pscreen);
867 break;
868 default:
869 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
870 goto fail;
871 }
872
873 if (screen->gpu_id >= 500) {
874 screen->gmem_alignw = 64;
875 screen->gmem_alignh = 32;
876 screen->num_vsc_pipes = 16;
877 } else {
878 screen->gmem_alignw = 32;
879 screen->gmem_alignh = 32;
880 screen->num_vsc_pipes = 8;
881 }
882
883 /* NOTE: don't enable reordering on a2xx, since completely untested.
884 * Also, don't enable if we have too old of a kernel to support
885 * growable cmdstream buffers, since memory requirement for cmdstream
886 * buffers would be too much otherwise.
887 */
888 if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
889 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
890
891 fd_bc_init(&screen->batch_cache);
892
893 (void) mtx_init(&screen->lock, mtx_plain);
894
895 pscreen->destroy = fd_screen_destroy;
896 pscreen->get_param = fd_screen_get_param;
897 pscreen->get_paramf = fd_screen_get_paramf;
898 pscreen->get_shader_param = fd_screen_get_shader_param;
899 pscreen->get_compute_param = fd_get_compute_param;
900 pscreen->get_compiler_options = fd_get_compiler_options;
901
902 fd_resource_screen_init(pscreen);
903 fd_query_screen_init(pscreen);
904
905 pscreen->get_name = fd_screen_get_name;
906 pscreen->get_vendor = fd_screen_get_vendor;
907 pscreen->get_device_vendor = fd_screen_get_device_vendor;
908
909 pscreen->get_timestamp = fd_screen_get_timestamp;
910
911 pscreen->fence_reference = fd_fence_ref;
912 pscreen->fence_finish = fd_fence_finish;
913 pscreen->fence_get_fd = fd_fence_get_fd;
914
915 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
916
917 return pscreen;
918
919 fail:
920 fd_screen_destroy(pscreen);
921 return NULL;
922 }