1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
41 #include "os/os_time.h"
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
57 /* XXX this should go away */
58 #include "state_tracker/drm_driver.h"
60 static const struct debug_named_value debug_options
[] = {
61 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
62 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
63 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
64 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
65 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
66 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
67 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
68 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
69 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
70 {"optmsgs", FD_DBG_OPTMSGS
,"Enable optimizer debug messages"},
71 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 120 (rather than 130) on a3xx+"},
75 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
77 int fd_mesa_debug
= 0;
78 bool fd_binning_enabled
= true;
79 static bool glsl120
= false;
82 fd_screen_get_name(struct pipe_screen
*pscreen
)
84 static char buffer
[128];
85 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
86 fd_screen(pscreen
)->device_id
);
91 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
97 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
104 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
106 int64_t cpu_time
= os_time_get() * 1000;
107 return cpu_time
+ fd_screen(pscreen
)->cpu_gpu_time_delta
;
111 fd_screen_destroy(struct pipe_screen
*pscreen
)
113 struct fd_screen
*screen
= fd_screen(pscreen
);
116 fd_pipe_del(screen
->pipe
);
119 fd_device_del(screen
->dev
);
125 TODO either move caps to a2xx/a3xx specific code, or maybe have some
126 tables for things that differ if the delta is not too much..
129 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
131 struct fd_screen
*screen
= fd_screen(pscreen
);
133 /* this is probably not totally correct.. but it's a start: */
135 /* Supported features (boolean caps). */
136 case PIPE_CAP_NPOT_TEXTURES
:
137 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
138 case PIPE_CAP_TWO_SIDED_STENCIL
:
139 case PIPE_CAP_ANISOTROPIC_FILTER
:
140 case PIPE_CAP_POINT_SPRITE
:
141 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
142 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
143 case PIPE_CAP_TEXTURE_SWIZZLE
:
144 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
145 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
146 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
147 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
148 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
149 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
150 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
151 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
152 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
153 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
154 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
155 case PIPE_CAP_VERTEXID_NOBASE
:
158 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
159 case PIPE_CAP_TGSI_TEXCOORD
:
160 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
161 case PIPE_CAP_CONDITIONAL_RENDER
:
162 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
163 case PIPE_CAP_TEXTURE_BARRIER
:
164 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
165 case PIPE_CAP_CUBE_MAP_ARRAY
:
166 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
167 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
168 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
169 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
170 case PIPE_CAP_START_INSTANCE
:
171 case PIPE_CAP_COMPUTE
:
175 case PIPE_CAP_PRIMITIVE_RESTART
:
176 case PIPE_CAP_TGSI_INSTANCEID
:
177 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
178 return is_a3xx(screen
) || is_a4xx(screen
);
180 case PIPE_CAP_INDEP_BLEND_ENABLE
:
181 case PIPE_CAP_INDEP_BLEND_FUNC
:
182 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
183 return is_a3xx(screen
);
185 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
188 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
191 return (is_a3xx(screen
) || is_a4xx(screen
)) ? 130 : 120;
193 /* Unsupported features. */
194 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
195 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
196 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
197 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
198 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
199 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
200 case PIPE_CAP_USER_VERTEX_BUFFERS
:
201 case PIPE_CAP_USER_INDEX_BUFFERS
:
202 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
203 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
204 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
206 case PIPE_CAP_TEXTURE_GATHER_SM5
:
207 case PIPE_CAP_FAKE_SW_MSAA
:
208 case PIPE_CAP_TEXTURE_QUERY_LOD
:
209 case PIPE_CAP_SAMPLE_SHADING
:
210 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
211 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
212 case PIPE_CAP_DRAW_INDIRECT
:
213 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
214 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
215 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
216 case PIPE_CAP_CLIP_HALFZ
:
217 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
218 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
219 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
220 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
223 case PIPE_CAP_MAX_VIEWPORTS
:
227 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
228 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
229 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
230 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
233 /* Geometry shader output, unsupported. */
234 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
235 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
236 case PIPE_CAP_MAX_VERTEX_STREAMS
:
239 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
243 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
244 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
245 return MAX_MIP_LEVELS
;
246 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
249 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
250 return (is_a3xx(screen
) || is_a4xx(screen
)) ? 256 : 0;
252 /* Render targets. */
253 case PIPE_CAP_MAX_RENDER_TARGETS
:
254 return screen
->max_rts
;
257 case PIPE_CAP_QUERY_TIME_ELAPSED
:
258 case PIPE_CAP_QUERY_TIMESTAMP
:
260 case PIPE_CAP_OCCLUSION_QUERY
:
261 /* TODO still missing on a4xx, but we lie to get gl2..
262 * it's not a feature, it's a bug!
264 return is_a3xx(screen
) || is_a4xx(screen
);
266 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
267 case PIPE_CAP_MIN_TEXEL_OFFSET
:
270 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
271 case PIPE_CAP_MAX_TEXEL_OFFSET
:
274 case PIPE_CAP_ENDIANNESS
:
275 return PIPE_ENDIAN_LITTLE
;
277 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
280 case PIPE_CAP_VENDOR_ID
:
282 case PIPE_CAP_DEVICE_ID
:
284 case PIPE_CAP_ACCELERATED
:
286 case PIPE_CAP_VIDEO_MEMORY
:
287 DBG("FINISHME: The value returned is incorrect\n");
292 debug_printf("unknown param %d\n", param
);
297 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
300 case PIPE_CAPF_MAX_LINE_WIDTH
:
301 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
302 case PIPE_CAPF_MAX_POINT_WIDTH
:
303 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
305 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
307 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
309 case PIPE_CAPF_GUARD_BAND_LEFT
:
310 case PIPE_CAPF_GUARD_BAND_TOP
:
311 case PIPE_CAPF_GUARD_BAND_RIGHT
:
312 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
315 debug_printf("unknown paramf %d\n", param
);
320 fd_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
321 enum pipe_shader_cap param
)
323 struct fd_screen
*screen
= fd_screen(pscreen
);
327 case PIPE_SHADER_FRAGMENT
:
328 case PIPE_SHADER_VERTEX
:
330 case PIPE_SHADER_COMPUTE
:
331 case PIPE_SHADER_GEOMETRY
:
332 /* maye we could emulate.. */
335 DBG("unknown shader type %d", shader
);
339 /* this is probably not totally correct.. but it's a start: */
341 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
342 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
343 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
344 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
346 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
348 case PIPE_SHADER_CAP_MAX_INPUTS
:
349 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
351 case PIPE_SHADER_CAP_MAX_TEMPS
:
352 return 64; /* Max native temporaries. */
353 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
354 /* NOTE: seems to be limit for a3xx is actually 512 but
355 * split between VS and FS. Use lower limit of 256 to
356 * avoid getting into impossible situations:
358 return ((is_a3xx(screen
) || is_a4xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
359 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
360 return (is_a3xx(screen
) || is_a4xx(screen
)) ? 16 : 1;
361 case PIPE_SHADER_CAP_MAX_PREDS
:
362 return 0; /* nothing uses this */
363 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
365 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
366 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
367 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
368 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
370 case PIPE_SHADER_CAP_SUBROUTINES
:
371 case PIPE_SHADER_CAP_DOUBLES
:
372 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
373 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
374 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
375 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
377 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
379 case PIPE_SHADER_CAP_INTEGERS
:
382 return (is_a3xx(screen
) || is_a4xx(screen
)) ? 1 : 0;
383 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
384 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
386 case PIPE_SHADER_CAP_PREFERRED_IR
:
387 return PIPE_SHADER_IR_TGSI
;
389 debug_printf("unknown shader param %d\n", param
);
394 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
397 struct winsys_handle
*whandle
)
399 whandle
->stride
= stride
;
401 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
402 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
403 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
404 whandle
->handle
= fd_bo_handle(bo
);
406 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
407 whandle
->handle
= fd_bo_dmabuf(bo
);
415 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
416 struct winsys_handle
*whandle
,
417 unsigned *out_stride
)
419 struct fd_screen
*screen
= fd_screen(pscreen
);
422 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
423 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
424 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
425 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
426 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
427 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
429 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
434 DBG("ref name 0x%08x failed", whandle
->handle
);
438 *out_stride
= whandle
->stride
;
444 fd_screen_create(struct fd_device
*dev
)
446 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
447 struct pipe_screen
*pscreen
;
450 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
452 if (fd_mesa_debug
& FD_DBG_NOBIN
)
453 fd_binning_enabled
= false;
455 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
460 pscreen
= &screen
->base
;
464 // maybe this should be in context?
465 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
467 DBG("could not create 3d pipe");
471 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
472 DBG("could not get GMEM size");
475 screen
->gmemsize_bytes
= val
;
477 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
478 DBG("could not get device-id");
481 screen
->device_id
= val
;
483 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
484 DBG("could not get gpu-id");
487 screen
->gpu_id
= val
;
489 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
490 DBG("could not get chip-id");
491 /* older kernels may not have this property: */
492 unsigned core
= screen
->gpu_id
/ 100;
493 unsigned major
= (screen
->gpu_id
% 100) / 10;
494 unsigned minor
= screen
->gpu_id
% 10;
495 unsigned patch
= 0; /* assume the worst */
496 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
497 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
499 screen
->chip_id
= val
;
502 DBG(" GPU-id: %d", screen
->gpu_id
);
503 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
504 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
506 /* explicitly checking for GPU revisions that are known to work. This
507 * may be overly conservative for a3xx, where spoofing the gpu_id with
508 * the blob driver seems to generate identical cmdstream dumps. But
509 * on a2xx, there seem to be small differences between the GPU revs
510 * so it is probably better to actually test first on real hardware
513 * If you have a different adreno version, feel free to add it to one
514 * of the cases below and see what happens. And if it works, please
517 switch (screen
->gpu_id
) {
519 fd2_screen_init(pscreen
);
524 fd3_screen_init(pscreen
);
527 fd4_screen_init(pscreen
);
530 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
534 pscreen
->destroy
= fd_screen_destroy
;
535 pscreen
->get_param
= fd_screen_get_param
;
536 pscreen
->get_paramf
= fd_screen_get_paramf
;
537 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
539 fd_resource_screen_init(pscreen
);
540 fd_query_screen_init(pscreen
);
542 pscreen
->get_name
= fd_screen_get_name
;
543 pscreen
->get_vendor
= fd_screen_get_vendor
;
544 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
546 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
548 pscreen
->fence_reference
= fd_screen_fence_ref
;
549 pscreen
->fence_signalled
= fd_screen_fence_signalled
;
550 pscreen
->fence_finish
= fd_screen_fence_finish
;
552 util_format_s3tc_init();
557 fd_screen_destroy(pscreen
);