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[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
39
40 #include "util/os_time.h"
41
42 #include "drm-uapi/drm_fourcc.h"
43 #include <errno.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <sys/sysinfo.h>
47
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
53
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
59
60
61 #include "ir3/ir3_nir.h"
62 #include "ir3/ir3_compiler.h"
63 #include "a2xx/ir2.h"
64
65 static const struct debug_named_value debug_options[] = {
66 {"msgs", FD_DBG_MSGS, "Print debug messages"},
67 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
68 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
69 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
70 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
71 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
72 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
73 {"log", FD_DBG_LOG, "Enable GPU timestamp based logging (a6xx+)"},
74 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
75 {"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
76 /* BIT(10) */
77 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
78 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
79 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
80 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
81 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
82 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
83 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
84 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
85 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
86 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
87 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
88 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
89 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
90 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
91 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
92 {"layout", FD_DBG_LAYOUT, "Dump resource layouts"},
93 {"nofp16", FD_DBG_NOFP16, "Disable mediump precision lowering"},
94 {"nohw", FD_DBG_NOHW, "Disable submitting commands to the HW"},
95 DEBUG_NAMED_VALUE_END
96 };
97
98 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
99
100 int fd_mesa_debug = 0;
101 bool fd_binning_enabled = true;
102
103 static const char *
104 fd_screen_get_name(struct pipe_screen *pscreen)
105 {
106 static char buffer[128];
107 snprintf(buffer, sizeof(buffer), "FD%03d",
108 fd_screen(pscreen)->device_id);
109 return buffer;
110 }
111
112 static const char *
113 fd_screen_get_vendor(struct pipe_screen *pscreen)
114 {
115 return "freedreno";
116 }
117
118 static const char *
119 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
120 {
121 return "Qualcomm";
122 }
123
124
125 static uint64_t
126 fd_screen_get_timestamp(struct pipe_screen *pscreen)
127 {
128 struct fd_screen *screen = fd_screen(pscreen);
129
130 if (screen->has_timestamp) {
131 uint64_t n;
132 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
133 debug_assert(screen->max_freq > 0);
134 return n * 1000000000 / screen->max_freq;
135 } else {
136 int64_t cpu_time = os_time_get() * 1000;
137 return cpu_time + screen->cpu_gpu_time_delta;
138 }
139
140 }
141
142 static void
143 fd_screen_destroy(struct pipe_screen *pscreen)
144 {
145 struct fd_screen *screen = fd_screen(pscreen);
146
147 if (screen->pipe)
148 fd_pipe_del(screen->pipe);
149
150 if (screen->dev)
151 fd_device_del(screen->dev);
152
153 if (screen->ro)
154 FREE(screen->ro);
155
156 fd_bc_fini(&screen->batch_cache);
157 fd_gmem_screen_fini(pscreen);
158
159 slab_destroy_parent(&screen->transfer_pool);
160
161 simple_mtx_destroy(&screen->lock);
162
163 if (screen->compiler)
164 ir3_compiler_destroy(screen->compiler);
165
166 ralloc_free(screen->live_batches);
167
168 free(screen->perfcntr_queries);
169 free(screen);
170 }
171
172 /*
173 TODO either move caps to a2xx/a3xx specific code, or maybe have some
174 tables for things that differ if the delta is not too much..
175 */
176 static int
177 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
178 {
179 struct fd_screen *screen = fd_screen(pscreen);
180
181 /* this is probably not totally correct.. but it's a start: */
182 switch (param) {
183 /* Supported features (boolean caps). */
184 case PIPE_CAP_NPOT_TEXTURES:
185 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
186 case PIPE_CAP_ANISOTROPIC_FILTER:
187 case PIPE_CAP_POINT_SPRITE:
188 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
189 case PIPE_CAP_TEXTURE_SWIZZLE:
190 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
191 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
192 case PIPE_CAP_SEAMLESS_CUBE_MAP:
193 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
194 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
195 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
196 case PIPE_CAP_STRING_MARKER:
197 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
198 case PIPE_CAP_TEXTURE_BARRIER:
199 case PIPE_CAP_INVALIDATE_BUFFER:
200 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
201 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
202 case PIPE_CAP_NIR_COMPACT_ARRAYS:
203 return 1;
204
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
208 return !is_a2xx(screen);
209
210 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
211 return is_a2xx(screen);
212 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
213 return !is_a2xx(screen);
214
215 case PIPE_CAP_PACKED_UNIFORMS:
216 return !is_a2xx(screen);
217
218 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
219 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
220 return screen->has_robustness;
221
222 case PIPE_CAP_VERTEXID_NOBASE:
223 return is_a3xx(screen) || is_a4xx(screen);
224
225 case PIPE_CAP_COMPUTE:
226 return has_compute(screen);
227
228 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
229 case PIPE_CAP_PCI_GROUP:
230 case PIPE_CAP_PCI_BUS:
231 case PIPE_CAP_PCI_DEVICE:
232 case PIPE_CAP_PCI_FUNCTION:
233 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
234 return 0;
235
236 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
237 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
238 case PIPE_CAP_VERTEX_SHADER_SATURATE:
239 case PIPE_CAP_PRIMITIVE_RESTART:
240 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
241 case PIPE_CAP_TGSI_INSTANCEID:
242 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
243 case PIPE_CAP_INDEP_BLEND_ENABLE:
244 case PIPE_CAP_INDEP_BLEND_FUNC:
245 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
246 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
247 case PIPE_CAP_CONDITIONAL_RENDER:
248 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
249 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
250 case PIPE_CAP_CLIP_HALFZ:
251 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
252
253 case PIPE_CAP_FAKE_SW_MSAA:
254 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
255
256 case PIPE_CAP_TEXTURE_MULTISAMPLE:
257 return is_a5xx(screen) || is_a6xx(screen);
258
259 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
260 return is_a6xx(screen);
261
262 case PIPE_CAP_DEPTH_CLIP_DISABLE:
263 return is_a3xx(screen) || is_a4xx(screen);
264
265 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
266 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
267
268 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
269 if (is_a3xx(screen)) return 16;
270 if (is_a4xx(screen)) return 32;
271 if (is_a5xx(screen)) return 32;
272 if (is_a6xx(screen)) return 64;
273 return 0;
274 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
275 /* We could possibly emulate more by pretending 2d/rect textures and
276 * splitting high bits of index into 2nd dimension..
277 */
278 if (is_a3xx(screen)) return 8192;
279 if (is_a4xx(screen)) return 16384;
280 if (is_a5xx(screen)) return 16384;
281 if (is_a6xx(screen)) return 1 << 27;
282 return 0;
283
284 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
285 case PIPE_CAP_CUBE_MAP_ARRAY:
286 case PIPE_CAP_SAMPLER_VIEW_TARGET:
287 case PIPE_CAP_TEXTURE_QUERY_LOD:
288 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
289
290 case PIPE_CAP_START_INSTANCE:
291 /* Note that a5xx can do this, it just can't (at least with
292 * current firmware) do draw_indirect with base_instance.
293 * Since draw_indirect is needed sooner (gles31 and gl40 vs
294 * gl42), hide base_instance on a5xx. :-/
295 */
296 return is_a4xx(screen);
297
298 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
299 return 64;
300
301 case PIPE_CAP_GLSL_FEATURE_LEVEL:
302 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
303 return is_ir3(screen) ? 140 : 120;
304
305 case PIPE_CAP_ESSL_FEATURE_LEVEL:
306 /* we can probably enable 320 for a5xx too, but need to test: */
307 if (is_a6xx(screen)) return 320;
308 if (is_a5xx(screen)) return 310;
309 if (is_ir3(screen)) return 300;
310 return 120;
311
312 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
313 if (is_a6xx(screen)) return 64;
314 if (is_a5xx(screen)) return 4;
315 return 0;
316
317 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
318 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
319 return 4;
320 return 0;
321
322 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
323 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
324 return 0;
325
326 case PIPE_CAP_FBFETCH:
327 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
328 is_a6xx(screen))
329 return 1;
330 return 0;
331 case PIPE_CAP_SAMPLE_SHADING:
332 if (is_a6xx(screen)) return 1;
333 return 0;
334
335 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
336 return screen->priority_mask;
337
338 case PIPE_CAP_DRAW_INDIRECT:
339 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
340 return 1;
341 return 0;
342
343 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
344 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
345 return 1;
346 return 0;
347
348 case PIPE_CAP_LOAD_CONSTBUF:
349 /* name is confusing, but this turns on std430 packing */
350 if (is_ir3(screen))
351 return 1;
352 return 0;
353
354 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
355 return 0;
356
357 case PIPE_CAP_MAX_VIEWPORTS:
358 return 1;
359
360 case PIPE_CAP_MAX_VARYINGS:
361 return 16;
362
363 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
364 /* We don't really have a limit on this, it all goes into the main
365 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
366 * for GL_MAX_TESS_PATCH_COMPONENTS).
367 */
368 return 128;
369
370 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
371 return 64 * 1024 * 1024;
372
373 case PIPE_CAP_SHAREABLE_SHADERS:
374 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
375 /* manage the variants for these ourself, to avoid breaking precompile: */
376 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
377 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
378 if (is_ir3(screen))
379 return 1;
380 return 0;
381
382 /* Geometry shaders.. */
383 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
384 return 512;
385 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
386 return 2048;
387 case PIPE_CAP_MAX_GS_INVOCATIONS:
388 return 32;
389
390 /* Stream output. */
391 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
392 if (is_ir3(screen))
393 return PIPE_MAX_SO_BUFFERS;
394 return 0;
395 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
396 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
397 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
398 case PIPE_CAP_TGSI_TEXCOORD:
399 if (is_ir3(screen))
400 return 1;
401 return 0;
402 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
403 return 1;
404 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
405 return is_a2xx(screen);
406 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
407 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
408 if (is_ir3(screen))
409 return 16 * 4; /* should only be shader out limit? */
410 return 0;
411
412 /* Texturing. */
413 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
414 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
415 return 16384;
416 else
417 return 8192;
418 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
419 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
420 return 15;
421 else
422 return 14;
423 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
424 return 11;
425
426 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
427 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
428
429 /* Render targets. */
430 case PIPE_CAP_MAX_RENDER_TARGETS:
431 return screen->max_rts;
432 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
433 return is_a3xx(screen) ? 1 : 0;
434
435 /* Queries. */
436 case PIPE_CAP_OCCLUSION_QUERY:
437 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
438 case PIPE_CAP_QUERY_TIMESTAMP:
439 case PIPE_CAP_QUERY_TIME_ELAPSED:
440 /* only a4xx, requires new enough kernel so we know max_freq: */
441 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
442
443 case PIPE_CAP_VENDOR_ID:
444 return 0x5143;
445 case PIPE_CAP_DEVICE_ID:
446 return 0xFFFFFFFF;
447 case PIPE_CAP_ACCELERATED:
448 return 1;
449 case PIPE_CAP_VIDEO_MEMORY:
450 DBG("FINISHME: The value returned is incorrect\n");
451 return 10;
452 case PIPE_CAP_UMA:
453 return 1;
454 case PIPE_CAP_NATIVE_FENCE_FD:
455 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
456 default:
457 return u_pipe_screen_get_param_defaults(pscreen, param);
458 }
459 }
460
461 static float
462 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
463 {
464 switch (param) {
465 case PIPE_CAPF_MAX_LINE_WIDTH:
466 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
467 /* NOTE: actual value is 127.0f, but this is working around a deqp
468 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
469 * uses too small of a render target size, and gets confused when
470 * the lines start going offscreen.
471 *
472 * See: https://code.google.com/p/android/issues/detail?id=206513
473 */
474 if (fd_mesa_debug & FD_DBG_DEQP)
475 return 48.0f;
476 return 127.0f;
477 case PIPE_CAPF_MAX_POINT_WIDTH:
478 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
479 return 4092.0f;
480 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
481 return 16.0f;
482 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
483 return 15.0f;
484 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
485 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
486 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
487 return 0.0f;
488 }
489 debug_printf("unknown paramf %d\n", param);
490 return 0;
491 }
492
493 static int
494 fd_screen_get_shader_param(struct pipe_screen *pscreen,
495 enum pipe_shader_type shader,
496 enum pipe_shader_cap param)
497 {
498 struct fd_screen *screen = fd_screen(pscreen);
499
500 switch(shader)
501 {
502 case PIPE_SHADER_FRAGMENT:
503 case PIPE_SHADER_VERTEX:
504 break;
505 case PIPE_SHADER_TESS_CTRL:
506 case PIPE_SHADER_TESS_EVAL:
507 case PIPE_SHADER_GEOMETRY:
508 if (is_a6xx(screen))
509 break;
510 return 0;
511 case PIPE_SHADER_COMPUTE:
512 if (has_compute(screen))
513 break;
514 return 0;
515 default:
516 DBG("unknown shader type %d", shader);
517 return 0;
518 }
519
520 /* this is probably not totally correct.. but it's a start: */
521 switch (param) {
522 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
523 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
524 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
525 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
526 return 16384;
527 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
528 return 8; /* XXX */
529 case PIPE_SHADER_CAP_MAX_INPUTS:
530 case PIPE_SHADER_CAP_MAX_OUTPUTS:
531 return 16;
532 case PIPE_SHADER_CAP_MAX_TEMPS:
533 return 64; /* Max native temporaries. */
534 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
535 /* NOTE: seems to be limit for a3xx is actually 512 but
536 * split between VS and FS. Use lower limit of 256 to
537 * avoid getting into impossible situations:
538 */
539 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
540 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
541 return is_ir3(screen) ? 16 : 1;
542 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
543 return 1;
544 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
545 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
546 /* Technically this should be the same as for TEMP/CONST, since
547 * everything is just normal registers. This is just temporary
548 * hack until load_input/store_output handle arrays in a similar
549 * way as load_var/store_var..
550 *
551 * For tessellation stages, inputs are loaded using ldlw or ldg, both
552 * of which support indirection.
553 */
554 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
555 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
556 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
557 /* a2xx compiler doesn't handle indirect: */
558 return is_ir3(screen) ? 1 : 0;
559 case PIPE_SHADER_CAP_SUBROUTINES:
560 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
561 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
562 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
563 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
564 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
565 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
566 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
567 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
568 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
569 return 0;
570 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
571 return 1;
572 case PIPE_SHADER_CAP_INTEGERS:
573 return is_ir3(screen) ? 1 : 0;
574 case PIPE_SHADER_CAP_INT64_ATOMICS:
575 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
576 case PIPE_SHADER_CAP_INT16:
577 return 0;
578 case PIPE_SHADER_CAP_FP16:
579 return ((is_a5xx(screen) || is_a6xx(screen)) &&
580 (shader == PIPE_SHADER_COMPUTE ||
581 shader == PIPE_SHADER_FRAGMENT) &&
582 !(fd_mesa_debug & FD_DBG_NOFP16));
583 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
584 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
585 return 16;
586 case PIPE_SHADER_CAP_PREFERRED_IR:
587 return PIPE_SHADER_IR_NIR;
588 case PIPE_SHADER_CAP_SUPPORTED_IRS:
589 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
590 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
591 return 32;
592 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
593 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
594 if (is_a5xx(screen) || is_a6xx(screen)) {
595 /* a5xx (and a4xx for that matter) has one state-block
596 * for compute-shader SSBO's and another that is shared
597 * by VS/HS/DS/GS/FS.. so to simplify things for now
598 * just advertise SSBOs for FS and CS. We could possibly
599 * do what blob does, and partition the space for
600 * VS/HS/DS/GS/FS. The blob advertises:
601 *
602 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
603 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
604 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
605 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
606 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
607 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
608 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
609 *
610 * I think that way we could avoid having to patch shaders
611 * for actual SSBO indexes by using a static partitioning.
612 *
613 * Note same state block is used for images and buffers,
614 * but images also need texture state for read access
615 * (isam/isam.3d)
616 */
617 switch(shader)
618 {
619 case PIPE_SHADER_FRAGMENT:
620 case PIPE_SHADER_COMPUTE:
621 return 24;
622 default:
623 return 0;
624 }
625 }
626 return 0;
627 }
628 debug_printf("unknown shader param %d\n", param);
629 return 0;
630 }
631
632 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
633 * into per-generation backend?
634 */
635 static int
636 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
637 enum pipe_compute_cap param, void *ret)
638 {
639 struct fd_screen *screen = fd_screen(pscreen);
640 const char * const ir = "ir3";
641
642 if (!has_compute(screen))
643 return 0;
644
645 #define RET(x) do { \
646 if (ret) \
647 memcpy(ret, x, sizeof(x)); \
648 return sizeof(x); \
649 } while (0)
650
651 switch (param) {
652 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
653 // don't expose 64b pointer support yet, until ir3 supports 64b
654 // math, otherwise spir64 target is used and we get 64b pointer
655 // calculations that we can't do yet
656 // if (is_a5xx(screen))
657 // RET((uint32_t []){ 64 });
658 RET((uint32_t []){ 32 });
659
660 case PIPE_COMPUTE_CAP_IR_TARGET:
661 if (ret)
662 sprintf(ret, "%s", ir);
663 return strlen(ir) * sizeof(char);
664
665 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
666 RET((uint64_t []) { 3 });
667
668 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
669 RET(((uint64_t []) { 65535, 65535, 65535 }));
670
671 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
672 RET(((uint64_t []) { 1024, 1024, 64 }));
673
674 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
675 RET((uint64_t []) { 1024 });
676
677 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
678 RET((uint64_t []) { screen->ram_size });
679
680 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
681 RET((uint64_t []) { 32768 });
682
683 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
684 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
685 RET((uint64_t []) { 4096 });
686
687 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
688 RET((uint64_t []) { screen->ram_size });
689
690 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
691 RET((uint32_t []) { screen->max_freq / 1000000 });
692
693 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
694 RET((uint32_t []) { 9999 }); // TODO
695
696 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
697 RET((uint32_t []) { 1 });
698
699 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
700 RET((uint32_t []) { 32 }); // TODO
701
702 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
703 RET((uint64_t []) { 1024 }); // TODO
704 }
705
706 return 0;
707 }
708
709 static const void *
710 fd_get_compiler_options(struct pipe_screen *pscreen,
711 enum pipe_shader_ir ir, unsigned shader)
712 {
713 struct fd_screen *screen = fd_screen(pscreen);
714
715 if (is_ir3(screen))
716 return ir3_get_compiler_options(screen->compiler);
717
718 return ir2_get_compiler_options();
719 }
720
721 static struct disk_cache *
722 fd_get_disk_shader_cache(struct pipe_screen *pscreen)
723 {
724 struct fd_screen *screen = fd_screen(pscreen);
725
726 if (is_ir3(screen)) {
727 struct ir3_compiler *compiler = screen->compiler;
728 return compiler->disk_cache;
729 }
730
731 return NULL;
732 }
733
734 bool
735 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
736 struct fd_bo *bo,
737 struct renderonly_scanout *scanout,
738 unsigned stride,
739 struct winsys_handle *whandle)
740 {
741 whandle->stride = stride;
742
743 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
744 return fd_bo_get_name(bo, &whandle->handle) == 0;
745 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
746 if (renderonly_get_handle(scanout, whandle))
747 return true;
748 whandle->handle = fd_bo_handle(bo);
749 return true;
750 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
751 whandle->handle = fd_bo_dmabuf(bo);
752 return true;
753 } else {
754 return false;
755 }
756 }
757
758 static void
759 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
760 enum pipe_format format,
761 int max, uint64_t *modifiers,
762 unsigned int *external_only,
763 int *count)
764 {
765 struct fd_screen *screen = fd_screen(pscreen);
766 int i, num = 0;
767
768 max = MIN2(max, screen->num_supported_modifiers);
769
770 if (!max) {
771 max = screen->num_supported_modifiers;
772 external_only = NULL;
773 modifiers = NULL;
774 }
775
776 for (i = 0; i < max; i++) {
777 if (modifiers)
778 modifiers[num] = screen->supported_modifiers[i];
779
780 if (external_only)
781 external_only[num] = 0;
782
783 num++;
784 }
785
786 *count = num;
787 }
788
789 struct fd_bo *
790 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
791 struct winsys_handle *whandle)
792 {
793 struct fd_screen *screen = fd_screen(pscreen);
794 struct fd_bo *bo;
795
796 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
797 bo = fd_bo_from_name(screen->dev, whandle->handle);
798 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
799 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
800 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
801 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
802 } else {
803 DBG("Attempt to import unsupported handle type %d", whandle->type);
804 return NULL;
805 }
806
807 if (!bo) {
808 DBG("ref name 0x%08x failed", whandle->handle);
809 return NULL;
810 }
811
812 return bo;
813 }
814
815 static void _fd_fence_ref(struct pipe_screen *pscreen,
816 struct pipe_fence_handle **ptr,
817 struct pipe_fence_handle *pfence)
818 {
819 fd_fence_ref(ptr, pfence);
820 }
821
822 struct pipe_screen *
823 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
824 {
825 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
826 struct pipe_screen *pscreen;
827 uint64_t val;
828
829 fd_mesa_debug = debug_get_option_fd_mesa_debug();
830
831 if (fd_mesa_debug & FD_DBG_NOBIN)
832 fd_binning_enabled = false;
833
834 if (!screen)
835 return NULL;
836
837 pscreen = &screen->base;
838
839 screen->dev = dev;
840 screen->refcnt = 1;
841
842 if (ro) {
843 screen->ro = renderonly_dup(ro);
844 if (!screen->ro) {
845 DBG("could not create renderonly object");
846 goto fail;
847 }
848 }
849
850 // maybe this should be in context?
851 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
852 if (!screen->pipe) {
853 DBG("could not create 3d pipe");
854 goto fail;
855 }
856
857 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
858 DBG("could not get GMEM size");
859 goto fail;
860 }
861 screen->gmemsize_bytes = val;
862
863 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
864 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
865 }
866
867 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
868 DBG("could not get device-id");
869 goto fail;
870 }
871 screen->device_id = val;
872
873 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
874 DBG("could not get gpu freq");
875 /* this limits what performance related queries are
876 * supported but is not fatal
877 */
878 screen->max_freq = 0;
879 } else {
880 screen->max_freq = val;
881 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
882 screen->has_timestamp = true;
883 }
884
885 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
886 DBG("could not get gpu-id");
887 goto fail;
888 }
889 screen->gpu_id = val;
890
891 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
892 DBG("could not get chip-id");
893 /* older kernels may not have this property: */
894 unsigned core = screen->gpu_id / 100;
895 unsigned major = (screen->gpu_id % 100) / 10;
896 unsigned minor = screen->gpu_id % 10;
897 unsigned patch = 0; /* assume the worst */
898 val = (patch & 0xff) | ((minor & 0xff) << 8) |
899 ((major & 0xff) << 16) | ((core & 0xff) << 24);
900 }
901 screen->chip_id = val;
902
903 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
904 DBG("could not get # of rings");
905 screen->priority_mask = 0;
906 } else {
907 /* # of rings equates to number of unique priority values: */
908 screen->priority_mask = (1 << val) - 1;
909 }
910
911 if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
912 screen->has_robustness = true;
913
914 struct sysinfo si;
915 sysinfo(&si);
916 screen->ram_size = si.totalram;
917
918 DBG("Pipe Info:");
919 DBG(" GPU-id: %d", screen->gpu_id);
920 DBG(" Chip-id: 0x%08x", screen->chip_id);
921 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
922
923 /* explicitly checking for GPU revisions that are known to work. This
924 * may be overly conservative for a3xx, where spoofing the gpu_id with
925 * the blob driver seems to generate identical cmdstream dumps. But
926 * on a2xx, there seem to be small differences between the GPU revs
927 * so it is probably better to actually test first on real hardware
928 * before enabling:
929 *
930 * If you have a different adreno version, feel free to add it to one
931 * of the cases below and see what happens. And if it works, please
932 * send a patch ;-)
933 */
934 switch (screen->gpu_id) {
935 case 200:
936 case 201:
937 case 205:
938 case 220:
939 fd2_screen_init(pscreen);
940 break;
941 case 305:
942 case 307:
943 case 320:
944 case 330:
945 fd3_screen_init(pscreen);
946 break;
947 case 405:
948 case 420:
949 case 430:
950 fd4_screen_init(pscreen);
951 break;
952 case 510:
953 case 530:
954 case 540:
955 fd5_screen_init(pscreen);
956 break;
957 case 618:
958 case 630:
959 case 640:
960 case 650:
961 fd6_screen_init(pscreen);
962 break;
963 default:
964 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
965 goto fail;
966 }
967
968 if (screen->gpu_id >= 600) {
969 screen->gmem_alignw = 16;
970 screen->gmem_alignh = 4;
971 screen->tile_alignw = is_a650(screen) ? 96 : 32;
972 screen->tile_alignh = 32;
973 screen->num_vsc_pipes = 32;
974 } else if (screen->gpu_id >= 500) {
975 screen->gmem_alignw = screen->tile_alignw = 64;
976 screen->gmem_alignh = screen->tile_alignh = 32;
977 screen->num_vsc_pipes = 16;
978 } else {
979 screen->gmem_alignw = screen->tile_alignw = 32;
980 screen->gmem_alignh = screen->tile_alignh = 32;
981 screen->num_vsc_pipes = 8;
982 }
983
984 if (fd_mesa_debug & FD_DBG_PERFC) {
985 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
986 &screen->num_perfcntr_groups);
987 }
988
989 /* NOTE: don't enable if we have too old of a kernel to support
990 * growable cmdstream buffers, since memory requirement for cmdstream
991 * buffers would be too much otherwise.
992 */
993 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
994 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
995
996 if (BATCH_DEBUG)
997 screen->live_batches = _mesa_pointer_set_create(NULL);
998
999 fd_bc_init(&screen->batch_cache);
1000
1001 list_inithead(&screen->context_list);
1002
1003 (void) simple_mtx_init(&screen->lock, mtx_plain);
1004
1005 pscreen->destroy = fd_screen_destroy;
1006 pscreen->get_param = fd_screen_get_param;
1007 pscreen->get_paramf = fd_screen_get_paramf;
1008 pscreen->get_shader_param = fd_screen_get_shader_param;
1009 pscreen->get_compute_param = fd_get_compute_param;
1010 pscreen->get_compiler_options = fd_get_compiler_options;
1011 pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;
1012
1013 fd_resource_screen_init(pscreen);
1014 fd_query_screen_init(pscreen);
1015 fd_gmem_screen_init(pscreen);
1016
1017 pscreen->get_name = fd_screen_get_name;
1018 pscreen->get_vendor = fd_screen_get_vendor;
1019 pscreen->get_device_vendor = fd_screen_get_device_vendor;
1020
1021 pscreen->get_timestamp = fd_screen_get_timestamp;
1022
1023 pscreen->fence_reference = _fd_fence_ref;
1024 pscreen->fence_finish = fd_fence_finish;
1025 pscreen->fence_get_fd = fd_fence_get_fd;
1026
1027 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
1028
1029 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
1030
1031 return pscreen;
1032
1033 fail:
1034 fd_screen_destroy(pscreen);
1035 return NULL;
1036 }