2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
42 #include "drm-uapi/drm_fourcc.h"
46 #include <sys/sysinfo.h>
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
61 #include "ir3/ir3_nir.h"
64 static const struct debug_named_value debug_options
[] = {
65 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
66 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
67 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
68 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
69 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
70 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
71 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
72 {"log", FD_DBG_LOG
, "Enable GPU timestamp based logging (a6xx+)"},
73 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
74 {"nogmem", FD_DBG_NOGMEM
, "Disable GMEM rendering (bypass only)"},
76 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
77 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
78 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
79 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx)"},
83 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
84 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
85 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
86 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a2xx/a3xx/a5xx)"},
87 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
88 {"noubwc", FD_DBG_NOUBWC
, "Disable UBWC for all internal buffers"},
89 {"nolrz", FD_DBG_NOLRZ
, "Disable LRZ (a6xx)"},
90 {"notile", FD_DBG_NOTILE
, "Disable tiling for all internal buffers"},
91 {"layout", FD_DBG_LAYOUT
, "Dump resource layouts"},
92 {"nofp16", FD_DBG_NOFP16
, "Disable mediump precision lowering"},
93 {"nohw", FD_DBG_NOHW
, "Disable submitting commands to the HW"},
97 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
99 int fd_mesa_debug
= 0;
100 bool fd_binning_enabled
= true;
103 fd_screen_get_name(struct pipe_screen
*pscreen
)
105 static char buffer
[128];
106 snprintf(buffer
, sizeof(buffer
), "FD%03d",
107 fd_screen(pscreen
)->device_id
);
112 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
118 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
125 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
127 struct fd_screen
*screen
= fd_screen(pscreen
);
129 if (screen
->has_timestamp
) {
131 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
132 debug_assert(screen
->max_freq
> 0);
133 return n
* 1000000000 / screen
->max_freq
;
135 int64_t cpu_time
= os_time_get() * 1000;
136 return cpu_time
+ screen
->cpu_gpu_time_delta
;
142 fd_screen_destroy(struct pipe_screen
*pscreen
)
144 struct fd_screen
*screen
= fd_screen(pscreen
);
147 fd_pipe_del(screen
->pipe
);
150 fd_device_del(screen
->dev
);
155 fd_bc_fini(&screen
->batch_cache
);
156 fd_gmem_screen_fini(pscreen
);
158 slab_destroy_parent(&screen
->transfer_pool
);
160 simple_mtx_destroy(&screen
->lock
);
162 ralloc_free(screen
->compiler
);
164 free(screen
->perfcntr_queries
);
169 TODO either move caps to a2xx/a3xx specific code, or maybe have some
170 tables for things that differ if the delta is not too much..
173 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
175 struct fd_screen
*screen
= fd_screen(pscreen
);
177 /* this is probably not totally correct.. but it's a start: */
179 /* Supported features (boolean caps). */
180 case PIPE_CAP_NPOT_TEXTURES
:
181 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
182 case PIPE_CAP_ANISOTROPIC_FILTER
:
183 case PIPE_CAP_POINT_SPRITE
:
184 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
185 case PIPE_CAP_TEXTURE_SWIZZLE
:
186 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
187 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
188 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
189 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
190 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
191 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
192 case PIPE_CAP_STRING_MARKER
:
193 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
194 case PIPE_CAP_TEXTURE_BARRIER
:
195 case PIPE_CAP_INVALIDATE_BUFFER
:
196 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
199 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
200 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
201 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
202 return !is_a2xx(screen
);
204 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
205 return is_a2xx(screen
);
206 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
207 return !is_a2xx(screen
);
209 case PIPE_CAP_PACKED_UNIFORMS
:
210 return !is_a2xx(screen
);
212 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
213 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
214 return screen
->has_robustness
;
216 case PIPE_CAP_VERTEXID_NOBASE
:
217 return is_a3xx(screen
) || is_a4xx(screen
);
219 case PIPE_CAP_COMPUTE
:
220 return has_compute(screen
);
222 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
223 case PIPE_CAP_PCI_GROUP
:
224 case PIPE_CAP_PCI_BUS
:
225 case PIPE_CAP_PCI_DEVICE
:
226 case PIPE_CAP_PCI_FUNCTION
:
227 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
230 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
231 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
232 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
233 case PIPE_CAP_PRIMITIVE_RESTART
:
234 case PIPE_CAP_TGSI_INSTANCEID
:
235 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
236 case PIPE_CAP_INDEP_BLEND_ENABLE
:
237 case PIPE_CAP_INDEP_BLEND_FUNC
:
238 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
239 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
240 case PIPE_CAP_CONDITIONAL_RENDER
:
241 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
242 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
243 case PIPE_CAP_CLIP_HALFZ
:
244 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
246 case PIPE_CAP_FAKE_SW_MSAA
:
247 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
249 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
250 return is_a5xx(screen
) || is_a6xx(screen
);
252 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
253 return is_a6xx(screen
);
255 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
256 return is_a3xx(screen
) || is_a4xx(screen
);
258 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
259 return is_a5xx(screen
) || is_a6xx(screen
);
261 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
262 if (is_a3xx(screen
)) return 16;
263 if (is_a4xx(screen
)) return 32;
264 if (is_a5xx(screen
)) return 32;
265 if (is_a6xx(screen
)) return 64;
267 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
268 /* We could possibly emulate more by pretending 2d/rect textures and
269 * splitting high bits of index into 2nd dimension..
271 if (is_a3xx(screen
)) return 8192;
272 if (is_a4xx(screen
)) return 16384;
273 if (is_a5xx(screen
)) return 16384;
274 if (is_a6xx(screen
)) return 1 << 27;
277 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
278 case PIPE_CAP_CUBE_MAP_ARRAY
:
279 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
280 case PIPE_CAP_TEXTURE_QUERY_LOD
:
281 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
283 case PIPE_CAP_START_INSTANCE
:
284 /* Note that a5xx can do this, it just can't (at least with
285 * current firmware) do draw_indirect with base_instance.
286 * Since draw_indirect is needed sooner (gles31 and gl40 vs
287 * gl42), hide base_instance on a5xx. :-/
289 return is_a4xx(screen
);
291 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
294 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
295 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
296 return is_ir3(screen
) ? 140 : 120;
298 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
299 /* we can probably enable 320 for a5xx too, but need to test: */
300 if (is_a6xx(screen
)) return 320;
301 if (is_a5xx(screen
)) return 310;
302 if (is_ir3(screen
)) return 300;
305 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
306 if (is_a6xx(screen
)) return 64;
307 if (is_a5xx(screen
)) return 4;
310 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
311 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
315 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
316 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
319 case PIPE_CAP_FBFETCH
:
320 if (fd_device_version(screen
->dev
) >= FD_VERSION_GMEM_BASE
&&
324 case PIPE_CAP_SAMPLE_SHADING
:
325 if (is_a6xx(screen
)) return 1;
328 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
329 return screen
->priority_mask
;
331 case PIPE_CAP_DRAW_INDIRECT
:
332 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
336 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
337 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
341 case PIPE_CAP_LOAD_CONSTBUF
:
342 /* name is confusing, but this turns on std430 packing */
347 case PIPE_CAP_NIR_IMAGES_AS_DEREF
:
350 case PIPE_CAP_MAX_VIEWPORTS
:
353 case PIPE_CAP_MAX_VARYINGS
:
356 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
357 /* We don't really have a limit on this, it all goes into the main
358 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
359 * for GL_MAX_TESS_PATCH_COMPONENTS).
363 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
364 return 64 * 1024 * 1024;
366 case PIPE_CAP_SHAREABLE_SHADERS
:
367 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
368 /* manage the variants for these ourself, to avoid breaking precompile: */
369 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
370 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
375 /* Geometry shaders.. */
376 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
378 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
380 case PIPE_CAP_MAX_GS_INVOCATIONS
:
384 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
386 return PIPE_MAX_SO_BUFFERS
;
388 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
389 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
390 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
394 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
396 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
397 return is_a2xx(screen
);
398 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
399 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
401 return 16 * 4; /* should only be shader out limit? */
405 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
406 if (is_a6xx(screen
) || is_a5xx(screen
) || is_a4xx(screen
))
410 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
411 if (is_a6xx(screen
) || is_a5xx(screen
) || is_a4xx(screen
))
415 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
418 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
419 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
421 /* Render targets. */
422 case PIPE_CAP_MAX_RENDER_TARGETS
:
423 return screen
->max_rts
;
424 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
425 return is_a3xx(screen
) ? 1 : 0;
428 case PIPE_CAP_OCCLUSION_QUERY
:
429 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
430 case PIPE_CAP_QUERY_TIMESTAMP
:
431 case PIPE_CAP_QUERY_TIME_ELAPSED
:
432 /* only a4xx, requires new enough kernel so we know max_freq: */
433 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
435 case PIPE_CAP_VENDOR_ID
:
437 case PIPE_CAP_DEVICE_ID
:
439 case PIPE_CAP_ACCELERATED
:
441 case PIPE_CAP_VIDEO_MEMORY
:
442 DBG("FINISHME: The value returned is incorrect\n");
446 case PIPE_CAP_NATIVE_FENCE_FD
:
447 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
449 return u_pipe_screen_get_param_defaults(pscreen
, param
);
454 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
457 case PIPE_CAPF_MAX_LINE_WIDTH
:
458 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
459 /* NOTE: actual value is 127.0f, but this is working around a deqp
460 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
461 * uses too small of a render target size, and gets confused when
462 * the lines start going offscreen.
464 * See: https://code.google.com/p/android/issues/detail?id=206513
466 if (fd_mesa_debug
& FD_DBG_DEQP
)
469 case PIPE_CAPF_MAX_POINT_WIDTH
:
470 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
472 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
474 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
476 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
477 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
478 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
481 debug_printf("unknown paramf %d\n", param
);
486 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
487 enum pipe_shader_type shader
,
488 enum pipe_shader_cap param
)
490 struct fd_screen
*screen
= fd_screen(pscreen
);
494 case PIPE_SHADER_FRAGMENT
:
495 case PIPE_SHADER_VERTEX
:
497 case PIPE_SHADER_TESS_CTRL
:
498 case PIPE_SHADER_TESS_EVAL
:
499 case PIPE_SHADER_GEOMETRY
:
503 case PIPE_SHADER_COMPUTE
:
504 if (has_compute(screen
))
508 DBG("unknown shader type %d", shader
);
512 /* this is probably not totally correct.. but it's a start: */
514 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
515 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
516 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
517 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
519 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
521 case PIPE_SHADER_CAP_MAX_INPUTS
:
522 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
524 case PIPE_SHADER_CAP_MAX_TEMPS
:
525 return 64; /* Max native temporaries. */
526 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
527 /* NOTE: seems to be limit for a3xx is actually 512 but
528 * split between VS and FS. Use lower limit of 256 to
529 * avoid getting into impossible situations:
531 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
532 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
533 return is_ir3(screen
) ? 16 : 1;
534 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
536 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
537 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
538 /* Technically this should be the same as for TEMP/CONST, since
539 * everything is just normal registers. This is just temporary
540 * hack until load_input/store_output handle arrays in a similar
541 * way as load_var/store_var..
543 * For tessellation stages, inputs are loaded using ldlw or ldg, both
544 * of which support indirection.
546 return shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
;
547 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
548 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
549 /* a2xx compiler doesn't handle indirect: */
550 return is_ir3(screen
) ? 1 : 0;
551 case PIPE_SHADER_CAP_SUBROUTINES
:
552 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
553 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
554 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
555 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
556 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
557 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
558 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
559 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
560 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
562 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
564 case PIPE_SHADER_CAP_INTEGERS
:
565 return is_ir3(screen
) ? 1 : 0;
566 case PIPE_SHADER_CAP_INT64_ATOMICS
:
568 case PIPE_SHADER_CAP_FP16
:
569 return ((is_a5xx(screen
) || is_a6xx(screen
)) &&
570 (shader
== PIPE_SHADER_COMPUTE
||
571 shader
== PIPE_SHADER_FRAGMENT
) &&
572 !(fd_mesa_debug
& FD_DBG_NOFP16
));
573 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
574 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
576 case PIPE_SHADER_CAP_PREFERRED_IR
:
577 return PIPE_SHADER_IR_NIR
;
578 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
579 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
580 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
582 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
583 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
584 if (is_a5xx(screen
) || is_a6xx(screen
)) {
585 /* a5xx (and a4xx for that matter) has one state-block
586 * for compute-shader SSBO's and another that is shared
587 * by VS/HS/DS/GS/FS.. so to simplify things for now
588 * just advertise SSBOs for FS and CS. We could possibly
589 * do what blob does, and partition the space for
590 * VS/HS/DS/GS/FS. The blob advertises:
592 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
593 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
594 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
595 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
596 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
597 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
598 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
600 * I think that way we could avoid having to patch shaders
601 * for actual SSBO indexes by using a static partitioning.
603 * Note same state block is used for images and buffers,
604 * but images also need texture state for read access
609 case PIPE_SHADER_FRAGMENT
:
610 case PIPE_SHADER_COMPUTE
:
618 debug_printf("unknown shader param %d\n", param
);
622 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
623 * into per-generation backend?
626 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
627 enum pipe_compute_cap param
, void *ret
)
629 struct fd_screen
*screen
= fd_screen(pscreen
);
630 const char * const ir
= "ir3";
632 if (!has_compute(screen
))
635 #define RET(x) do { \
637 memcpy(ret, x, sizeof(x)); \
642 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
643 // don't expose 64b pointer support yet, until ir3 supports 64b
644 // math, otherwise spir64 target is used and we get 64b pointer
645 // calculations that we can't do yet
646 // if (is_a5xx(screen))
647 // RET((uint32_t []){ 64 });
648 RET((uint32_t []){ 32 });
650 case PIPE_COMPUTE_CAP_IR_TARGET
:
652 sprintf(ret
, "%s", ir
);
653 return strlen(ir
) * sizeof(char);
655 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
656 RET((uint64_t []) { 3 });
658 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
659 RET(((uint64_t []) { 65535, 65535, 65535 }));
661 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
662 RET(((uint64_t []) { 1024, 1024, 64 }));
664 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
665 RET((uint64_t []) { 1024 });
667 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
668 RET((uint64_t []) { screen
->ram_size
});
670 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
671 RET((uint64_t []) { 32768 });
673 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
674 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
675 RET((uint64_t []) { 4096 });
677 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
678 RET((uint64_t []) { screen
->ram_size
});
680 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
681 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
683 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
684 RET((uint32_t []) { 9999 }); // TODO
686 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
687 RET((uint32_t []) { 1 });
689 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
690 RET((uint32_t []) { 32 }); // TODO
692 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
693 RET((uint64_t []) { 1024 }); // TODO
700 fd_get_compiler_options(struct pipe_screen
*pscreen
,
701 enum pipe_shader_ir ir
, unsigned shader
)
703 struct fd_screen
*screen
= fd_screen(pscreen
);
706 return ir3_get_compiler_options(screen
->compiler
);
708 return ir2_get_compiler_options();
712 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
714 struct renderonly_scanout
*scanout
,
716 struct winsys_handle
*whandle
)
718 whandle
->stride
= stride
;
720 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
721 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
722 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
723 if (renderonly_get_handle(scanout
, whandle
))
725 whandle
->handle
= fd_bo_handle(bo
);
727 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
728 whandle
->handle
= fd_bo_dmabuf(bo
);
736 fd_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
737 enum pipe_format format
,
738 int max
, uint64_t *modifiers
,
739 unsigned int *external_only
,
742 struct fd_screen
*screen
= fd_screen(pscreen
);
745 max
= MIN2(max
, screen
->num_supported_modifiers
);
748 max
= screen
->num_supported_modifiers
;
749 external_only
= NULL
;
753 for (i
= 0; i
< max
; i
++) {
755 modifiers
[num
] = screen
->supported_modifiers
[i
];
758 external_only
[num
] = 0;
767 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
768 struct winsys_handle
*whandle
)
770 struct fd_screen
*screen
= fd_screen(pscreen
);
773 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
774 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
775 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
776 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
777 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
778 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
780 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
785 DBG("ref name 0x%08x failed", whandle
->handle
);
792 static void _fd_fence_ref(struct pipe_screen
*pscreen
,
793 struct pipe_fence_handle
**ptr
,
794 struct pipe_fence_handle
*pfence
)
796 fd_fence_ref(ptr
, pfence
);
800 fd_screen_create(struct fd_device
*dev
, struct renderonly
*ro
)
802 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
803 struct pipe_screen
*pscreen
;
806 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
808 if (fd_mesa_debug
& FD_DBG_NOBIN
)
809 fd_binning_enabled
= false;
814 pscreen
= &screen
->base
;
820 screen
->ro
= renderonly_dup(ro
);
822 DBG("could not create renderonly object");
827 // maybe this should be in context?
828 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
830 DBG("could not create 3d pipe");
834 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
835 DBG("could not get GMEM size");
838 screen
->gmemsize_bytes
= val
;
840 if (fd_device_version(dev
) >= FD_VERSION_GMEM_BASE
) {
841 fd_pipe_get_param(screen
->pipe
, FD_GMEM_BASE
, &screen
->gmem_base
);
844 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
845 DBG("could not get device-id");
848 screen
->device_id
= val
;
850 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
851 DBG("could not get gpu freq");
852 /* this limits what performance related queries are
853 * supported but is not fatal
855 screen
->max_freq
= 0;
857 screen
->max_freq
= val
;
858 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
859 screen
->has_timestamp
= true;
862 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
863 DBG("could not get gpu-id");
866 screen
->gpu_id
= val
;
868 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
869 DBG("could not get chip-id");
870 /* older kernels may not have this property: */
871 unsigned core
= screen
->gpu_id
/ 100;
872 unsigned major
= (screen
->gpu_id
% 100) / 10;
873 unsigned minor
= screen
->gpu_id
% 10;
874 unsigned patch
= 0; /* assume the worst */
875 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
876 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
878 screen
->chip_id
= val
;
880 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
881 DBG("could not get # of rings");
882 screen
->priority_mask
= 0;
884 /* # of rings equates to number of unique priority values: */
885 screen
->priority_mask
= (1 << val
) - 1;
888 if ((fd_device_version(dev
) >= FD_VERSION_ROBUSTNESS
) &&
889 (fd_pipe_get_param(screen
->pipe
, FD_PP_PGTABLE
, &val
) == 0)) {
890 screen
->has_robustness
= val
;
895 screen
->ram_size
= si
.totalram
;
898 DBG(" GPU-id: %d", screen
->gpu_id
);
899 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
900 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
902 /* explicitly checking for GPU revisions that are known to work. This
903 * may be overly conservative for a3xx, where spoofing the gpu_id with
904 * the blob driver seems to generate identical cmdstream dumps. But
905 * on a2xx, there seem to be small differences between the GPU revs
906 * so it is probably better to actually test first on real hardware
909 * If you have a different adreno version, feel free to add it to one
910 * of the cases below and see what happens. And if it works, please
913 switch (screen
->gpu_id
) {
918 fd2_screen_init(pscreen
);
924 fd3_screen_init(pscreen
);
929 fd4_screen_init(pscreen
);
934 fd5_screen_init(pscreen
);
939 fd6_screen_init(pscreen
);
942 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
946 if (screen
->gpu_id
>= 600) {
947 screen
->gmem_alignw
= 16;
948 screen
->gmem_alignh
= 4;
949 screen
->tile_alignw
= 32;
950 screen
->tile_alignh
= 32;
951 screen
->num_vsc_pipes
= 32;
952 } else if (screen
->gpu_id
>= 500) {
953 screen
->gmem_alignw
= screen
->tile_alignw
= 64;
954 screen
->gmem_alignh
= screen
->tile_alignh
= 32;
955 screen
->num_vsc_pipes
= 16;
957 screen
->gmem_alignw
= screen
->tile_alignw
= 32;
958 screen
->gmem_alignh
= screen
->tile_alignh
= 32;
959 screen
->num_vsc_pipes
= 8;
962 if (fd_mesa_debug
& FD_DBG_PERFC
) {
963 screen
->perfcntr_groups
= fd_perfcntrs(screen
->gpu_id
,
964 &screen
->num_perfcntr_groups
);
967 /* NOTE: don't enable if we have too old of a kernel to support
968 * growable cmdstream buffers, since memory requirement for cmdstream
969 * buffers would be too much otherwise.
971 if (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
)
972 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
974 fd_bc_init(&screen
->batch_cache
);
976 list_inithead(&screen
->context_list
);
978 (void) simple_mtx_init(&screen
->lock
, mtx_plain
);
980 pscreen
->destroy
= fd_screen_destroy
;
981 pscreen
->get_param
= fd_screen_get_param
;
982 pscreen
->get_paramf
= fd_screen_get_paramf
;
983 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
984 pscreen
->get_compute_param
= fd_get_compute_param
;
985 pscreen
->get_compiler_options
= fd_get_compiler_options
;
987 fd_resource_screen_init(pscreen
);
988 fd_query_screen_init(pscreen
);
989 fd_gmem_screen_init(pscreen
);
991 pscreen
->get_name
= fd_screen_get_name
;
992 pscreen
->get_vendor
= fd_screen_get_vendor
;
993 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
995 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
997 pscreen
->fence_reference
= _fd_fence_ref
;
998 pscreen
->fence_finish
= fd_fence_finish
;
999 pscreen
->fence_get_fd
= fd_fence_get_fd
;
1001 pscreen
->query_dmabuf_modifiers
= fd_screen_query_dmabuf_modifiers
;
1003 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
1008 fd_screen_destroy(pscreen
);