2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
45 #include <sys/sysinfo.h>
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57 #include "a6xx/fd6_screen.h"
60 #include "ir3/ir3_nir.h"
63 /* XXX this should go away */
64 #include "state_tracker/drm_driver.h"
66 static const struct debug_named_value debug_options
[] = {
67 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
68 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
69 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
70 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
71 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
72 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
73 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
74 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
75 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
76 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
77 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
78 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
79 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
80 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
81 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
82 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
83 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
84 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
85 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
86 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
87 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a5xx)"},
88 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
89 {"softpin", FD_DBG_SOFTPIN
,"Enable softpin command submission (experimental)"},
93 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
95 int fd_mesa_debug
= 0;
96 bool fd_binning_enabled
= true;
97 static bool glsl120
= false;
100 fd_screen_get_name(struct pipe_screen
*pscreen
)
102 static char buffer
[128];
103 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
104 fd_screen(pscreen
)->device_id
);
109 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
115 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
122 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
124 struct fd_screen
*screen
= fd_screen(pscreen
);
126 if (screen
->has_timestamp
) {
128 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
129 debug_assert(screen
->max_freq
> 0);
130 return n
* 1000000000 / screen
->max_freq
;
132 int64_t cpu_time
= os_time_get() * 1000;
133 return cpu_time
+ screen
->cpu_gpu_time_delta
;
139 fd_screen_destroy(struct pipe_screen
*pscreen
)
141 struct fd_screen
*screen
= fd_screen(pscreen
);
144 fd_pipe_del(screen
->pipe
);
147 fd_device_del(screen
->dev
);
149 fd_bc_fini(&screen
->batch_cache
);
151 slab_destroy_parent(&screen
->transfer_pool
);
153 mtx_destroy(&screen
->lock
);
155 ralloc_free(screen
->compiler
);
157 free(screen
->perfcntr_queries
);
162 TODO either move caps to a2xx/a3xx specific code, or maybe have some
163 tables for things that differ if the delta is not too much..
166 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
168 struct fd_screen
*screen
= fd_screen(pscreen
);
170 /* this is probably not totally correct.. but it's a start: */
172 /* Supported features (boolean caps). */
173 case PIPE_CAP_NPOT_TEXTURES
:
174 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
175 case PIPE_CAP_ANISOTROPIC_FILTER
:
176 case PIPE_CAP_POINT_SPRITE
:
177 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
178 case PIPE_CAP_TEXTURE_SWIZZLE
:
179 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
180 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
181 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
182 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
183 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
184 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
185 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
186 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
187 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
188 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
189 case PIPE_CAP_STRING_MARKER
:
190 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
191 case PIPE_CAP_TEXTURE_BARRIER
:
192 case PIPE_CAP_INVALIDATE_BUFFER
:
195 case PIPE_CAP_VERTEXID_NOBASE
:
196 return is_a3xx(screen
) || is_a4xx(screen
);
198 case PIPE_CAP_COMPUTE
:
199 return has_compute(screen
);
201 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
202 case PIPE_CAP_PCI_GROUP
:
203 case PIPE_CAP_PCI_BUS
:
204 case PIPE_CAP_PCI_DEVICE
:
205 case PIPE_CAP_PCI_FUNCTION
:
206 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
210 case PIPE_CAP_PRIMITIVE_RESTART
:
211 case PIPE_CAP_TGSI_INSTANCEID
:
212 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
213 case PIPE_CAP_INDEP_BLEND_ENABLE
:
214 case PIPE_CAP_INDEP_BLEND_FUNC
:
215 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
216 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
217 case PIPE_CAP_CONDITIONAL_RENDER
:
218 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
219 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
220 case PIPE_CAP_CLIP_HALFZ
:
221 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
223 case PIPE_CAP_FAKE_SW_MSAA
:
224 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
226 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
227 return is_a5xx(screen
) || is_a6xx(screen
);
229 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
230 return is_a6xx(screen
);
232 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
233 return is_a3xx(screen
) || is_a4xx(screen
);
235 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
236 return is_a5xx(screen
) || is_a6xx(screen
);
238 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
239 if (is_a3xx(screen
)) return 16;
240 if (is_a4xx(screen
)) return 32;
241 if (is_a5xx(screen
)) return 32;
242 if (is_a6xx(screen
)) return 32;
244 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
245 /* We could possibly emulate more by pretending 2d/rect textures and
246 * splitting high bits of index into 2nd dimension..
248 if (is_a3xx(screen
)) return 8192;
249 if (is_a4xx(screen
)) return 16384;
250 if (is_a5xx(screen
)) return 16384;
251 if (is_a6xx(screen
)) return 16384;
254 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
255 case PIPE_CAP_CUBE_MAP_ARRAY
:
256 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
257 case PIPE_CAP_TEXTURE_QUERY_LOD
:
258 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
260 case PIPE_CAP_START_INSTANCE
:
261 /* Note that a5xx can do this, it just can't (at least with
262 * current firmware) do draw_indirect with base_instance.
263 * Since draw_indirect is needed sooner (gles31 and gl40 vs
264 * gl42), hide base_instance on a5xx. :-/
266 return is_a4xx(screen
);
268 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
271 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
272 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
275 return is_ir3(screen
) ? 140 : 120;
277 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
278 if (is_a5xx(screen
) || is_a6xx(screen
))
282 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
283 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
287 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
288 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
291 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
294 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
295 return screen
->priority_mask
;
297 case PIPE_CAP_DRAW_INDIRECT
:
298 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
302 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
303 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
307 case PIPE_CAP_LOAD_CONSTBUF
:
308 /* name is confusing, but this turns on std430 packing */
313 case PIPE_CAP_MAX_VIEWPORTS
:
316 case PIPE_CAP_SHAREABLE_SHADERS
:
317 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
318 /* manage the variants for these ourself, to avoid breaking precompile: */
319 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
320 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
326 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
328 return PIPE_MAX_SO_BUFFERS
;
330 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
331 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
335 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
336 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
338 return 16 * 4; /* should only be shader out limit? */
342 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
343 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
344 return MAX_MIP_LEVELS
;
345 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
348 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
349 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
351 /* Render targets. */
352 case PIPE_CAP_MAX_RENDER_TARGETS
:
353 return screen
->max_rts
;
354 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
355 return is_a3xx(screen
) ? 1 : 0;
358 case PIPE_CAP_OCCLUSION_QUERY
:
359 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
360 case PIPE_CAP_QUERY_TIMESTAMP
:
361 case PIPE_CAP_QUERY_TIME_ELAPSED
:
362 /* only a4xx, requires new enough kernel so we know max_freq: */
363 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
365 case PIPE_CAP_VENDOR_ID
:
367 case PIPE_CAP_DEVICE_ID
:
369 case PIPE_CAP_ACCELERATED
:
371 case PIPE_CAP_VIDEO_MEMORY
:
372 DBG("FINISHME: The value returned is incorrect\n");
376 case PIPE_CAP_NATIVE_FENCE_FD
:
377 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
379 return u_pipe_screen_get_param_defaults(pscreen
, param
);
384 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
387 case PIPE_CAPF_MAX_LINE_WIDTH
:
388 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
389 /* NOTE: actual value is 127.0f, but this is working around a deqp
390 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
391 * uses too small of a render target size, and gets confused when
392 * the lines start going offscreen.
394 * See: https://code.google.com/p/android/issues/detail?id=206513
396 if (fd_mesa_debug
& FD_DBG_DEQP
)
399 case PIPE_CAPF_MAX_POINT_WIDTH
:
400 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
402 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
404 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
406 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
407 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
408 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
411 debug_printf("unknown paramf %d\n", param
);
416 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
417 enum pipe_shader_type shader
,
418 enum pipe_shader_cap param
)
420 struct fd_screen
*screen
= fd_screen(pscreen
);
424 case PIPE_SHADER_FRAGMENT
:
425 case PIPE_SHADER_VERTEX
:
427 case PIPE_SHADER_COMPUTE
:
428 if (has_compute(screen
))
431 case PIPE_SHADER_GEOMETRY
:
432 /* maye we could emulate.. */
435 DBG("unknown shader type %d", shader
);
439 /* this is probably not totally correct.. but it's a start: */
441 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
442 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
443 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
444 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
446 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
448 case PIPE_SHADER_CAP_MAX_INPUTS
:
449 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
451 case PIPE_SHADER_CAP_MAX_TEMPS
:
452 return 64; /* Max native temporaries. */
453 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
454 /* NOTE: seems to be limit for a3xx is actually 512 but
455 * split between VS and FS. Use lower limit of 256 to
456 * avoid getting into impossible situations:
458 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
459 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
460 return is_ir3(screen
) ? 16 : 1;
461 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
463 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
464 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
465 /* Technically this should be the same as for TEMP/CONST, since
466 * everything is just normal registers. This is just temporary
467 * hack until load_input/store_output handle arrays in a similar
468 * way as load_var/store_var..
471 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
472 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
473 /* a2xx compiler doesn't handle indirect: */
474 return is_ir3(screen
) ? 1 : 0;
475 case PIPE_SHADER_CAP_SUBROUTINES
:
476 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
477 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
478 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
479 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
480 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
481 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
482 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
483 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
484 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
486 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
488 case PIPE_SHADER_CAP_INTEGERS
:
491 return is_ir3(screen
) ? 1 : 0;
492 case PIPE_SHADER_CAP_INT64_ATOMICS
:
494 case PIPE_SHADER_CAP_FP16
:
496 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
497 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
499 case PIPE_SHADER_CAP_PREFERRED_IR
:
500 return PIPE_SHADER_IR_NIR
;
501 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
502 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
503 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
505 case PIPE_SHADER_CAP_SCALAR_ISA
:
506 return is_ir3(screen
) ? 1 : 0;
507 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
508 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
509 if (is_a5xx(screen
) || is_a6xx(screen
)) {
510 /* a5xx (and a4xx for that matter) has one state-block
511 * for compute-shader SSBO's and another that is shared
512 * by VS/HS/DS/GS/FS.. so to simplify things for now
513 * just advertise SSBOs for FS and CS. We could possibly
514 * do what blob does, and partition the space for
515 * VS/HS/DS/GS/FS. The blob advertises:
517 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
518 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
519 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
520 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
521 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
522 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
523 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
525 * I think that way we could avoid having to patch shaders
526 * for actual SSBO indexes by using a static partitioning.
528 * Note same state block is used for images and buffers,
529 * but images also need texture state for read access
534 case PIPE_SHADER_FRAGMENT
:
535 case PIPE_SHADER_COMPUTE
:
543 debug_printf("unknown shader param %d\n", param
);
547 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
548 * into per-generation backend?
551 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
552 enum pipe_compute_cap param
, void *ret
)
554 struct fd_screen
*screen
= fd_screen(pscreen
);
555 const char * const ir
= "ir3";
557 if (!has_compute(screen
))
560 #define RET(x) do { \
562 memcpy(ret, x, sizeof(x)); \
567 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
568 // don't expose 64b pointer support yet, until ir3 supports 64b
569 // math, otherwise spir64 target is used and we get 64b pointer
570 // calculations that we can't do yet
571 // if (is_a5xx(screen))
572 // RET((uint32_t []){ 64 });
573 RET((uint32_t []){ 32 });
575 case PIPE_COMPUTE_CAP_IR_TARGET
:
578 return strlen(ir
) * sizeof(char);
580 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
581 RET((uint64_t []) { 3 });
583 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
584 RET(((uint64_t []) { 65535, 65535, 65535 }));
586 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
587 RET(((uint64_t []) { 1024, 1024, 64 }));
589 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
590 RET((uint64_t []) { 1024 });
592 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
593 RET((uint64_t []) { screen
->ram_size
});
595 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
596 RET((uint64_t []) { 32768 });
598 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
599 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
600 RET((uint64_t []) { 4096 });
602 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
603 RET((uint64_t []) { screen
->ram_size
});
605 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
606 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
608 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
609 RET((uint32_t []) { 9999 }); // TODO
611 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
612 RET((uint32_t []) { 1 });
614 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
615 RET((uint32_t []) { 32 }); // TODO
617 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
618 RET((uint64_t []) { 1024 }); // TODO
625 fd_get_compiler_options(struct pipe_screen
*pscreen
,
626 enum pipe_shader_ir ir
, unsigned shader
)
628 struct fd_screen
*screen
= fd_screen(pscreen
);
631 return ir3_get_compiler_options(screen
->compiler
);
633 return ir2_get_compiler_options();
637 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
640 struct winsys_handle
*whandle
)
642 whandle
->stride
= stride
;
644 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
645 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
646 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
647 whandle
->handle
= fd_bo_handle(bo
);
649 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
650 whandle
->handle
= fd_bo_dmabuf(bo
);
658 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
659 struct winsys_handle
*whandle
)
661 struct fd_screen
*screen
= fd_screen(pscreen
);
664 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
665 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
666 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
667 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
668 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
669 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
671 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
676 DBG("ref name 0x%08x failed", whandle
->handle
);
684 fd_screen_create(struct fd_device
*dev
)
686 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
687 struct pipe_screen
*pscreen
;
690 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
692 if (fd_mesa_debug
& FD_DBG_NOBIN
)
693 fd_binning_enabled
= false;
695 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
700 pscreen
= &screen
->base
;
705 // maybe this should be in context?
706 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
708 DBG("could not create 3d pipe");
712 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
713 DBG("could not get GMEM size");
716 screen
->gmemsize_bytes
= val
;
718 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
719 DBG("could not get device-id");
722 screen
->device_id
= val
;
724 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
725 DBG("could not get gpu freq");
726 /* this limits what performance related queries are
727 * supported but is not fatal
729 screen
->max_freq
= 0;
731 screen
->max_freq
= val
;
732 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
733 screen
->has_timestamp
= true;
736 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
737 DBG("could not get gpu-id");
740 screen
->gpu_id
= val
;
742 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
743 DBG("could not get chip-id");
744 /* older kernels may not have this property: */
745 unsigned core
= screen
->gpu_id
/ 100;
746 unsigned major
= (screen
->gpu_id
% 100) / 10;
747 unsigned minor
= screen
->gpu_id
% 10;
748 unsigned patch
= 0; /* assume the worst */
749 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
750 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
752 screen
->chip_id
= val
;
754 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
755 DBG("could not get # of rings");
756 screen
->priority_mask
= 0;
758 /* # of rings equates to number of unique priority values: */
759 screen
->priority_mask
= (1 << val
) - 1;
764 screen
->ram_size
= si
.totalram
;
767 DBG(" GPU-id: %d", screen
->gpu_id
);
768 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
769 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
771 /* explicitly checking for GPU revisions that are known to work. This
772 * may be overly conservative for a3xx, where spoofing the gpu_id with
773 * the blob driver seems to generate identical cmdstream dumps. But
774 * on a2xx, there seem to be small differences between the GPU revs
775 * so it is probably better to actually test first on real hardware
778 * If you have a different adreno version, feel free to add it to one
779 * of the cases below and see what happens. And if it works, please
782 switch (screen
->gpu_id
) {
787 fd2_screen_init(pscreen
);
793 fd3_screen_init(pscreen
);
797 fd4_screen_init(pscreen
);
800 fd5_screen_init(pscreen
);
803 fd6_screen_init(pscreen
);
806 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
810 if (screen
->gpu_id
>= 600) {
811 screen
->gmem_alignw
= 32;
812 screen
->gmem_alignh
= 32;
813 screen
->num_vsc_pipes
= 32;
814 } else if (screen
->gpu_id
>= 500) {
815 screen
->gmem_alignw
= 64;
816 screen
->gmem_alignh
= 32;
817 screen
->num_vsc_pipes
= 16;
819 screen
->gmem_alignw
= 32;
820 screen
->gmem_alignh
= 32;
821 screen
->num_vsc_pipes
= 8;
824 /* NOTE: don't enable reordering on a2xx, since completely untested.
825 * Also, don't enable if we have too old of a kernel to support
826 * growable cmdstream buffers, since memory requirement for cmdstream
827 * buffers would be too much otherwise.
829 if ((screen
->gpu_id
>= 300) && (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
))
830 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
832 fd_bc_init(&screen
->batch_cache
);
834 (void) mtx_init(&screen
->lock
, mtx_plain
);
836 pscreen
->destroy
= fd_screen_destroy
;
837 pscreen
->get_param
= fd_screen_get_param
;
838 pscreen
->get_paramf
= fd_screen_get_paramf
;
839 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
840 pscreen
->get_compute_param
= fd_get_compute_param
;
841 pscreen
->get_compiler_options
= fd_get_compiler_options
;
843 fd_resource_screen_init(pscreen
);
844 fd_query_screen_init(pscreen
);
846 pscreen
->get_name
= fd_screen_get_name
;
847 pscreen
->get_vendor
= fd_screen_get_vendor
;
848 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
850 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
852 pscreen
->fence_reference
= fd_fence_ref
;
853 pscreen
->fence_finish
= fd_fence_finish
;
854 pscreen
->fence_get_fd
= fd_fence_get_fd
;
856 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
861 fd_screen_destroy(pscreen
);