src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58
  59 #include "ir3/ir3_nir.h"
  60
  61 /* XXX this should go away */
  62 #include "state_tracker/drm_driver.h"
  63
  64 static const struct debug_named_value debug_options[] = {
  65                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  66                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  67                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  68                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  69                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  70                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  71                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  72                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  73                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  74                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  75                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  76                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  77                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  78                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  79                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  82                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  83                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  84                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  85                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  86                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  87                 DEBUG_NAMED_VALUE_END
  88 };
  89
  90 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  91
  92 int fd_mesa_debug = 0;
  93 bool fd_binning_enabled = true;
  94 static bool glsl120 = false;
  95
  96 static const struct debug_named_value shader_debug_options[] = {
  97                 {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
  98                 {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
  99                 {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
 100                 DEBUG_NAMED_VALUE_END
 101 };
 102
 103 DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
 104
 105 enum fd_shader_debug fd_shader_debug = 0;
 106
 107 static const char *
 108 fd_screen_get_name(struct pipe_screen *pscreen)
 109 {
 110         static char buffer[128];
 111         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 112                         fd_screen(pscreen)->device_id);
 113         return buffer;
 114 }
 115
 116 static const char *
 117 fd_screen_get_vendor(struct pipe_screen *pscreen)
 118 {
 119         return "freedreno";
 120 }
 121
 122 static const char *
 123 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 124 {
 125         return "Qualcomm";
 126 }
 127
 128
 129 static uint64_t
 130 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 131 {
 132         struct fd_screen *screen = fd_screen(pscreen);
 133
 134         if (screen->has_timestamp) {
 135                 uint64_t n;
 136                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 137                 debug_assert(screen->max_freq > 0);
 138                 return n * 1000000000 / screen->max_freq;
 139         } else {
 140                 int64_t cpu_time = os_time_get() * 1000;
 141                 return cpu_time + screen->cpu_gpu_time_delta;
 142         }
 143
 144 }
 145
 146 static void
 147 fd_screen_destroy(struct pipe_screen *pscreen)
 148 {
 149         struct fd_screen *screen = fd_screen(pscreen);
 150
 151         if (screen->pipe)
 152                 fd_pipe_del(screen->pipe);
 153
 154         if (screen->dev)
 155                 fd_device_del(screen->dev);
 156
 157         fd_bc_fini(&screen->batch_cache);
 158
 159         slab_destroy_parent(&screen->transfer_pool);
 160
 161         mtx_destroy(&screen->lock);
 162
 163         ralloc_free(screen->compiler);
 164
 165         free(screen);
 166 }
 167
 168 /*
 169 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 170 tables for things that differ if the delta is not too much..
 171  */
 172 static int
 173 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 174 {
 175         struct fd_screen *screen = fd_screen(pscreen);
 176
 177         /* this is probably not totally correct.. but it's a start: */
 178         switch (param) {
 179         /* Supported features (boolean caps). */
 180         case PIPE_CAP_NPOT_TEXTURES:
 181         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 182         case PIPE_CAP_ANISOTROPIC_FILTER:
 183         case PIPE_CAP_POINT_SPRITE:
 184         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 185         case PIPE_CAP_TEXTURE_SWIZZLE:
 186         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 187         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 188         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 189         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 190         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 191         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 192         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 193         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 194         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 195         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 196         case PIPE_CAP_STRING_MARKER:
 197         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 198         case PIPE_CAP_TEXTURE_BARRIER:
 199         case PIPE_CAP_INVALIDATE_BUFFER:
 200                 return 1;
 201
 202         case PIPE_CAP_VERTEXID_NOBASE:
 203                 return is_a3xx(screen) || is_a4xx(screen);
 204
 205         case PIPE_CAP_COMPUTE:
 206                 return has_compute(screen);
 207
 208         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 209         case PIPE_CAP_TGSI_TEXCOORD:
 210         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 211         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 212         case PIPE_CAP_QUERY_MEMORY_INFO:
 213         case PIPE_CAP_PCI_GROUP:
 214         case PIPE_CAP_PCI_BUS:
 215         case PIPE_CAP_PCI_DEVICE:
 216         case PIPE_CAP_PCI_FUNCTION:
 217                 return 0;
 218
 219         case PIPE_CAP_SM3:
 220         case PIPE_CAP_PRIMITIVE_RESTART:
 221         case PIPE_CAP_TGSI_INSTANCEID:
 222         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 223         case PIPE_CAP_INDEP_BLEND_ENABLE:
 224         case PIPE_CAP_INDEP_BLEND_FUNC:
 225         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 226         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 227         case PIPE_CAP_CONDITIONAL_RENDER:
 228         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 229         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 230         case PIPE_CAP_CLIP_HALFZ:
 231                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 232
 233         case PIPE_CAP_FAKE_SW_MSAA:
 234                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 235
 236         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 237                 return is_a5xx(screen);
 238
 239         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 240                 return is_a3xx(screen) || is_a4xx(screen);
 241
 242         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 243                 return is_a5xx(screen);
 244
 245         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 246                 return 0;
 247         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 248                 if (is_a3xx(screen)) return 16;
 249                 if (is_a4xx(screen)) return 32;
 250                 if (is_a5xx(screen)) return 32;
 251                 return 0;
 252         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 253                 /* We could possibly emulate more by pretending 2d/rect textures and
 254                  * splitting high bits of index into 2nd dimension..
 255                  */
 256                 if (is_a3xx(screen)) return 8192;
 257                 if (is_a4xx(screen)) return 16384;
 258                 if (is_a5xx(screen)) return 16384;
 259                 return 0;
 260
 261         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 262         case PIPE_CAP_CUBE_MAP_ARRAY:
 263         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 264         case PIPE_CAP_TEXTURE_QUERY_LOD:
 265                 return is_a4xx(screen) || is_a5xx(screen);
 266
 267         case PIPE_CAP_START_INSTANCE:
 268                 /* Note that a5xx can do this, it just can't (at least with
 269                  * current firmware) do draw_indirect with base_instance.
 270                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 271                  * gl42), hide base_instance on a5xx.  :-/
 272                  */
 273                 return is_a4xx(screen);
 274
 275         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 276                 return 64;
 277
 278         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 279         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 280                 if (glsl120)
 281                         return 120;
 282                 return is_ir3(screen) ? 140 : 120;
 283
 284         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 285                 if (is_a5xx(screen))
 286                         return 4;
 287                 return 0;
 288
 289         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 290                 if (is_a4xx(screen) || is_a5xx(screen))
 291                         return 4;
 292                 return 0;
 293
 294         /* Unsupported features. */
 295         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 296         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 297         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 298         case PIPE_CAP_USER_VERTEX_BUFFERS:
 299         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 300         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 301         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 302         case PIPE_CAP_TEXTURE_GATHER_SM5:
 303         case PIPE_CAP_SAMPLE_SHADING:
 304         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 305         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 306         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 307         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 308         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 309         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 310         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 311         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 312         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 313         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 314         case PIPE_CAP_TGSI_TXQS:
 315         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 316         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 317         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 318         case PIPE_CAP_CLEAR_TEXTURE:
 319         case PIPE_CAP_DRAW_PARAMETERS:
 320         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 321         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 322         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 323         case PIPE_CAP_GENERATE_MIPMAP:
 324         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 325         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 326         case PIPE_CAP_CULL_DISTANCE:
 327         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 328         case PIPE_CAP_TGSI_VOTE:
 329         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 330         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 331         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 332         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 333         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 334         case PIPE_CAP_TGSI_FS_FBFETCH:
 335         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 336         case PIPE_CAP_DOUBLES:
 337         case PIPE_CAP_INT64:
 338         case PIPE_CAP_INT64_DIVMOD:
 339         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 340         case PIPE_CAP_TGSI_CLOCK:
 341         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 342         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 343         case PIPE_CAP_TGSI_BALLOT:
 344         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 345         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 346         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 347         case PIPE_CAP_POST_DEPTH_COVERAGE:
 348         case PIPE_CAP_BINDLESS_TEXTURE:
 349         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 350         case PIPE_CAP_QUERY_SO_OVERFLOW:
 351         case PIPE_CAP_MEMOBJ:
 352         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 353         case PIPE_CAP_TILE_RASTER_ORDER:
 354         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 355         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 356         case PIPE_CAP_FENCE_SIGNAL:
 357         case PIPE_CAP_CONSTBUF0_FLAGS:
 358         case PIPE_CAP_PACKED_UNIFORMS:
 359         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 360         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 361         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 362         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 363         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 364         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 365         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 366                 return 0;
 367
 368         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 369                 return screen->priority_mask;
 370
 371         case PIPE_CAP_DRAW_INDIRECT:
 372                 if (is_a4xx(screen) || is_a5xx(screen))
 373                         return 1;
 374                 return 0;
 375
 376         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 377                 if (is_a4xx(screen) || is_a5xx(screen))
 378                         return 1;
 379                 return 0;
 380
 381         case PIPE_CAP_LOAD_CONSTBUF:
 382                 /* name is confusing, but this turns on std430 packing */
 383                 if (is_ir3(screen))
 384                         return 1;
 385                 return 0;
 386
 387         case PIPE_CAP_MAX_VIEWPORTS:
 388                 return 1;
 389
 390         case PIPE_CAP_SHAREABLE_SHADERS:
 391         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 392         /* manage the variants for these ourself, to avoid breaking precompile: */
 393         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 394         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 395                 if (is_ir3(screen))
 396                         return 1;
 397                 return 0;
 398
 399         /* Stream output. */
 400         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 401                 if (is_ir3(screen))
 402                         return PIPE_MAX_SO_BUFFERS;
 403                 return 0;
 404         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 405         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 406                 if (is_ir3(screen))
 407                         return 1;
 408                 return 0;
 409         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 411                 if (is_ir3(screen))
 412                         return 16 * 4;   /* should only be shader out limit? */
 413                 return 0;
 414
 415         /* Geometry shader output, unsupported. */
 416         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 417         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 418         case PIPE_CAP_MAX_VERTEX_STREAMS:
 419                 return 0;
 420
 421         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 422                 return 2048;
 423
 424         /* Texturing. */
 425         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 426         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 427                 return MAX_MIP_LEVELS;
 428         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 429                 return 11;
 430
 431         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 432                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 433
 434         /* Render targets. */
 435         case PIPE_CAP_MAX_RENDER_TARGETS:
 436                 return screen->max_rts;
 437         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 438                 return is_a3xx(screen) ? 1 : 0;
 439
 440         /* Queries. */
 441         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 442                 return 0;
 443         case PIPE_CAP_OCCLUSION_QUERY:
 444                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 445         case PIPE_CAP_QUERY_TIMESTAMP:
 446         case PIPE_CAP_QUERY_TIME_ELAPSED:
 447                 /* only a4xx, requires new enough kernel so we know max_freq: */
 448                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 449
 450         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 451         case PIPE_CAP_MIN_TEXEL_OFFSET:
 452                 return -8;
 453
 454         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 455         case PIPE_CAP_MAX_TEXEL_OFFSET:
 456                 return 7;
 457
 458         case PIPE_CAP_ENDIANNESS:
 459                 return PIPE_ENDIAN_LITTLE;
 460
 461         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 462                 return 64;
 463
 464         case PIPE_CAP_VENDOR_ID:
 465                 return 0x5143;
 466         case PIPE_CAP_DEVICE_ID:
 467                 return 0xFFFFFFFF;
 468         case PIPE_CAP_ACCELERATED:
 469                 return 1;
 470         case PIPE_CAP_VIDEO_MEMORY:
 471                 DBG("FINISHME: The value returned is incorrect\n");
 472                 return 10;
 473         case PIPE_CAP_UMA:
 474                 return 1;
 475         case PIPE_CAP_NATIVE_FENCE_FD:
 476                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 477         }
 478         debug_printf("unknown param %d\n", param);
 479         return 0;
 480 }
 481
 482 static float
 483 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 484 {
 485         switch (param) {
 486         case PIPE_CAPF_MAX_LINE_WIDTH:
 487         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 488                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 489                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 490                  * uses too small of a render target size, and gets confused when
 491                  * the lines start going offscreen.
 492                  *
 493                  * See: https://code.google.com/p/android/issues/detail?id=206513
 494                  */
 495                 if (fd_mesa_debug & FD_DBG_DEQP)
 496                         return 48.0f;
 497                 return 127.0f;
 498         case PIPE_CAPF_MAX_POINT_WIDTH:
 499         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 500                 return 4092.0f;
 501         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 502                 return 16.0f;
 503         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 504                 return 15.0f;
 505         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 506         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 507         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 508                 return 0.0f;
 509         }
 510         debug_printf("unknown paramf %d\n", param);
 511         return 0;
 512 }
 513
 514 static int
 515 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 516                 enum pipe_shader_type shader,
 517                 enum pipe_shader_cap param)
 518 {
 519         struct fd_screen *screen = fd_screen(pscreen);
 520
 521         switch(shader)
 522         {
 523         case PIPE_SHADER_FRAGMENT:
 524         case PIPE_SHADER_VERTEX:
 525                 break;
 526         case PIPE_SHADER_COMPUTE:
 527                 if (has_compute(screen))
 528                         break;
 529                 return 0;
 530         case PIPE_SHADER_GEOMETRY:
 531                 /* maye we could emulate.. */
 532                 return 0;
 533         default:
 534                 DBG("unknown shader type %d", shader);
 535                 return 0;
 536         }
 537
 538         /* this is probably not totally correct.. but it's a start: */
 539         switch (param) {
 540         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 541         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 542         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 543         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 544                 return 16384;
 545         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 546                 return 8; /* XXX */
 547         case PIPE_SHADER_CAP_MAX_INPUTS:
 548         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 549                 return 16;
 550         case PIPE_SHADER_CAP_MAX_TEMPS:
 551                 return 64; /* Max native temporaries. */
 552         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 553                 /* NOTE: seems to be limit for a3xx is actually 512 but
 554                  * split between VS and FS.  Use lower limit of 256 to
 555                  * avoid getting into impossible situations:
 556                  */
 557                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 558         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 559                 return is_ir3(screen) ? 16 : 1;
 560         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 561                 return 1;
 562         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 563         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 564                 /* Technically this should be the same as for TEMP/CONST, since
 565                  * everything is just normal registers.  This is just temporary
 566                  * hack until load_input/store_output handle arrays in a similar
 567                  * way as load_var/store_var..
 568                  */
 569                 return 0;
 570         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 571         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 572                 /* a2xx compiler doesn't handle indirect: */
 573                 return is_ir3(screen) ? 1 : 0;
 574         case PIPE_SHADER_CAP_SUBROUTINES:
 575         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 576         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 577         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 578         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 579         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 580         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 581                 return 0;
 582         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 583                 return 1;
 584         case PIPE_SHADER_CAP_INTEGERS:
 585                 if (glsl120)
 586                         return 0;
 587                 return is_ir3(screen) ? 1 : 0;
 588         case PIPE_SHADER_CAP_INT64_ATOMICS:
 589                 return 0;
 590         case PIPE_SHADER_CAP_FP16:
 591                 return 0;
 592         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 593         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 594                 return 16;
 595         case PIPE_SHADER_CAP_PREFERRED_IR:
 596                 if (is_ir3(screen))
 597                         return PIPE_SHADER_IR_NIR;
 598                 return PIPE_SHADER_IR_TGSI;
 599         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 600                 if (is_ir3(screen)) {
 601                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 602                 } else {
 603                         return (1 << PIPE_SHADER_IR_TGSI);
 604                 }
 605                 return 0;
 606         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 607                 return 32;
 608         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 609         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 610         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 611         case PIPE_SHADER_CAP_SCALAR_ISA:
 612                 return 1;
 613         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 614         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 615                 if (is_a5xx(screen)) {
 616                         /* a5xx (and a4xx for that matter) has one state-block
 617                          * for compute-shader SSBO's and another that is shared
 618                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 619                          * just advertise SSBOs for FS and CS.  We could possibly
 620                          * do what blob does, and partition the space for
 621                          * VS/HS/DS/GS/FS.  The blob advertises:
 622                          *
 623                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 624                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 625                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 626                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 627                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 628                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 629                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 630                          *
 631                          * I think that way we could avoid having to patch shaders
 632                          * for actual SSBO indexes by using a static partitioning.
 633                          *
 634                          * Note same state block is used for images and buffers,
 635                          * but images also need texture state for read access
 636                          * (isam/isam.3d)
 637                          */
 638                         switch(shader)
 639                         {
 640                         case PIPE_SHADER_FRAGMENT:
 641                         case PIPE_SHADER_COMPUTE:
 642                                 return 24;
 643                         default:
 644                                 return 0;
 645                         }
 646                 }
 647                 return 0;
 648         }
 649         debug_printf("unknown shader param %d\n", param);
 650         return 0;
 651 }
 652
 653 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 654  * into per-generation backend?
 655  */
 656 static int
 657 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 658                 enum pipe_compute_cap param, void *ret)
 659 {
 660         struct fd_screen *screen = fd_screen(pscreen);
 661         const char * const ir = "ir3";
 662
 663         if (!has_compute(screen))
 664                 return 0;
 665
 666 #define RET(x) do {                  \
 667    if (ret)                          \
 668       memcpy(ret, x, sizeof(x));     \
 669    return sizeof(x);                 \
 670 } while (0)
 671
 672         switch (param) {
 673         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 674 // don't expose 64b pointer support yet, until ir3 supports 64b
 675 // math, otherwise spir64 target is used and we get 64b pointer
 676 // calculations that we can't do yet
 677 //              if (is_a5xx(screen))
 678 //                      RET((uint32_t []){ 64 });
 679                 RET((uint32_t []){ 32 });
 680
 681         case PIPE_COMPUTE_CAP_IR_TARGET:
 682                 if (ret)
 683                         sprintf(ret, ir);
 684                 return strlen(ir) * sizeof(char);
 685
 686         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 687                 RET((uint64_t []) { 3 });
 688
 689         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 690                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 691
 692         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 693                 RET(((uint64_t []) { 1024, 1024, 64 }));
 694
 695         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 696                 RET((uint64_t []) { 1024 });
 697
 698         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 699                 RET((uint64_t []) { screen->ram_size });
 700
 701         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 702                 RET((uint64_t []) { 32768 });
 703
 704         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 705         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 706                 RET((uint64_t []) { 4096 });
 707
 708         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 709                 RET((uint64_t []) { screen->ram_size });
 710
 711         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 712                 RET((uint32_t []) { screen->max_freq / 1000000 });
 713
 714         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 715                 RET((uint32_t []) { 9999 });  // TODO
 716
 717         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 718                 RET((uint32_t []) { 1 });
 719
 720         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 721                 RET((uint32_t []) { 32 });  // TODO
 722
 723         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 724                 RET((uint64_t []) { 1024 }); // TODO
 725         }
 726
 727         return 0;
 728 }
 729
 730 static const void *
 731 fd_get_compiler_options(struct pipe_screen *pscreen,
 732                 enum pipe_shader_ir ir, unsigned shader)
 733 {
 734         struct fd_screen *screen = fd_screen(pscreen);
 735
 736         if (is_ir3(screen))
 737                 return ir3_get_compiler_options(screen->compiler);
 738
 739         return NULL;
 740 }
 741
 742 boolean
 743 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 744                 struct fd_bo *bo,
 745                 unsigned stride,
 746                 struct winsys_handle *whandle)
 747 {
 748         whandle->stride = stride;
 749
 750         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 751                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 752         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 753                 whandle->handle = fd_bo_handle(bo);
 754                 return TRUE;
 755         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 756                 whandle->handle = fd_bo_dmabuf(bo);
 757                 return TRUE;
 758         } else {
 759                 return FALSE;
 760         }
 761 }
 762
 763 struct fd_bo *
 764 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 765                 struct winsys_handle *whandle)
 766 {
 767         struct fd_screen *screen = fd_screen(pscreen);
 768         struct fd_bo *bo;
 769
 770         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 771                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 772         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 773                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 774         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 775                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 776         } else {
 777                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 778                 return NULL;
 779         }
 780
 781         if (!bo) {
 782                 DBG("ref name 0x%08x failed", whandle->handle);
 783                 return NULL;
 784         }
 785
 786         return bo;
 787 }
 788
 789 struct pipe_screen *
 790 fd_screen_create(struct fd_device *dev)
 791 {
 792         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 793         struct pipe_screen *pscreen;
 794         uint64_t val;
 795
 796         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 797         fd_shader_debug = debug_get_option_fd_shader_debug();
 798
 799         if (fd_mesa_debug & FD_DBG_NOBIN)
 800                 fd_binning_enabled = false;
 801
 802         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 803
 804         if (!screen)
 805                 return NULL;
 806
 807         pscreen = &screen->base;
 808
 809         screen->dev = dev;
 810         screen->refcnt = 1;
 811
 812         // maybe this should be in context?
 813         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 814         if (!screen->pipe) {
 815                 DBG("could not create 3d pipe");
 816                 goto fail;
 817         }
 818
 819         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 820                 DBG("could not get GMEM size");
 821                 goto fail;
 822         }
 823         screen->gmemsize_bytes = val;
 824
 825         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 826                 DBG("could not get device-id");
 827                 goto fail;
 828         }
 829         screen->device_id = val;
 830
 831         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 832                 DBG("could not get gpu freq");
 833                 /* this limits what performance related queries are
 834                  * supported but is not fatal
 835                  */
 836                 screen->max_freq = 0;
 837         } else {
 838                 screen->max_freq = val;
 839                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 840                         screen->has_timestamp = true;
 841         }
 842
 843         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 844                 DBG("could not get gpu-id");
 845                 goto fail;
 846         }
 847         screen->gpu_id = val;
 848
 849         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 850                 DBG("could not get chip-id");
 851                 /* older kernels may not have this property: */
 852                 unsigned core  = screen->gpu_id / 100;
 853                 unsigned major = (screen->gpu_id % 100) / 10;
 854                 unsigned minor = screen->gpu_id % 10;
 855                 unsigned patch = 0;  /* assume the worst */
 856                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 857                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 858         }
 859         screen->chip_id = val;
 860
 861         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 862                 DBG("could not get # of rings");
 863                 screen->priority_mask = 0;
 864         } else {
 865                 /* # of rings equates to number of unique priority values: */
 866                 screen->priority_mask = (1 << val) - 1;
 867         }
 868
 869         struct sysinfo si;
 870         sysinfo(&si);
 871         screen->ram_size = si.totalram;
 872
 873         DBG("Pipe Info:");
 874         DBG(" GPU-id:          %d", screen->gpu_id);
 875         DBG(" Chip-id:         0x%08x", screen->chip_id);
 876         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 877
 878         /* explicitly checking for GPU revisions that are known to work.  This
 879          * may be overly conservative for a3xx, where spoofing the gpu_id with
 880          * the blob driver seems to generate identical cmdstream dumps.  But
 881          * on a2xx, there seem to be small differences between the GPU revs
 882          * so it is probably better to actually test first on real hardware
 883          * before enabling:
 884          *
 885          * If you have a different adreno version, feel free to add it to one
 886          * of the cases below and see what happens.  And if it works, please
 887          * send a patch ;-)
 888          */
 889         switch (screen->gpu_id) {
 890         case 205:
 891         case 220:
 892                 fd2_screen_init(pscreen);
 893                 break;
 894         case 305:
 895         case 307:
 896         case 320:
 897         case 330:
 898                 fd3_screen_init(pscreen);
 899                 break;
 900         case 420:
 901         case 430:
 902                 fd4_screen_init(pscreen);
 903                 break;
 904         case 530:
 905                 fd5_screen_init(pscreen);
 906                 break;
 907         default:
 908                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 909                 goto fail;
 910         }
 911
 912         if (screen->gpu_id >= 500) {
 913                 screen->gmem_alignw = 64;
 914                 screen->gmem_alignh = 32;
 915                 screen->num_vsc_pipes = 16;
 916         } else {
 917                 screen->gmem_alignw = 32;
 918                 screen->gmem_alignh = 32;
 919                 screen->num_vsc_pipes = 8;
 920         }
 921
 922         /* NOTE: don't enable reordering on a2xx, since completely untested.
 923          * Also, don't enable if we have too old of a kernel to support
 924          * growable cmdstream buffers, since memory requirement for cmdstream
 925          * buffers would be too much otherwise.
 926          */
 927         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 928                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 929
 930         fd_bc_init(&screen->batch_cache);
 931
 932         (void) mtx_init(&screen->lock, mtx_plain);
 933
 934         pscreen->destroy = fd_screen_destroy;
 935         pscreen->get_param = fd_screen_get_param;
 936         pscreen->get_paramf = fd_screen_get_paramf;
 937         pscreen->get_shader_param = fd_screen_get_shader_param;
 938         pscreen->get_compute_param = fd_get_compute_param;
 939         pscreen->get_compiler_options = fd_get_compiler_options;
 940
 941         fd_resource_screen_init(pscreen);
 942         fd_query_screen_init(pscreen);
 943
 944         pscreen->get_name = fd_screen_get_name;
 945         pscreen->get_vendor = fd_screen_get_vendor;
 946         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 947
 948         pscreen->get_timestamp = fd_screen_get_timestamp;
 949
 950         pscreen->fence_reference = fd_fence_ref;
 951         pscreen->fence_finish = fd_fence_finish;
 952         pscreen->fence_get_fd = fd_fence_get_fd;
 953
 954         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 955
 956         return pscreen;
 957
 958 fail:
 959         fd_screen_destroy(pscreen);
 960         return NULL;
 961 }