src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  81                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  82                 DEBUG_NAMED_VALUE_END
  83 };
  84
  85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  86
  87 int fd_mesa_debug = 0;
  88 bool fd_binning_enabled = true;
  89 static bool glsl120 = false;
  90
  91 static const char *
  92 fd_screen_get_name(struct pipe_screen *pscreen)
  93 {
  94         static char buffer[128];
  95         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  96                         fd_screen(pscreen)->device_id);
  97         return buffer;
  98 }
  99
 100 static const char *
 101 fd_screen_get_vendor(struct pipe_screen *pscreen)
 102 {
 103         return "freedreno";
 104 }
 105
 106 static const char *
 107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 108 {
 109         return "Qualcomm";
 110 }
 111
 112
 113 static uint64_t
 114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 115 {
 116         struct fd_screen *screen = fd_screen(pscreen);
 117
 118         if (screen->has_timestamp) {
 119                 uint64_t n;
 120                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 121                 debug_assert(screen->max_freq > 0);
 122                 return n * 1000000000 / screen->max_freq;
 123         } else {
 124                 int64_t cpu_time = os_time_get() * 1000;
 125                 return cpu_time + screen->cpu_gpu_time_delta;
 126         }
 127
 128 }
 129
 130 static void
 131 fd_screen_destroy(struct pipe_screen *pscreen)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         if (screen->pipe)
 136                 fd_pipe_del(screen->pipe);
 137
 138         if (screen->dev)
 139                 fd_device_del(screen->dev);
 140
 141         fd_bc_fini(&screen->batch_cache);
 142
 143         slab_destroy_parent(&screen->transfer_pool);
 144
 145         mtx_destroy(&screen->lock);
 146
 147         ralloc_free(screen->compiler);
 148
 149         free(screen);
 150 }
 151
 152 /*
 153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 154 tables for things that differ if the delta is not too much..
 155  */
 156 static int
 157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 158 {
 159         struct fd_screen *screen = fd_screen(pscreen);
 160
 161         /* this is probably not totally correct.. but it's a start: */
 162         switch (param) {
 163         /* Supported features (boolean caps). */
 164         case PIPE_CAP_NPOT_TEXTURES:
 165         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 166         case PIPE_CAP_TWO_SIDED_STENCIL:
 167         case PIPE_CAP_ANISOTROPIC_FILTER:
 168         case PIPE_CAP_POINT_SPRITE:
 169         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 170         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 171         case PIPE_CAP_TEXTURE_SWIZZLE:
 172         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 174         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 175         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 176         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 177         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 178         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 179         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 180         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 182         case PIPE_CAP_STRING_MARKER:
 183         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 184         case PIPE_CAP_TEXTURE_BARRIER:
 185         case PIPE_CAP_INVALIDATE_BUFFER:
 186                 return 1;
 187
 188         case PIPE_CAP_VERTEXID_NOBASE:
 189                 return is_a3xx(screen) || is_a4xx(screen);
 190
 191         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 192                 return is_a4xx(screen) ? 0 : 1;
 193
 194         case PIPE_CAP_COMPUTE:
 195                 return has_compute(screen);
 196
 197         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 198         case PIPE_CAP_TGSI_TEXCOORD:
 199         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 200         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 201         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 202         case PIPE_CAP_QUERY_MEMORY_INFO:
 203         case PIPE_CAP_PCI_GROUP:
 204         case PIPE_CAP_PCI_BUS:
 205         case PIPE_CAP_PCI_DEVICE:
 206         case PIPE_CAP_PCI_FUNCTION:
 207                 return 0;
 208
 209         case PIPE_CAP_SM3:
 210         case PIPE_CAP_PRIMITIVE_RESTART:
 211         case PIPE_CAP_TGSI_INSTANCEID:
 212         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 213         case PIPE_CAP_INDEP_BLEND_ENABLE:
 214         case PIPE_CAP_INDEP_BLEND_FUNC:
 215         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 216         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 217         case PIPE_CAP_CONDITIONAL_RENDER:
 218         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 219         case PIPE_CAP_FAKE_SW_MSAA:
 220         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 221         case PIPE_CAP_CLIP_HALFZ:
 222                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 223
 224         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 225                 return is_a3xx(screen) || is_a4xx(screen);
 226
 227         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 228                 return is_a5xx(screen);
 229
 230         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 231                 return 0;
 232         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 233                 if (is_a3xx(screen)) return 16;
 234                 if (is_a4xx(screen)) return 32;
 235                 if (is_a5xx(screen)) return 32;
 236                 return 0;
 237         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 238                 /* We could possibly emulate more by pretending 2d/rect textures and
 239                  * splitting high bits of index into 2nd dimension..
 240                  */
 241                 if (is_a3xx(screen)) return 8192;
 242                 if (is_a4xx(screen)) return 16384;
 243                 if (is_a5xx(screen)) return 16384;
 244                 return 0;
 245
 246         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 247         case PIPE_CAP_CUBE_MAP_ARRAY:
 248         case PIPE_CAP_START_INSTANCE:
 249         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 250         case PIPE_CAP_TEXTURE_QUERY_LOD:
 251                 return is_a4xx(screen) || is_a5xx(screen);
 252
 253         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 254                 return 64;
 255
 256         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 257                 if (glsl120)
 258                         return 120;
 259                 return is_ir3(screen) ? 140 : 120;
 260
 261         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 262                 if (is_a5xx(screen))
 263                         return 4;
 264                 return 0;
 265
 266         /* Unsupported features. */
 267         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 268         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 269         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 270         case PIPE_CAP_USER_VERTEX_BUFFERS:
 271         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 272         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 273         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 274         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 275         case PIPE_CAP_TEXTURE_GATHER_SM5:
 276         case PIPE_CAP_SAMPLE_SHADING:
 277         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 278         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 279         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 280         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 281         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 282         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 283         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 284         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 285         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 286         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 287         case PIPE_CAP_TGSI_TXQS:
 288         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 289         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 290         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 291         case PIPE_CAP_CLEAR_TEXTURE:
 292         case PIPE_CAP_DRAW_PARAMETERS:
 293         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 294         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 295         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 296         case PIPE_CAP_GENERATE_MIPMAP:
 297         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 298         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 299         case PIPE_CAP_CULL_DISTANCE:
 300         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 301         case PIPE_CAP_TGSI_VOTE:
 302         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 303         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 304         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 305         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 306         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 307         case PIPE_CAP_TGSI_FS_FBFETCH:
 308         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 309         case PIPE_CAP_DOUBLES:
 310         case PIPE_CAP_INT64:
 311         case PIPE_CAP_INT64_DIVMOD:
 312         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 313         case PIPE_CAP_TGSI_CLOCK:
 314         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 315         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 316         case PIPE_CAP_TGSI_BALLOT:
 317         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 318         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 319         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 320         case PIPE_CAP_POST_DEPTH_COVERAGE:
 321         case PIPE_CAP_BINDLESS_TEXTURE:
 322         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 323         case PIPE_CAP_QUERY_SO_OVERFLOW:
 324         case PIPE_CAP_MEMOBJ:
 325         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 326         case PIPE_CAP_TILE_RASTER_ORDER:
 327         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 328         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 329                 return 0;
 330
 331         case PIPE_CAP_DRAW_INDIRECT:
 332         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 333                 if (is_a5xx(screen))
 334                         return 1;
 335                 return 0;
 336
 337         case PIPE_CAP_LOAD_CONSTBUF:
 338                 /* name is confusing, but this turns on std430 packing */
 339                 if (is_ir3(screen))
 340                         return 1;
 341                 return 0;
 342
 343         case PIPE_CAP_MAX_VIEWPORTS:
 344                 return 1;
 345
 346         case PIPE_CAP_SHAREABLE_SHADERS:
 347         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 348         /* manage the variants for these ourself, to avoid breaking precompile: */
 349         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 350         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 351                 if (is_ir3(screen))
 352                         return 1;
 353                 return 0;
 354
 355         /* Stream output. */
 356         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 357                 if (is_ir3(screen))
 358                         return PIPE_MAX_SO_BUFFERS;
 359                 return 0;
 360         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 361         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 362                 if (is_ir3(screen))
 363                         return 1;
 364                 return 0;
 365         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 366         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 367                 if (is_ir3(screen))
 368                         return 16 * 4;   /* should only be shader out limit? */
 369                 return 0;
 370
 371         /* Geometry shader output, unsupported. */
 372         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 373         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 374         case PIPE_CAP_MAX_VERTEX_STREAMS:
 375                 return 0;
 376
 377         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 378                 return 2048;
 379
 380         /* Texturing. */
 381         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 382         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 383                 return MAX_MIP_LEVELS;
 384         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 385                 return 11;
 386
 387         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 388                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 389
 390         /* Render targets. */
 391         case PIPE_CAP_MAX_RENDER_TARGETS:
 392                 return screen->max_rts;
 393         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 394                 return is_a3xx(screen) ? 1 : 0;
 395
 396         /* Queries. */
 397         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 398                 return 0;
 399         case PIPE_CAP_OCCLUSION_QUERY:
 400                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 401         case PIPE_CAP_QUERY_TIMESTAMP:
 402         case PIPE_CAP_QUERY_TIME_ELAPSED:
 403                 /* only a4xx, requires new enough kernel so we know max_freq: */
 404                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 405
 406         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 407         case PIPE_CAP_MIN_TEXEL_OFFSET:
 408                 return -8;
 409
 410         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 411         case PIPE_CAP_MAX_TEXEL_OFFSET:
 412                 return 7;
 413
 414         case PIPE_CAP_ENDIANNESS:
 415                 return PIPE_ENDIAN_LITTLE;
 416
 417         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 418                 return 64;
 419
 420         case PIPE_CAP_VENDOR_ID:
 421                 return 0x5143;
 422         case PIPE_CAP_DEVICE_ID:
 423                 return 0xFFFFFFFF;
 424         case PIPE_CAP_ACCELERATED:
 425                 return 1;
 426         case PIPE_CAP_VIDEO_MEMORY:
 427                 DBG("FINISHME: The value returned is incorrect\n");
 428                 return 10;
 429         case PIPE_CAP_UMA:
 430                 return 1;
 431         case PIPE_CAP_NATIVE_FENCE_FD:
 432                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 433         }
 434         debug_printf("unknown param %d\n", param);
 435         return 0;
 436 }
 437
 438 static float
 439 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 440 {
 441         switch (param) {
 442         case PIPE_CAPF_MAX_LINE_WIDTH:
 443         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 444                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 445                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 446                  * uses too small of a render target size, and gets confused when
 447                  * the lines start going offscreen.
 448                  *
 449                  * See: https://code.google.com/p/android/issues/detail?id=206513
 450                  */
 451                 if (fd_mesa_debug & FD_DBG_DEQP)
 452                         return 48.0f;
 453                 return 127.0f;
 454         case PIPE_CAPF_MAX_POINT_WIDTH:
 455         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 456                 return 4092.0f;
 457         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 458                 return 16.0f;
 459         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 460                 return 15.0f;
 461         case PIPE_CAPF_GUARD_BAND_LEFT:
 462         case PIPE_CAPF_GUARD_BAND_TOP:
 463         case PIPE_CAPF_GUARD_BAND_RIGHT:
 464         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 465                 return 0.0f;
 466         }
 467         debug_printf("unknown paramf %d\n", param);
 468         return 0;
 469 }
 470
 471 static int
 472 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 473                 enum pipe_shader_type shader,
 474                 enum pipe_shader_cap param)
 475 {
 476         struct fd_screen *screen = fd_screen(pscreen);
 477
 478         switch(shader)
 479         {
 480         case PIPE_SHADER_FRAGMENT:
 481         case PIPE_SHADER_VERTEX:
 482                 break;
 483         case PIPE_SHADER_COMPUTE:
 484                 if (has_compute(screen))
 485                         break;
 486                 return 0;
 487         case PIPE_SHADER_GEOMETRY:
 488                 /* maye we could emulate.. */
 489                 return 0;
 490         default:
 491                 DBG("unknown shader type %d", shader);
 492                 return 0;
 493         }
 494
 495         /* this is probably not totally correct.. but it's a start: */
 496         switch (param) {
 497         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 498         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 499         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 500         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 501                 return 16384;
 502         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 503                 return 8; /* XXX */
 504         case PIPE_SHADER_CAP_MAX_INPUTS:
 505         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 506                 return 16;
 507         case PIPE_SHADER_CAP_MAX_TEMPS:
 508                 return 64; /* Max native temporaries. */
 509         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 510                 /* NOTE: seems to be limit for a3xx is actually 512 but
 511                  * split between VS and FS.  Use lower limit of 256 to
 512                  * avoid getting into impossible situations:
 513                  */
 514                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 515         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 516                 return is_ir3(screen) ? 16 : 1;
 517         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 518                 return 1;
 519         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 520         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 521                 /* Technically this should be the same as for TEMP/CONST, since
 522                  * everything is just normal registers.  This is just temporary
 523                  * hack until load_input/store_output handle arrays in a similar
 524                  * way as load_var/store_var..
 525                  */
 526                 return 0;
 527         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 528         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 529                 /* a2xx compiler doesn't handle indirect: */
 530                 return is_ir3(screen) ? 1 : 0;
 531         case PIPE_SHADER_CAP_SUBROUTINES:
 532         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 533         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 534         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 535         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 536         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 537                 return 0;
 538         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 539                 return 1;
 540         case PIPE_SHADER_CAP_INTEGERS:
 541                 if (glsl120)
 542                         return 0;
 543                 return is_ir3(screen) ? 1 : 0;
 544         case PIPE_SHADER_CAP_INT64_ATOMICS:
 545                 return 0;
 546         case PIPE_SHADER_CAP_FP16:
 547                 return 0;
 548         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 549         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 550                 return 16;
 551         case PIPE_SHADER_CAP_PREFERRED_IR:
 552                 if (is_ir3(screen))
 553                         return PIPE_SHADER_IR_NIR;
 554                 return PIPE_SHADER_IR_TGSI;
 555         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 556                 if (is_ir3(screen)) {
 557                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 558                 } else {
 559                         return (1 << PIPE_SHADER_IR_TGSI);
 560                 }
 561                 return 0;
 562         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 563                 return 32;
 564         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 565         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 566         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 567         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 568                 return 0;
 569         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 570         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 571                 if (is_a5xx(screen)) {
 572                         /* a5xx (and a4xx for that matter) has one state-block
 573                          * for compute-shader SSBO's and another that is shared
 574                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 575                          * just advertise SSBOs for FS and CS.  We could possibly
 576                          * do what blob does, and partition the space for
 577                          * VS/HS/DS/GS/FS.  The blob advertises:
 578                          *
 579                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 580                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 581                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 582                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 583                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 584                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 585                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 586                          *
 587                          * I think that way we could avoid having to patch shaders
 588                          * for actual SSBO indexes by using a static partitioning.
 589                          *
 590                          * Note same state block is used for images and buffers,
 591                          * but images also need texture state for read access
 592                          * (isam/isam.3d)
 593                          */
 594                         switch(shader)
 595                         {
 596                         case PIPE_SHADER_FRAGMENT:
 597                         case PIPE_SHADER_COMPUTE:
 598                                 return 24;
 599                         default:
 600                                 return 0;
 601                         }
 602                 }
 603                 return 0;
 604         }
 605         debug_printf("unknown shader param %d\n", param);
 606         return 0;
 607 }
 608
 609 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 610  * into per-generation backend?
 611  */
 612 static int
 613 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 614                 enum pipe_compute_cap param, void *ret)
 615 {
 616         struct fd_screen *screen = fd_screen(pscreen);
 617         const char * const ir = "ir3";
 618
 619         if (!has_compute(screen))
 620                 return 0;
 621
 622         switch (param) {
 623         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 624                 if (ret) {
 625                         uint32_t *address_bits = ret;
 626                         address_bits[0] = 32;
 627
 628                         if (is_a5xx(screen))
 629                                 address_bits[0] = 64;
 630                 }
 631                 return 1 * sizeof(uint32_t);
 632
 633         case PIPE_COMPUTE_CAP_IR_TARGET:
 634                 if (ret)
 635                         sprintf(ret, ir);
 636                 return strlen(ir) * sizeof(char);
 637
 638         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 639                 if (ret) {
 640                         uint64_t *grid_dimension = ret;
 641                         grid_dimension[0] = 3;
 642                 }
 643                 return 1 * sizeof(uint64_t);
 644
 645         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 646                 if (ret) {
 647                         uint64_t *grid_size = ret;
 648                         grid_size[0] = 65535;
 649                         grid_size[1] = 65535;
 650                         grid_size[2] = 65535;
 651                 }
 652                 return 3 * sizeof(uint64_t) ;
 653
 654         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 655                 if (ret) {
 656                         uint64_t *block_size = ret;
 657                         block_size[0] = 1024;
 658                         block_size[1] = 1024;
 659                         block_size[2] = 64;
 660                 }
 661                 return 3 * sizeof(uint64_t) ;
 662
 663         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 664                 if (ret) {
 665                         uint64_t *max_threads_per_block = ret;
 666                         *max_threads_per_block = 1024;
 667                 }
 668                 return sizeof(uint64_t);
 669
 670         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 671         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 672                 if (ret) {
 673                         uint64_t *local_size = ret;
 674                         *local_size = 32768;
 675                 }
 676                 return sizeof(uint64_t);
 677         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 678         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 679                 break;
 680         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 681                 if (ret) {
 682                         uint64_t *max = ret;
 683                         *max = 32768;
 684                 }
 685                 return sizeof(uint64_t);
 686         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 687         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 688         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 689         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 690         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 691                 break;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static const void *
 698 fd_get_compiler_options(struct pipe_screen *pscreen,
 699                 enum pipe_shader_ir ir, unsigned shader)
 700 {
 701         struct fd_screen *screen = fd_screen(pscreen);
 702
 703         if (is_ir3(screen))
 704                 return ir3_get_compiler_options(screen->compiler);
 705
 706         return NULL;
 707 }
 708
 709 boolean
 710 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 711                 struct fd_bo *bo,
 712                 unsigned stride,
 713                 struct winsys_handle *whandle)
 714 {
 715         whandle->stride = stride;
 716
 717         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 718                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 719         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 720                 whandle->handle = fd_bo_handle(bo);
 721                 return TRUE;
 722         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 723                 whandle->handle = fd_bo_dmabuf(bo);
 724                 return TRUE;
 725         } else {
 726                 return FALSE;
 727         }
 728 }
 729
 730 struct fd_bo *
 731 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 732                 struct winsys_handle *whandle)
 733 {
 734         struct fd_screen *screen = fd_screen(pscreen);
 735         struct fd_bo *bo;
 736
 737         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 738                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 739         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 740                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 741         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 742                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 743         } else {
 744                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 745                 return NULL;
 746         }
 747
 748         if (!bo) {
 749                 DBG("ref name 0x%08x failed", whandle->handle);
 750                 return NULL;
 751         }
 752
 753         return bo;
 754 }
 755
 756 struct pipe_screen *
 757 fd_screen_create(struct fd_device *dev)
 758 {
 759         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 760         struct pipe_screen *pscreen;
 761         uint64_t val;
 762
 763         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 764
 765         if (fd_mesa_debug & FD_DBG_NOBIN)
 766                 fd_binning_enabled = false;
 767
 768         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 769
 770         if (!screen)
 771                 return NULL;
 772
 773         pscreen = &screen->base;
 774
 775         screen->dev = dev;
 776         screen->refcnt = 1;
 777
 778         // maybe this should be in context?
 779         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 780         if (!screen->pipe) {
 781                 DBG("could not create 3d pipe");
 782                 goto fail;
 783         }
 784
 785         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 786                 DBG("could not get GMEM size");
 787                 goto fail;
 788         }
 789         screen->gmemsize_bytes = val;
 790
 791         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 792                 DBG("could not get device-id");
 793                 goto fail;
 794         }
 795         screen->device_id = val;
 796
 797         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 798                 DBG("could not get gpu freq");
 799                 /* this limits what performance related queries are
 800                  * supported but is not fatal
 801                  */
 802                 screen->max_freq = 0;
 803         } else {
 804                 screen->max_freq = val;
 805                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 806                         screen->has_timestamp = true;
 807         }
 808
 809         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 810                 DBG("could not get gpu-id");
 811                 goto fail;
 812         }
 813         screen->gpu_id = val;
 814
 815         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 816                 DBG("could not get chip-id");
 817                 /* older kernels may not have this property: */
 818                 unsigned core  = screen->gpu_id / 100;
 819                 unsigned major = (screen->gpu_id % 100) / 10;
 820                 unsigned minor = screen->gpu_id % 10;
 821                 unsigned patch = 0;  /* assume the worst */
 822                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 823                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 824         }
 825         screen->chip_id = val;
 826
 827         DBG("Pipe Info:");
 828         DBG(" GPU-id:          %d", screen->gpu_id);
 829         DBG(" Chip-id:         0x%08x", screen->chip_id);
 830         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 831
 832         /* explicitly checking for GPU revisions that are known to work.  This
 833          * may be overly conservative for a3xx, where spoofing the gpu_id with
 834          * the blob driver seems to generate identical cmdstream dumps.  But
 835          * on a2xx, there seem to be small differences between the GPU revs
 836          * so it is probably better to actually test first on real hardware
 837          * before enabling:
 838          *
 839          * If you have a different adreno version, feel free to add it to one
 840          * of the cases below and see what happens.  And if it works, please
 841          * send a patch ;-)
 842          */
 843         switch (screen->gpu_id) {
 844         case 220:
 845                 fd2_screen_init(pscreen);
 846                 break;
 847         case 305:
 848         case 307:
 849         case 320:
 850         case 330:
 851                 fd3_screen_init(pscreen);
 852                 break;
 853         case 420:
 854         case 430:
 855                 fd4_screen_init(pscreen);
 856                 break;
 857         case 530:
 858                 fd5_screen_init(pscreen);
 859                 break;
 860         default:
 861                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 862                 goto fail;
 863         }
 864
 865         if (screen->gpu_id >= 500) {
 866                 screen->gmem_alignw = 64;
 867                 screen->gmem_alignh = 32;
 868                 screen->num_vsc_pipes = 16;
 869         } else {
 870                 screen->gmem_alignw = 32;
 871                 screen->gmem_alignh = 32;
 872                 screen->num_vsc_pipes = 8;
 873         }
 874
 875         /* NOTE: don't enable reordering on a2xx, since completely untested.
 876          * Also, don't enable if we have too old of a kernel to support
 877          * growable cmdstream buffers, since memory requirement for cmdstream
 878          * buffers would be too much otherwise.
 879          */
 880         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 881                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 882
 883         fd_bc_init(&screen->batch_cache);
 884
 885         (void) mtx_init(&screen->lock, mtx_plain);
 886
 887         pscreen->destroy = fd_screen_destroy;
 888         pscreen->get_param = fd_screen_get_param;
 889         pscreen->get_paramf = fd_screen_get_paramf;
 890         pscreen->get_shader_param = fd_screen_get_shader_param;
 891         pscreen->get_compute_param = fd_get_compute_param;
 892         pscreen->get_compiler_options = fd_get_compiler_options;
 893
 894         fd_resource_screen_init(pscreen);
 895         fd_query_screen_init(pscreen);
 896
 897         pscreen->get_name = fd_screen_get_name;
 898         pscreen->get_vendor = fd_screen_get_vendor;
 899         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 900
 901         pscreen->get_timestamp = fd_screen_get_timestamp;
 902
 903         pscreen->fence_reference = fd_fence_ref;
 904         pscreen->fence_finish = fd_fence_finish;
 905         pscreen->fence_get_fd = fd_fence_get_fd;
 906
 907         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 908
 909         return pscreen;
 910
 911 fail:
 912         fd_screen_destroy(pscreen);
 913         return NULL;
 914 }