src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 /* XXX this should go away */
  58 #include "state_tracker/drm_driver.h"
  59
  60 static const struct debug_named_value debug_options[] = {
  61                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  62                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  63                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  64                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  65                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  66                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  67                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  68                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  69                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  71                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  72                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  73                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  74                 DEBUG_NAMED_VALUE_END
  75 };
  76
  77 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  78
  79 int fd_mesa_debug = 0;
  80 bool fd_binning_enabled = true;
  81 static bool glsl120 = false;
  82
  83 static const char *
  84 fd_screen_get_name(struct pipe_screen *pscreen)
  85 {
  86         static char buffer[128];
  87         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  88                         fd_screen(pscreen)->device_id);
  89         return buffer;
  90 }
  91
  92 static const char *
  93 fd_screen_get_vendor(struct pipe_screen *pscreen)
  94 {
  95         return "freedreno";
  96 }
  97
  98 static const char *
  99 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 100 {
 101         return "Qualcomm";
 102 }
 103
 104
 105 static uint64_t
 106 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 107 {
 108         int64_t cpu_time = os_time_get() * 1000;
 109         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 110 }
 111
 112 static void
 113 fd_screen_destroy(struct pipe_screen *pscreen)
 114 {
 115         struct fd_screen *screen = fd_screen(pscreen);
 116
 117         if (screen->pipe)
 118                 fd_pipe_del(screen->pipe);
 119
 120         if (screen->dev)
 121                 fd_device_del(screen->dev);
 122
 123         free(screen);
 124 }
 125
 126 /*
 127 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 128 tables for things that differ if the delta is not too much..
 129  */
 130 static int
 131 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         /* this is probably not totally correct.. but it's a start: */
 136         switch (param) {
 137         /* Supported features (boolean caps). */
 138         case PIPE_CAP_NPOT_TEXTURES:
 139         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 140         case PIPE_CAP_TWO_SIDED_STENCIL:
 141         case PIPE_CAP_ANISOTROPIC_FILTER:
 142         case PIPE_CAP_POINT_SPRITE:
 143         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 144         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 145         case PIPE_CAP_TEXTURE_SWIZZLE:
 146         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 148         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 149         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 150         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 151         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 152         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 153         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 154         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 155         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 156         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 157         case PIPE_CAP_VERTEXID_NOBASE:
 158         case PIPE_CAP_STRING_MARKER:
 159                 return 1;
 160
 161         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 162         case PIPE_CAP_TGSI_TEXCOORD:
 163         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 164         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 165         case PIPE_CAP_TEXTURE_BARRIER:
 166         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 167         case PIPE_CAP_COMPUTE:
 168         case PIPE_CAP_QUERY_MEMORY_INFO:
 169                 return 0;
 170
 171         case PIPE_CAP_SM3:
 172         case PIPE_CAP_PRIMITIVE_RESTART:
 173         case PIPE_CAP_TGSI_INSTANCEID:
 174         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 175         case PIPE_CAP_INDEP_BLEND_ENABLE:
 176         case PIPE_CAP_INDEP_BLEND_FUNC:
 177         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 178         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 179         case PIPE_CAP_CONDITIONAL_RENDER:
 180         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 181         case PIPE_CAP_FAKE_SW_MSAA:
 182         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 183         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 184         case PIPE_CAP_CLIP_HALFZ:
 185                 return is_a3xx(screen) || is_a4xx(screen);
 186
 187         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 188                 return 0;
 189         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190                 if (is_a3xx(screen)) return 16;
 191                 if (is_a4xx(screen)) return 32;
 192                 return 0;
 193         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 194                 /* We could possibly emulate more by pretending 2d/rect textures and
 195                  * splitting high bits of index into 2nd dimension..
 196                  */
 197                 if (is_a3xx(screen)) return 8192;
 198                 if (is_a4xx(screen)) return 16384;
 199                 return 0;
 200
 201         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 202         case PIPE_CAP_CUBE_MAP_ARRAY:
 203         case PIPE_CAP_START_INSTANCE:
 204         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 205         case PIPE_CAP_TEXTURE_QUERY_LOD:
 206                 return is_a4xx(screen);
 207
 208         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 209                 return 256;
 210
 211         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 212                 if (glsl120)
 213                         return 120;
 214                 return is_ir3(screen) ? 140 : 120;
 215
 216         /* Unsupported features. */
 217         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 219         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 220         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 221         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 222         case PIPE_CAP_USER_VERTEX_BUFFERS:
 223         case PIPE_CAP_USER_INDEX_BUFFERS:
 224         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 225         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 226         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 227         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 228         case PIPE_CAP_TEXTURE_GATHER_SM5:
 229         case PIPE_CAP_SAMPLE_SHADING:
 230         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 231         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 232         case PIPE_CAP_DRAW_INDIRECT:
 233         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 236         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 237         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 238         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 239         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 240         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 241         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 242         case PIPE_CAP_TGSI_TXQS:
 243         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 244         case PIPE_CAP_SHAREABLE_SHADERS:
 245         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 246         case PIPE_CAP_CLEAR_TEXTURE:
 247         case PIPE_CAP_DRAW_PARAMETERS:
 248         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 249         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 250         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 251         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 252         case PIPE_CAP_INVALIDATE_BUFFER:
 253         case PIPE_CAP_GENERATE_MIPMAP:
 254         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 255                 return 0;
 256
 257         case PIPE_CAP_MAX_VIEWPORTS:
 258                 return 1;
 259
 260         /* Stream output. */
 261         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 262                 if (is_ir3(screen))
 263                         return PIPE_MAX_SO_BUFFERS;
 264                 return 0;
 265         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 266                 if (is_ir3(screen))
 267                         return 1;
 268                 return 0;
 269         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 270         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 271                 if (is_ir3(screen))
 272                         return 16 * 4;   /* should only be shader out limit? */
 273                 return 0;
 274
 275         /* Geometry shader output, unsupported. */
 276         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 277         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 278         case PIPE_CAP_MAX_VERTEX_STREAMS:
 279                 return 0;
 280
 281         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 282                 return 2048;
 283
 284         /* Texturing. */
 285         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 286         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 287                 return MAX_MIP_LEVELS;
 288         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 289                 return 11;
 290
 291         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 292                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 293
 294         /* Render targets. */
 295         case PIPE_CAP_MAX_RENDER_TARGETS:
 296                 return screen->max_rts;
 297         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 298                 return is_a3xx(screen) ? 1 : 0;
 299
 300         /* Queries. */
 301         case PIPE_CAP_QUERY_TIMESTAMP:
 302         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 303                 return 0;
 304         case PIPE_CAP_OCCLUSION_QUERY:
 305                 return is_a3xx(screen) || is_a4xx(screen);
 306         case PIPE_CAP_QUERY_TIME_ELAPSED:
 307                 /* only a4xx, requires new enough kernel so we know max_freq: */
 308                 return (screen->max_freq > 0) && is_a4xx(screen);
 309
 310         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 311         case PIPE_CAP_MIN_TEXEL_OFFSET:
 312                 return -8;
 313
 314         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 315         case PIPE_CAP_MAX_TEXEL_OFFSET:
 316                 return 7;
 317
 318         case PIPE_CAP_ENDIANNESS:
 319                 return PIPE_ENDIAN_LITTLE;
 320
 321         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 322                 return 64;
 323
 324         case PIPE_CAP_VENDOR_ID:
 325                 return 0x5143;
 326         case PIPE_CAP_DEVICE_ID:
 327                 return 0xFFFFFFFF;
 328         case PIPE_CAP_ACCELERATED:
 329                 return 1;
 330         case PIPE_CAP_VIDEO_MEMORY:
 331                 DBG("FINISHME: The value returned is incorrect\n");
 332                 return 10;
 333         case PIPE_CAP_UMA:
 334                 return 1;
 335         }
 336         debug_printf("unknown param %d\n", param);
 337         return 0;
 338 }
 339
 340 static float
 341 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 342 {
 343         switch (param) {
 344         case PIPE_CAPF_MAX_LINE_WIDTH:
 345         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 346         case PIPE_CAPF_MAX_POINT_WIDTH:
 347         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 348                 return 4092.0f;
 349         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 350                 return 16.0f;
 351         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 352                 return 15.0f;
 353         case PIPE_CAPF_GUARD_BAND_LEFT:
 354         case PIPE_CAPF_GUARD_BAND_TOP:
 355         case PIPE_CAPF_GUARD_BAND_RIGHT:
 356         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 357                 return 0.0f;
 358         }
 359         debug_printf("unknown paramf %d\n", param);
 360         return 0;
 361 }
 362
 363 static int
 364 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 365                 enum pipe_shader_cap param)
 366 {
 367         struct fd_screen *screen = fd_screen(pscreen);
 368
 369         switch(shader)
 370         {
 371         case PIPE_SHADER_FRAGMENT:
 372         case PIPE_SHADER_VERTEX:
 373                 break;
 374         case PIPE_SHADER_COMPUTE:
 375         case PIPE_SHADER_GEOMETRY:
 376                 /* maye we could emulate.. */
 377                 return 0;
 378         default:
 379                 DBG("unknown shader type %d", shader);
 380                 return 0;
 381         }
 382
 383         /* this is probably not totally correct.. but it's a start: */
 384         switch (param) {
 385         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 386         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 387         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 388         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 389                 return 16384;
 390         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 391                 return 8; /* XXX */
 392         case PIPE_SHADER_CAP_MAX_INPUTS:
 393         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 394                 return 16;
 395         case PIPE_SHADER_CAP_MAX_TEMPS:
 396                 return 64; /* Max native temporaries. */
 397         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 398                 /* NOTE: seems to be limit for a3xx is actually 512 but
 399                  * split between VS and FS.  Use lower limit of 256 to
 400                  * avoid getting into impossible situations:
 401                  */
 402                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 403         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 404                 return is_ir3(screen) ? 16 : 1;
 405         case PIPE_SHADER_CAP_MAX_PREDS:
 406                 return 0; /* nothing uses this */
 407         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 408                 return 1;
 409         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 410         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 411                 /* Technically this should be the same as for TEMP/CONST, since
 412                  * everything is just normal registers.  This is just temporary
 413                  * hack until load_input/store_output handle arrays in a similar
 414                  * way as load_var/store_var..
 415                  */
 416                 return 0;
 417         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 418         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 419                 /* a2xx compiler doesn't handle indirect: */
 420                 return is_ir3(screen) ? 1 : 0;
 421         case PIPE_SHADER_CAP_SUBROUTINES:
 422         case PIPE_SHADER_CAP_DOUBLES:
 423         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 424         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 425         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 426         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 427                 return 0;
 428         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 429                 return 1;
 430         case PIPE_SHADER_CAP_INTEGERS:
 431                 if (glsl120)
 432                         return 0;
 433                 return is_ir3(screen) ? 1 : 0;
 434         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 435         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 436                 return 16;
 437         case PIPE_SHADER_CAP_PREFERRED_IR:
 438                 return PIPE_SHADER_IR_TGSI;
 439         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 440                 return 0;
 441         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 442                 return 32;
 443         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 444         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 445                 return 0;
 446         }
 447         debug_printf("unknown shader param %d\n", param);
 448         return 0;
 449 }
 450
 451 boolean
 452 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 453                 struct fd_bo *bo,
 454                 unsigned stride,
 455                 struct winsys_handle *whandle)
 456 {
 457         whandle->stride = stride;
 458
 459         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 460                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 461         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 462                 whandle->handle = fd_bo_handle(bo);
 463                 return TRUE;
 464         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 465                 whandle->handle = fd_bo_dmabuf(bo);
 466                 return TRUE;
 467         } else {
 468                 return FALSE;
 469         }
 470 }
 471
 472 struct fd_bo *
 473 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 474                 struct winsys_handle *whandle,
 475                 unsigned *out_stride)
 476 {
 477         struct fd_screen *screen = fd_screen(pscreen);
 478         struct fd_bo *bo;
 479
 480         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 481                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 482         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 483                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 484         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 485                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 486         } else {
 487                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 488                 return NULL;
 489         }
 490
 491         if (!bo) {
 492                 DBG("ref name 0x%08x failed", whandle->handle);
 493                 return NULL;
 494         }
 495
 496         *out_stride = whandle->stride;
 497
 498         return bo;
 499 }
 500
 501 struct pipe_screen *
 502 fd_screen_create(struct fd_device *dev)
 503 {
 504         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 505         struct pipe_screen *pscreen;
 506         uint64_t val;
 507
 508         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 509
 510         if (fd_mesa_debug & FD_DBG_NOBIN)
 511                 fd_binning_enabled = false;
 512
 513         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 514
 515         if (!screen)
 516                 return NULL;
 517
 518         pscreen = &screen->base;
 519
 520         screen->dev = dev;
 521         screen->refcnt = 1;
 522
 523         // maybe this should be in context?
 524         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 525         if (!screen->pipe) {
 526                 DBG("could not create 3d pipe");
 527                 goto fail;
 528         }
 529
 530         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 531                 DBG("could not get GMEM size");
 532                 goto fail;
 533         }
 534         screen->gmemsize_bytes = val;
 535
 536         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 537                 DBG("could not get device-id");
 538                 goto fail;
 539         }
 540         screen->device_id = val;
 541
 542         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 543                 DBG("could not get gpu freq");
 544                 /* this limits what performance related queries are
 545                  * supported but is not fatal
 546                  */
 547                 screen->max_freq = 0;
 548         } else {
 549                 screen->max_freq = val;
 550         }
 551
 552         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 553                 DBG("could not get gpu-id");
 554                 goto fail;
 555         }
 556         screen->gpu_id = val;
 557
 558         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 559                 DBG("could not get chip-id");
 560                 /* older kernels may not have this property: */
 561                 unsigned core  = screen->gpu_id / 100;
 562                 unsigned major = (screen->gpu_id % 100) / 10;
 563                 unsigned minor = screen->gpu_id % 10;
 564                 unsigned patch = 0;  /* assume the worst */
 565                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 566                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 567         }
 568         screen->chip_id = val;
 569
 570         DBG("Pipe Info:");
 571         DBG(" GPU-id:          %d", screen->gpu_id);
 572         DBG(" Chip-id:         0x%08x", screen->chip_id);
 573         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 574
 575         /* explicitly checking for GPU revisions that are known to work.  This
 576          * may be overly conservative for a3xx, where spoofing the gpu_id with
 577          * the blob driver seems to generate identical cmdstream dumps.  But
 578          * on a2xx, there seem to be small differences between the GPU revs
 579          * so it is probably better to actually test first on real hardware
 580          * before enabling:
 581          *
 582          * If you have a different adreno version, feel free to add it to one
 583          * of the cases below and see what happens.  And if it works, please
 584          * send a patch ;-)
 585          */
 586         switch (screen->gpu_id) {
 587         case 220:
 588                 fd2_screen_init(pscreen);
 589                 break;
 590         case 305:
 591         case 307:
 592         case 320:
 593         case 330:
 594                 fd3_screen_init(pscreen);
 595                 break;
 596         case 420:
 597         case 430:
 598                 fd4_screen_init(pscreen);
 599                 break;
 600         default:
 601                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 602                 goto fail;
 603         }
 604
 605         pscreen->destroy = fd_screen_destroy;
 606         pscreen->get_param = fd_screen_get_param;
 607         pscreen->get_paramf = fd_screen_get_paramf;
 608         pscreen->get_shader_param = fd_screen_get_shader_param;
 609
 610         fd_resource_screen_init(pscreen);
 611         fd_query_screen_init(pscreen);
 612
 613         pscreen->get_name = fd_screen_get_name;
 614         pscreen->get_vendor = fd_screen_get_vendor;
 615         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 616
 617         pscreen->get_timestamp = fd_screen_get_timestamp;
 618
 619         pscreen->fence_reference = fd_screen_fence_ref;
 620         pscreen->fence_finish = fd_screen_fence_finish;
 621
 622         util_format_s3tc_init();
 623
 624         return pscreen;
 625
 626 fail:
 627         fd_screen_destroy(pscreen);
 628         return NULL;
 629 }