src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 #include "ir3/ir3_nir.h"
  58
  59 /* XXX this should go away */
  60 #include "state_tracker/drm_driver.h"
  61
  62 static const struct debug_named_value debug_options[] = {
  63                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  64                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  65                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  66                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  67                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  68                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  69                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  70                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  71                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  72                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  73                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  74                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  75                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  76                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  77                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  78                 DEBUG_NAMED_VALUE_END
  79 };
  80
  81 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  82
  83 int fd_mesa_debug = 0;
  84 bool fd_binning_enabled = true;
  85 static bool glsl120 = false;
  86
  87 static const char *
  88 fd_screen_get_name(struct pipe_screen *pscreen)
  89 {
  90         static char buffer[128];
  91         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  92                         fd_screen(pscreen)->device_id);
  93         return buffer;
  94 }
  95
  96 static const char *
  97 fd_screen_get_vendor(struct pipe_screen *pscreen)
  98 {
  99         return "freedreno";
 100 }
 101
 102 static const char *
 103 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 104 {
 105         return "Qualcomm";
 106 }
 107
 108
 109 static uint64_t
 110 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 111 {
 112         int64_t cpu_time = os_time_get() * 1000;
 113         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 114 }
 115
 116 static void
 117 fd_screen_destroy(struct pipe_screen *pscreen)
 118 {
 119         struct fd_screen *screen = fd_screen(pscreen);
 120
 121         if (screen->pipe)
 122                 fd_pipe_del(screen->pipe);
 123
 124         if (screen->dev)
 125                 fd_device_del(screen->dev);
 126
 127         free(screen);
 128 }
 129
 130 /*
 131 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 132 tables for things that differ if the delta is not too much..
 133  */
 134 static int
 135 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 136 {
 137         struct fd_screen *screen = fd_screen(pscreen);
 138
 139         /* this is probably not totally correct.. but it's a start: */
 140         switch (param) {
 141         /* Supported features (boolean caps). */
 142         case PIPE_CAP_NPOT_TEXTURES:
 143         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 144         case PIPE_CAP_TWO_SIDED_STENCIL:
 145         case PIPE_CAP_ANISOTROPIC_FILTER:
 146         case PIPE_CAP_POINT_SPRITE:
 147         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 148         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149         case PIPE_CAP_TEXTURE_SWIZZLE:
 150         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 152         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 153         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 154         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 155         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 156         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 157         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 158         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 159         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 160         case PIPE_CAP_VERTEXID_NOBASE:
 161         case PIPE_CAP_STRING_MARKER:
 162                 return 1;
 163
 164         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 165                 return is_ir3(screen) ? 0 : 1;
 166
 167         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 168         case PIPE_CAP_TGSI_TEXCOORD:
 169         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 170         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 171         case PIPE_CAP_TEXTURE_BARRIER:
 172         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 173         case PIPE_CAP_COMPUTE:
 174         case PIPE_CAP_QUERY_MEMORY_INFO:
 175         case PIPE_CAP_PCI_GROUP:
 176         case PIPE_CAP_PCI_BUS:
 177         case PIPE_CAP_PCI_DEVICE:
 178         case PIPE_CAP_PCI_FUNCTION:
 179                 return 0;
 180
 181         case PIPE_CAP_SM3:
 182         case PIPE_CAP_PRIMITIVE_RESTART:
 183         case PIPE_CAP_TGSI_INSTANCEID:
 184         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 185         case PIPE_CAP_INDEP_BLEND_ENABLE:
 186         case PIPE_CAP_INDEP_BLEND_FUNC:
 187         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 188         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189         case PIPE_CAP_CONDITIONAL_RENDER:
 190         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 191         case PIPE_CAP_FAKE_SW_MSAA:
 192         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 193         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 194         case PIPE_CAP_CLIP_HALFZ:
 195                 return is_a3xx(screen) || is_a4xx(screen);
 196
 197         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 198                 return 0;
 199         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 200                 if (is_a3xx(screen)) return 16;
 201                 if (is_a4xx(screen)) return 32;
 202                 return 0;
 203         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 204                 /* We could possibly emulate more by pretending 2d/rect textures and
 205                  * splitting high bits of index into 2nd dimension..
 206                  */
 207                 if (is_a3xx(screen)) return 8192;
 208                 if (is_a4xx(screen)) return 16384;
 209                 return 0;
 210
 211         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 212         case PIPE_CAP_CUBE_MAP_ARRAY:
 213         case PIPE_CAP_START_INSTANCE:
 214         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 215         case PIPE_CAP_TEXTURE_QUERY_LOD:
 216                 return is_a4xx(screen);
 217
 218         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 219                 return 64;
 220
 221         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 222                 if (glsl120)
 223                         return 120;
 224                 return is_ir3(screen) ? 140 : 120;
 225
 226         /* Unsupported features. */
 227         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 228         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 229         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 230         case PIPE_CAP_USER_VERTEX_BUFFERS:
 231         case PIPE_CAP_USER_INDEX_BUFFERS:
 232         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 233         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 234         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 235         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 236         case PIPE_CAP_TEXTURE_GATHER_SM5:
 237         case PIPE_CAP_SAMPLE_SHADING:
 238         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 239         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 240         case PIPE_CAP_DRAW_INDIRECT:
 241         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 242         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 243         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 244         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 245         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 246         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 247         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 248         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 249         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 250         case PIPE_CAP_TGSI_TXQS:
 251         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 252         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 253         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 254         case PIPE_CAP_CLEAR_TEXTURE:
 255         case PIPE_CAP_DRAW_PARAMETERS:
 256         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 257         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 258         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 259         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 260         case PIPE_CAP_INVALIDATE_BUFFER:
 261         case PIPE_CAP_GENERATE_MIPMAP:
 262         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 263         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 264         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 265         case PIPE_CAP_CULL_DISTANCE:
 266         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 267         case PIPE_CAP_TGSI_VOTE:
 268         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 269         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 270         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 271                 return 0;
 272
 273         case PIPE_CAP_MAX_VIEWPORTS:
 274                 return 1;
 275
 276         case PIPE_CAP_SHAREABLE_SHADERS:
 277         /* manage the variants for these ourself, to avoid breaking precompile: */
 278         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 279         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 280                 if (is_ir3(screen))
 281                         return 1;
 282                 return 0;
 283
 284         /* Stream output. */
 285         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 286                 if (is_ir3(screen))
 287                         return PIPE_MAX_SO_BUFFERS;
 288                 return 0;
 289         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 290                 if (is_ir3(screen))
 291                         return 1;
 292                 return 0;
 293         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 294         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 295                 if (is_ir3(screen))
 296                         return 16 * 4;   /* should only be shader out limit? */
 297                 return 0;
 298
 299         /* Geometry shader output, unsupported. */
 300         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 301         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 302         case PIPE_CAP_MAX_VERTEX_STREAMS:
 303                 return 0;
 304
 305         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 306                 return 2048;
 307
 308         /* Texturing. */
 309         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 310         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 311                 return MAX_MIP_LEVELS;
 312         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 313                 return 11;
 314
 315         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 316                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 317
 318         /* Render targets. */
 319         case PIPE_CAP_MAX_RENDER_TARGETS:
 320                 return screen->max_rts;
 321         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 322                 return is_a3xx(screen) ? 1 : 0;
 323
 324         /* Queries. */
 325         case PIPE_CAP_QUERY_TIMESTAMP:
 326         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 327                 return 0;
 328         case PIPE_CAP_OCCLUSION_QUERY:
 329                 return is_a3xx(screen) || is_a4xx(screen);
 330         case PIPE_CAP_QUERY_TIME_ELAPSED:
 331                 /* only a4xx, requires new enough kernel so we know max_freq: */
 332                 return (screen->max_freq > 0) && is_a4xx(screen);
 333
 334         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 335         case PIPE_CAP_MIN_TEXEL_OFFSET:
 336                 return -8;
 337
 338         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 339         case PIPE_CAP_MAX_TEXEL_OFFSET:
 340                 return 7;
 341
 342         case PIPE_CAP_ENDIANNESS:
 343                 return PIPE_ENDIAN_LITTLE;
 344
 345         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 346                 return 64;
 347
 348         case PIPE_CAP_VENDOR_ID:
 349                 return 0x5143;
 350         case PIPE_CAP_DEVICE_ID:
 351                 return 0xFFFFFFFF;
 352         case PIPE_CAP_ACCELERATED:
 353                 return 1;
 354         case PIPE_CAP_VIDEO_MEMORY:
 355                 DBG("FINISHME: The value returned is incorrect\n");
 356                 return 10;
 357         case PIPE_CAP_UMA:
 358                 return 1;
 359         }
 360         debug_printf("unknown param %d\n", param);
 361         return 0;
 362 }
 363
 364 static float
 365 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 366 {
 367         switch (param) {
 368         case PIPE_CAPF_MAX_LINE_WIDTH:
 369         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 370                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 371                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 372                  * uses too small of a render target size, and gets confused when
 373                  * the lines start going offscreen.
 374                  *
 375                  * See: https://code.google.com/p/android/issues/detail?id=206513
 376                  */
 377                 if (fd_mesa_debug & FD_DBG_DEQP)
 378                         return 48.0f;
 379                 return 127.0f;
 380         case PIPE_CAPF_MAX_POINT_WIDTH:
 381         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 382                 return 4092.0f;
 383         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 384                 return 16.0f;
 385         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 386                 return 15.0f;
 387         case PIPE_CAPF_GUARD_BAND_LEFT:
 388         case PIPE_CAPF_GUARD_BAND_TOP:
 389         case PIPE_CAPF_GUARD_BAND_RIGHT:
 390         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 391                 return 0.0f;
 392         }
 393         debug_printf("unknown paramf %d\n", param);
 394         return 0;
 395 }
 396
 397 static int
 398 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 399                 enum pipe_shader_cap param)
 400 {
 401         struct fd_screen *screen = fd_screen(pscreen);
 402
 403         switch(shader)
 404         {
 405         case PIPE_SHADER_FRAGMENT:
 406         case PIPE_SHADER_VERTEX:
 407                 break;
 408         case PIPE_SHADER_COMPUTE:
 409         case PIPE_SHADER_GEOMETRY:
 410                 /* maye we could emulate.. */
 411                 return 0;
 412         default:
 413                 DBG("unknown shader type %d", shader);
 414                 return 0;
 415         }
 416
 417         /* this is probably not totally correct.. but it's a start: */
 418         switch (param) {
 419         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 420         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 421         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 422         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 423                 return 16384;
 424         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 425                 return 8; /* XXX */
 426         case PIPE_SHADER_CAP_MAX_INPUTS:
 427         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 428                 return 16;
 429         case PIPE_SHADER_CAP_MAX_TEMPS:
 430                 return 64; /* Max native temporaries. */
 431         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 432                 /* NOTE: seems to be limit for a3xx is actually 512 but
 433                  * split between VS and FS.  Use lower limit of 256 to
 434                  * avoid getting into impossible situations:
 435                  */
 436                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 437         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 438                 return is_ir3(screen) ? 16 : 1;
 439         case PIPE_SHADER_CAP_MAX_PREDS:
 440                 return 0; /* nothing uses this */
 441         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 442                 return 1;
 443         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 444         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 445                 /* Technically this should be the same as for TEMP/CONST, since
 446                  * everything is just normal registers.  This is just temporary
 447                  * hack until load_input/store_output handle arrays in a similar
 448                  * way as load_var/store_var..
 449                  */
 450                 return 0;
 451         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 452         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 453                 /* a2xx compiler doesn't handle indirect: */
 454                 return is_ir3(screen) ? 1 : 0;
 455         case PIPE_SHADER_CAP_SUBROUTINES:
 456         case PIPE_SHADER_CAP_DOUBLES:
 457         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 458         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 459         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 460         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 461                 return 0;
 462         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 463                 return 1;
 464         case PIPE_SHADER_CAP_INTEGERS:
 465                 if (glsl120)
 466                         return 0;
 467                 return is_ir3(screen) ? 1 : 0;
 468         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 469         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 470                 return 16;
 471         case PIPE_SHADER_CAP_PREFERRED_IR:
 472                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 473                         return PIPE_SHADER_IR_NIR;
 474                 return PIPE_SHADER_IR_TGSI;
 475         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 476                 return 0;
 477         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 478                 return 32;
 479         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 480         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 481                 return 0;
 482         }
 483         debug_printf("unknown shader param %d\n", param);
 484         return 0;
 485 }
 486
 487 static const void *
 488 fd_get_compiler_options(struct pipe_screen *pscreen,
 489                 enum pipe_shader_ir ir, unsigned shader)
 490 {
 491         struct fd_screen *screen = fd_screen(pscreen);
 492
 493         if (is_ir3(screen))
 494                 return ir3_get_compiler_options();
 495
 496         return NULL;
 497 }
 498
 499 boolean
 500 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 501                 struct fd_bo *bo,
 502                 unsigned stride,
 503                 struct winsys_handle *whandle)
 504 {
 505         whandle->stride = stride;
 506
 507         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 508                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 509         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 510                 whandle->handle = fd_bo_handle(bo);
 511                 return TRUE;
 512         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 513                 whandle->handle = fd_bo_dmabuf(bo);
 514                 return TRUE;
 515         } else {
 516                 return FALSE;
 517         }
 518 }
 519
 520 struct fd_bo *
 521 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 522                 struct winsys_handle *whandle,
 523                 unsigned *out_stride)
 524 {
 525         struct fd_screen *screen = fd_screen(pscreen);
 526         struct fd_bo *bo;
 527
 528         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 529                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 530         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 531                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 532         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 533                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 534         } else {
 535                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 536                 return NULL;
 537         }
 538
 539         if (!bo) {
 540                 DBG("ref name 0x%08x failed", whandle->handle);
 541                 return NULL;
 542         }
 543
 544         *out_stride = whandle->stride;
 545
 546         return bo;
 547 }
 548
 549 struct pipe_screen *
 550 fd_screen_create(struct fd_device *dev)
 551 {
 552         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 553         struct pipe_screen *pscreen;
 554         uint64_t val;
 555
 556         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 557
 558         if (fd_mesa_debug & FD_DBG_NOBIN)
 559                 fd_binning_enabled = false;
 560
 561         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 562
 563         if (!screen)
 564                 return NULL;
 565
 566         pscreen = &screen->base;
 567
 568         screen->dev = dev;
 569         screen->refcnt = 1;
 570
 571         // maybe this should be in context?
 572         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 573         if (!screen->pipe) {
 574                 DBG("could not create 3d pipe");
 575                 goto fail;
 576         }
 577
 578         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 579                 DBG("could not get GMEM size");
 580                 goto fail;
 581         }
 582         screen->gmemsize_bytes = val;
 583
 584         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 585                 DBG("could not get device-id");
 586                 goto fail;
 587         }
 588         screen->device_id = val;
 589
 590         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 591                 DBG("could not get gpu freq");
 592                 /* this limits what performance related queries are
 593                  * supported but is not fatal
 594                  */
 595                 screen->max_freq = 0;
 596         } else {
 597                 screen->max_freq = val;
 598         }
 599
 600         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 601                 DBG("could not get gpu-id");
 602                 goto fail;
 603         }
 604         screen->gpu_id = val;
 605
 606         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 607                 DBG("could not get chip-id");
 608                 /* older kernels may not have this property: */
 609                 unsigned core  = screen->gpu_id / 100;
 610                 unsigned major = (screen->gpu_id % 100) / 10;
 611                 unsigned minor = screen->gpu_id % 10;
 612                 unsigned patch = 0;  /* assume the worst */
 613                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 614                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 615         }
 616         screen->chip_id = val;
 617
 618         DBG("Pipe Info:");
 619         DBG(" GPU-id:          %d", screen->gpu_id);
 620         DBG(" Chip-id:         0x%08x", screen->chip_id);
 621         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 622
 623         /* explicitly checking for GPU revisions that are known to work.  This
 624          * may be overly conservative for a3xx, where spoofing the gpu_id with
 625          * the blob driver seems to generate identical cmdstream dumps.  But
 626          * on a2xx, there seem to be small differences between the GPU revs
 627          * so it is probably better to actually test first on real hardware
 628          * before enabling:
 629          *
 630          * If you have a different adreno version, feel free to add it to one
 631          * of the cases below and see what happens.  And if it works, please
 632          * send a patch ;-)
 633          */
 634         switch (screen->gpu_id) {
 635         case 220:
 636                 fd2_screen_init(pscreen);
 637                 break;
 638         case 305:
 639         case 307:
 640         case 320:
 641         case 330:
 642                 fd3_screen_init(pscreen);
 643                 break;
 644         case 420:
 645         case 430:
 646                 fd4_screen_init(pscreen);
 647                 break;
 648         default:
 649                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 650                 goto fail;
 651         }
 652
 653         pscreen->destroy = fd_screen_destroy;
 654         pscreen->get_param = fd_screen_get_param;
 655         pscreen->get_paramf = fd_screen_get_paramf;
 656         pscreen->get_shader_param = fd_screen_get_shader_param;
 657         pscreen->get_compiler_options = fd_get_compiler_options;
 658
 659         fd_resource_screen_init(pscreen);
 660         fd_query_screen_init(pscreen);
 661
 662         pscreen->get_name = fd_screen_get_name;
 663         pscreen->get_vendor = fd_screen_get_vendor;
 664         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 665
 666         pscreen->get_timestamp = fd_screen_get_timestamp;
 667
 668         pscreen->fence_reference = fd_screen_fence_ref;
 669         pscreen->fence_finish = fd_screen_fence_finish;
 670
 671         util_format_s3tc_init();
 672
 673         return pscreen;
 674
 675 fail:
 676         fd_screen_destroy(pscreen);
 677         return NULL;
 678 }