1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
41 #include "util/os_time.h"
46 #include <sys/sysinfo.h>
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
59 #include "ir3/ir3_nir.h"
61 /* XXX this should go away */
62 #include "state_tracker/drm_driver.h"
64 static const struct debug_named_value debug_options
[] = {
65 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
66 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
67 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
68 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
69 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
70 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
71 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
72 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
73 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
74 {"optmsgs", FD_DBG_OPTMSGS
,"Enable optimizer debug messages"},
75 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
76 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
77 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
78 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
79 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
83 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
84 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
85 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
86 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a5xx)"},
90 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
92 int fd_mesa_debug
= 0;
93 bool fd_binning_enabled
= true;
94 static bool glsl120
= false;
97 fd_screen_get_name(struct pipe_screen
*pscreen
)
99 static char buffer
[128];
100 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
101 fd_screen(pscreen
)->device_id
);
106 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
112 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
119 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
121 struct fd_screen
*screen
= fd_screen(pscreen
);
123 if (screen
->has_timestamp
) {
125 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
126 debug_assert(screen
->max_freq
> 0);
127 return n
* 1000000000 / screen
->max_freq
;
129 int64_t cpu_time
= os_time_get() * 1000;
130 return cpu_time
+ screen
->cpu_gpu_time_delta
;
136 fd_screen_destroy(struct pipe_screen
*pscreen
)
138 struct fd_screen
*screen
= fd_screen(pscreen
);
141 fd_pipe_del(screen
->pipe
);
144 fd_device_del(screen
->dev
);
146 fd_bc_fini(&screen
->batch_cache
);
148 slab_destroy_parent(&screen
->transfer_pool
);
150 mtx_destroy(&screen
->lock
);
152 ralloc_free(screen
->compiler
);
158 TODO either move caps to a2xx/a3xx specific code, or maybe have some
159 tables for things that differ if the delta is not too much..
162 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
164 struct fd_screen
*screen
= fd_screen(pscreen
);
166 /* this is probably not totally correct.. but it's a start: */
168 /* Supported features (boolean caps). */
169 case PIPE_CAP_NPOT_TEXTURES
:
170 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
171 case PIPE_CAP_ANISOTROPIC_FILTER
:
172 case PIPE_CAP_POINT_SPRITE
:
173 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
174 case PIPE_CAP_TEXTURE_SWIZZLE
:
175 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
176 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
177 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
178 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
179 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
180 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
181 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
182 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
183 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
184 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
185 case PIPE_CAP_STRING_MARKER
:
186 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
187 case PIPE_CAP_TEXTURE_BARRIER
:
188 case PIPE_CAP_INVALIDATE_BUFFER
:
191 case PIPE_CAP_VERTEXID_NOBASE
:
192 return is_a3xx(screen
) || is_a4xx(screen
);
194 case PIPE_CAP_COMPUTE
:
195 return has_compute(screen
);
197 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
198 case PIPE_CAP_TGSI_TEXCOORD
:
199 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
200 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
201 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
202 case PIPE_CAP_QUERY_MEMORY_INFO
:
203 case PIPE_CAP_PCI_GROUP
:
204 case PIPE_CAP_PCI_BUS
:
205 case PIPE_CAP_PCI_DEVICE
:
206 case PIPE_CAP_PCI_FUNCTION
:
210 case PIPE_CAP_PRIMITIVE_RESTART
:
211 case PIPE_CAP_TGSI_INSTANCEID
:
212 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
213 case PIPE_CAP_INDEP_BLEND_ENABLE
:
214 case PIPE_CAP_INDEP_BLEND_FUNC
:
215 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
216 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
217 case PIPE_CAP_CONDITIONAL_RENDER
:
218 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
219 case PIPE_CAP_FAKE_SW_MSAA
:
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
221 case PIPE_CAP_CLIP_HALFZ
:
222 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
);
224 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
225 return is_a3xx(screen
) || is_a4xx(screen
);
227 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
228 return is_a5xx(screen
);
230 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
232 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
233 if (is_a3xx(screen
)) return 16;
234 if (is_a4xx(screen
)) return 32;
235 if (is_a5xx(screen
)) return 32;
237 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
238 /* We could possibly emulate more by pretending 2d/rect textures and
239 * splitting high bits of index into 2nd dimension..
241 if (is_a3xx(screen
)) return 8192;
242 if (is_a4xx(screen
)) return 16384;
243 if (is_a5xx(screen
)) return 16384;
246 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
247 case PIPE_CAP_CUBE_MAP_ARRAY
:
248 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
249 case PIPE_CAP_TEXTURE_QUERY_LOD
:
250 return is_a4xx(screen
) || is_a5xx(screen
);
252 case PIPE_CAP_START_INSTANCE
:
253 /* Note that a5xx can do this, it just can't (at least with
254 * current firmware) do draw_indirect with base_instance.
255 * Since draw_indirect is needed sooner (gles31 and gl40 vs
256 * gl42), hide base_instance on a5xx. :-/
258 return is_a4xx(screen
);
260 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
263 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
264 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
267 return is_ir3(screen
) ? 140 : 120;
269 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
274 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
275 if (is_a4xx(screen
) || is_a5xx(screen
))
279 /* Unsupported features. */
280 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
281 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
282 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
283 case PIPE_CAP_USER_VERTEX_BUFFERS
:
284 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
285 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
286 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
287 case PIPE_CAP_TEXTURE_GATHER_SM5
:
288 case PIPE_CAP_SAMPLE_SHADING
:
289 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
290 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
291 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
292 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
293 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
294 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
295 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
296 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
297 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
298 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
299 case PIPE_CAP_TGSI_TXQS
:
300 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
301 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
302 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
303 case PIPE_CAP_CLEAR_TEXTURE
:
304 case PIPE_CAP_DRAW_PARAMETERS
:
305 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
306 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
307 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
308 case PIPE_CAP_GENERATE_MIPMAP
:
309 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
310 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
311 case PIPE_CAP_CULL_DISTANCE
:
312 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
313 case PIPE_CAP_TGSI_VOTE
:
314 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
315 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
316 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
317 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
318 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
319 case PIPE_CAP_TGSI_FS_FBFETCH
:
320 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
321 case PIPE_CAP_DOUBLES
:
323 case PIPE_CAP_INT64_DIVMOD
:
324 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
325 case PIPE_CAP_TGSI_CLOCK
:
326 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
327 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
328 case PIPE_CAP_TGSI_BALLOT
:
329 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
330 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
331 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
332 case PIPE_CAP_POST_DEPTH_COVERAGE
:
333 case PIPE_CAP_BINDLESS_TEXTURE
:
334 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
335 case PIPE_CAP_QUERY_SO_OVERFLOW
:
336 case PIPE_CAP_MEMOBJ
:
337 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
338 case PIPE_CAP_TILE_RASTER_ORDER
:
339 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
340 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
341 case PIPE_CAP_FENCE_SIGNAL
:
342 case PIPE_CAP_CONSTBUF0_FLAGS
:
343 case PIPE_CAP_PACKED_UNIFORMS
:
344 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
345 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
346 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
347 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
348 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
349 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
350 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
353 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
354 return screen
->priority_mask
;
356 case PIPE_CAP_DRAW_INDIRECT
:
357 if (is_a4xx(screen
) || is_a5xx(screen
))
361 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
362 if (is_a4xx(screen
) || is_a5xx(screen
))
366 case PIPE_CAP_LOAD_CONSTBUF
:
367 /* name is confusing, but this turns on std430 packing */
372 case PIPE_CAP_MAX_VIEWPORTS
:
375 case PIPE_CAP_SHAREABLE_SHADERS
:
376 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
377 /* manage the variants for these ourself, to avoid breaking precompile: */
378 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
379 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
385 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
387 return PIPE_MAX_SO_BUFFERS
;
389 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
390 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
394 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
395 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
397 return 16 * 4; /* should only be shader out limit? */
400 /* Geometry shader output, unsupported. */
401 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
402 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
403 case PIPE_CAP_MAX_VERTEX_STREAMS
:
406 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
410 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
411 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
412 return MAX_MIP_LEVELS
;
413 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
416 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
417 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
)) ? 256 : 0;
419 /* Render targets. */
420 case PIPE_CAP_MAX_RENDER_TARGETS
:
421 return screen
->max_rts
;
422 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
423 return is_a3xx(screen
) ? 1 : 0;
426 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
428 case PIPE_CAP_OCCLUSION_QUERY
:
429 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
);
430 case PIPE_CAP_QUERY_TIMESTAMP
:
431 case PIPE_CAP_QUERY_TIME_ELAPSED
:
432 /* only a4xx, requires new enough kernel so we know max_freq: */
433 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
));
435 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
436 case PIPE_CAP_MIN_TEXEL_OFFSET
:
439 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
440 case PIPE_CAP_MAX_TEXEL_OFFSET
:
443 case PIPE_CAP_ENDIANNESS
:
444 return PIPE_ENDIAN_LITTLE
;
446 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
449 case PIPE_CAP_VENDOR_ID
:
451 case PIPE_CAP_DEVICE_ID
:
453 case PIPE_CAP_ACCELERATED
:
455 case PIPE_CAP_VIDEO_MEMORY
:
456 DBG("FINISHME: The value returned is incorrect\n");
460 case PIPE_CAP_NATIVE_FENCE_FD
:
461 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
463 debug_printf("unknown param %d\n", param
);
468 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
471 case PIPE_CAPF_MAX_LINE_WIDTH
:
472 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
473 /* NOTE: actual value is 127.0f, but this is working around a deqp
474 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
475 * uses too small of a render target size, and gets confused when
476 * the lines start going offscreen.
478 * See: https://code.google.com/p/android/issues/detail?id=206513
480 if (fd_mesa_debug
& FD_DBG_DEQP
)
483 case PIPE_CAPF_MAX_POINT_WIDTH
:
484 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
486 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
488 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
490 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
491 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
492 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
495 debug_printf("unknown paramf %d\n", param
);
500 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
501 enum pipe_shader_type shader
,
502 enum pipe_shader_cap param
)
504 struct fd_screen
*screen
= fd_screen(pscreen
);
508 case PIPE_SHADER_FRAGMENT
:
509 case PIPE_SHADER_VERTEX
:
511 case PIPE_SHADER_COMPUTE
:
512 if (has_compute(screen
))
515 case PIPE_SHADER_GEOMETRY
:
516 /* maye we could emulate.. */
519 DBG("unknown shader type %d", shader
);
523 /* this is probably not totally correct.. but it's a start: */
525 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
526 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
527 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
528 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
530 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
532 case PIPE_SHADER_CAP_MAX_INPUTS
:
533 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
535 case PIPE_SHADER_CAP_MAX_TEMPS
:
536 return 64; /* Max native temporaries. */
537 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
538 /* NOTE: seems to be limit for a3xx is actually 512 but
539 * split between VS and FS. Use lower limit of 256 to
540 * avoid getting into impossible situations:
542 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
543 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
544 return is_ir3(screen
) ? 16 : 1;
545 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
547 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
548 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
549 /* Technically this should be the same as for TEMP/CONST, since
550 * everything is just normal registers. This is just temporary
551 * hack until load_input/store_output handle arrays in a similar
552 * way as load_var/store_var..
555 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
556 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
557 /* a2xx compiler doesn't handle indirect: */
558 return is_ir3(screen
) ? 1 : 0;
559 case PIPE_SHADER_CAP_SUBROUTINES
:
560 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
561 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
562 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
563 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
564 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
566 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
568 case PIPE_SHADER_CAP_INTEGERS
:
571 return is_ir3(screen
) ? 1 : 0;
572 case PIPE_SHADER_CAP_INT64_ATOMICS
:
574 case PIPE_SHADER_CAP_FP16
:
576 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
577 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
579 case PIPE_SHADER_CAP_PREFERRED_IR
:
581 return PIPE_SHADER_IR_NIR
;
582 return PIPE_SHADER_IR_TGSI
;
583 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
584 if (is_ir3(screen
)) {
585 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
587 return (1 << PIPE_SHADER_IR_TGSI
);
590 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
592 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
593 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
594 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
595 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
597 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
598 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
599 if (is_a5xx(screen
)) {
600 /* a5xx (and a4xx for that matter) has one state-block
601 * for compute-shader SSBO's and another that is shared
602 * by VS/HS/DS/GS/FS.. so to simplify things for now
603 * just advertise SSBOs for FS and CS. We could possibly
604 * do what blob does, and partition the space for
605 * VS/HS/DS/GS/FS. The blob advertises:
607 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
608 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
609 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
610 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
611 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
612 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
613 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
615 * I think that way we could avoid having to patch shaders
616 * for actual SSBO indexes by using a static partitioning.
618 * Note same state block is used for images and buffers,
619 * but images also need texture state for read access
624 case PIPE_SHADER_FRAGMENT
:
625 case PIPE_SHADER_COMPUTE
:
633 debug_printf("unknown shader param %d\n", param
);
637 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
638 * into per-generation backend?
641 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
642 enum pipe_compute_cap param
, void *ret
)
644 struct fd_screen
*screen
= fd_screen(pscreen
);
645 const char * const ir
= "ir3";
647 if (!has_compute(screen
))
650 #define RET(x) do { \
652 memcpy(ret, x, sizeof(x)); \
657 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
658 // don't expose 64b pointer support yet, until ir3 supports 64b
659 // math, otherwise spir64 target is used and we get 64b pointer
660 // calculations that we can't do yet
661 // if (is_a5xx(screen))
662 // RET((uint32_t []){ 64 });
663 RET((uint32_t []){ 32 });
665 case PIPE_COMPUTE_CAP_IR_TARGET
:
668 return strlen(ir
) * sizeof(char);
670 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
671 RET((uint64_t []) { 3 });
673 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
674 RET(((uint64_t []) { 65535, 65535, 65535 }));
676 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
677 RET(((uint64_t []) { 1024, 1024, 64 }));
679 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
680 RET((uint64_t []) { 1024 });
682 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
683 RET((uint64_t []) { screen
->ram_size
});
685 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
686 RET((uint64_t []) { 32768 });
688 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
689 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
690 RET((uint64_t []) { 4096 });
692 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
693 RET((uint64_t []) { screen
->ram_size
});
695 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
696 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
698 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
699 RET((uint32_t []) { 9999 }); // TODO
701 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
702 RET((uint32_t []) { 1 });
704 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
705 RET((uint32_t []) { 32 }); // TODO
707 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
708 RET((uint64_t []) { 1024 }); // TODO
715 fd_get_compiler_options(struct pipe_screen
*pscreen
,
716 enum pipe_shader_ir ir
, unsigned shader
)
718 struct fd_screen
*screen
= fd_screen(pscreen
);
721 return ir3_get_compiler_options(screen
->compiler
);
727 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
730 struct winsys_handle
*whandle
)
732 whandle
->stride
= stride
;
734 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
735 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
736 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
737 whandle
->handle
= fd_bo_handle(bo
);
739 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
740 whandle
->handle
= fd_bo_dmabuf(bo
);
748 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
749 struct winsys_handle
*whandle
)
751 struct fd_screen
*screen
= fd_screen(pscreen
);
754 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
755 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
756 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
757 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
758 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
759 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
761 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
766 DBG("ref name 0x%08x failed", whandle
->handle
);
774 fd_screen_create(struct fd_device
*dev
)
776 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
777 struct pipe_screen
*pscreen
;
780 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
782 if (fd_mesa_debug
& FD_DBG_NOBIN
)
783 fd_binning_enabled
= false;
785 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
790 pscreen
= &screen
->base
;
795 // maybe this should be in context?
796 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
798 DBG("could not create 3d pipe");
802 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
803 DBG("could not get GMEM size");
806 screen
->gmemsize_bytes
= val
;
808 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
809 DBG("could not get device-id");
812 screen
->device_id
= val
;
814 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
815 DBG("could not get gpu freq");
816 /* this limits what performance related queries are
817 * supported but is not fatal
819 screen
->max_freq
= 0;
821 screen
->max_freq
= val
;
822 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
823 screen
->has_timestamp
= true;
826 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
827 DBG("could not get gpu-id");
830 screen
->gpu_id
= val
;
832 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
833 DBG("could not get chip-id");
834 /* older kernels may not have this property: */
835 unsigned core
= screen
->gpu_id
/ 100;
836 unsigned major
= (screen
->gpu_id
% 100) / 10;
837 unsigned minor
= screen
->gpu_id
% 10;
838 unsigned patch
= 0; /* assume the worst */
839 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
840 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
842 screen
->chip_id
= val
;
844 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
845 DBG("could not get # of rings");
846 screen
->priority_mask
= 0;
848 /* # of rings equates to number of unique priority values: */
849 screen
->priority_mask
= (1 << val
) - 1;
854 screen
->ram_size
= si
.totalram
;
857 DBG(" GPU-id: %d", screen
->gpu_id
);
858 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
859 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
861 /* explicitly checking for GPU revisions that are known to work. This
862 * may be overly conservative for a3xx, where spoofing the gpu_id with
863 * the blob driver seems to generate identical cmdstream dumps. But
864 * on a2xx, there seem to be small differences between the GPU revs
865 * so it is probably better to actually test first on real hardware
868 * If you have a different adreno version, feel free to add it to one
869 * of the cases below and see what happens. And if it works, please
872 switch (screen
->gpu_id
) {
874 fd2_screen_init(pscreen
);
880 fd3_screen_init(pscreen
);
884 fd4_screen_init(pscreen
);
887 fd5_screen_init(pscreen
);
890 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
894 if (screen
->gpu_id
>= 500) {
895 screen
->gmem_alignw
= 64;
896 screen
->gmem_alignh
= 32;
897 screen
->num_vsc_pipes
= 16;
899 screen
->gmem_alignw
= 32;
900 screen
->gmem_alignh
= 32;
901 screen
->num_vsc_pipes
= 8;
904 /* NOTE: don't enable reordering on a2xx, since completely untested.
905 * Also, don't enable if we have too old of a kernel to support
906 * growable cmdstream buffers, since memory requirement for cmdstream
907 * buffers would be too much otherwise.
909 if ((screen
->gpu_id
>= 300) && (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
))
910 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
912 fd_bc_init(&screen
->batch_cache
);
914 (void) mtx_init(&screen
->lock
, mtx_plain
);
916 pscreen
->destroy
= fd_screen_destroy
;
917 pscreen
->get_param
= fd_screen_get_param
;
918 pscreen
->get_paramf
= fd_screen_get_paramf
;
919 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
920 pscreen
->get_compute_param
= fd_get_compute_param
;
921 pscreen
->get_compiler_options
= fd_get_compiler_options
;
923 fd_resource_screen_init(pscreen
);
924 fd_query_screen_init(pscreen
);
926 pscreen
->get_name
= fd_screen_get_name
;
927 pscreen
->get_vendor
= fd_screen_get_vendor
;
928 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
930 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
932 pscreen
->fence_reference
= fd_fence_ref
;
933 pscreen
->fence_finish
= fd_fence_finish
;
934 pscreen
->fence_get_fd
= fd_fence_get_fd
;
936 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
941 fd_screen_destroy(pscreen
);