src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 #include "ir3/ir3_nir.h"
  58
  59 /* XXX this should go away */
  60 #include "state_tracker/drm_driver.h"
  61
  62 static const struct debug_named_value debug_options[] = {
  63                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  64                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  65                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  66                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  67                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  68                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  69                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  70                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  71                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  72                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  73                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  74                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  75                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  76                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  77                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  78                 DEBUG_NAMED_VALUE_END
  79 };
  80
  81 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  82
  83 int fd_mesa_debug = 0;
  84 bool fd_binning_enabled = true;
  85 static bool glsl120 = false;
  86
  87 static const char *
  88 fd_screen_get_name(struct pipe_screen *pscreen)
  89 {
  90         static char buffer[128];
  91         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  92                         fd_screen(pscreen)->device_id);
  93         return buffer;
  94 }
  95
  96 static const char *
  97 fd_screen_get_vendor(struct pipe_screen *pscreen)
  98 {
  99         return "freedreno";
 100 }
 101
 102 static const char *
 103 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 104 {
 105         return "Qualcomm";
 106 }
 107
 108
 109 static uint64_t
 110 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 111 {
 112         struct fd_screen *screen = fd_screen(pscreen);
 113
 114         if (screen->has_timestamp) {
 115                 uint64_t n;
 116                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 117                 debug_assert(screen->max_freq > 0);
 118                 return n * 1000000000 / screen->max_freq;
 119         } else {
 120                 int64_t cpu_time = os_time_get() * 1000;
 121                 return cpu_time + screen->cpu_gpu_time_delta;
 122         }
 123
 124 }
 125
 126 static void
 127 fd_screen_destroy(struct pipe_screen *pscreen)
 128 {
 129         struct fd_screen *screen = fd_screen(pscreen);
 130
 131         if (screen->pipe)
 132                 fd_pipe_del(screen->pipe);
 133
 134         if (screen->dev)
 135                 fd_device_del(screen->dev);
 136
 137         free(screen);
 138 }
 139
 140 /*
 141 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 142 tables for things that differ if the delta is not too much..
 143  */
 144 static int
 145 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 146 {
 147         struct fd_screen *screen = fd_screen(pscreen);
 148
 149         /* this is probably not totally correct.. but it's a start: */
 150         switch (param) {
 151         /* Supported features (boolean caps). */
 152         case PIPE_CAP_NPOT_TEXTURES:
 153         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 154         case PIPE_CAP_TWO_SIDED_STENCIL:
 155         case PIPE_CAP_ANISOTROPIC_FILTER:
 156         case PIPE_CAP_POINT_SPRITE:
 157         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 158         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 159         case PIPE_CAP_TEXTURE_SWIZZLE:
 160         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 161         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 162         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 163         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 164         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 165         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 166         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 167         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 168         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 169         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 170         case PIPE_CAP_VERTEXID_NOBASE:
 171         case PIPE_CAP_STRING_MARKER:
 172                 return 1;
 173
 174         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 175                 return is_a4xx(screen) ? 0 : 1;
 176
 177         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 178         case PIPE_CAP_TGSI_TEXCOORD:
 179         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 180         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 181         case PIPE_CAP_TEXTURE_BARRIER:
 182         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 183         case PIPE_CAP_COMPUTE:
 184         case PIPE_CAP_QUERY_MEMORY_INFO:
 185         case PIPE_CAP_PCI_GROUP:
 186         case PIPE_CAP_PCI_BUS:
 187         case PIPE_CAP_PCI_DEVICE:
 188         case PIPE_CAP_PCI_FUNCTION:
 189                 return 0;
 190
 191         case PIPE_CAP_SM3:
 192         case PIPE_CAP_PRIMITIVE_RESTART:
 193         case PIPE_CAP_TGSI_INSTANCEID:
 194         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 195         case PIPE_CAP_INDEP_BLEND_ENABLE:
 196         case PIPE_CAP_INDEP_BLEND_FUNC:
 197         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 198         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 199         case PIPE_CAP_CONDITIONAL_RENDER:
 200         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 201         case PIPE_CAP_FAKE_SW_MSAA:
 202         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 203         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 204         case PIPE_CAP_CLIP_HALFZ:
 205                 return is_a3xx(screen) || is_a4xx(screen);
 206
 207         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 208                 return 0;
 209         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 210                 if (is_a3xx(screen)) return 16;
 211                 if (is_a4xx(screen)) return 32;
 212                 return 0;
 213         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 214                 /* We could possibly emulate more by pretending 2d/rect textures and
 215                  * splitting high bits of index into 2nd dimension..
 216                  */
 217                 if (is_a3xx(screen)) return 8192;
 218                 if (is_a4xx(screen)) return 16384;
 219                 return 0;
 220
 221         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 222         case PIPE_CAP_CUBE_MAP_ARRAY:
 223         case PIPE_CAP_START_INSTANCE:
 224         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 225         case PIPE_CAP_TEXTURE_QUERY_LOD:
 226                 return is_a4xx(screen);
 227
 228         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 229                 return 64;
 230
 231         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 232                 if (glsl120)
 233                         return 120;
 234                 return is_ir3(screen) ? 140 : 120;
 235
 236         /* Unsupported features. */
 237         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 238         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 239         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 240         case PIPE_CAP_USER_VERTEX_BUFFERS:
 241         case PIPE_CAP_USER_INDEX_BUFFERS:
 242         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 243         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 244         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 245         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 246         case PIPE_CAP_TEXTURE_GATHER_SM5:
 247         case PIPE_CAP_SAMPLE_SHADING:
 248         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 249         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 250         case PIPE_CAP_DRAW_INDIRECT:
 251         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 252         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 253         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 254         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 255         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 256         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 257         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 258         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 259         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 260         case PIPE_CAP_TGSI_TXQS:
 261         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 262         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 263         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 264         case PIPE_CAP_CLEAR_TEXTURE:
 265         case PIPE_CAP_DRAW_PARAMETERS:
 266         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 267         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 268         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 269         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 270         case PIPE_CAP_INVALIDATE_BUFFER:
 271         case PIPE_CAP_GENERATE_MIPMAP:
 272         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 273         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 274         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 275         case PIPE_CAP_CULL_DISTANCE:
 276         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 277         case PIPE_CAP_TGSI_VOTE:
 278         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 279         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 280         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 281                 return 0;
 282
 283         case PIPE_CAP_MAX_VIEWPORTS:
 284                 return 1;
 285
 286         case PIPE_CAP_SHAREABLE_SHADERS:
 287         /* manage the variants for these ourself, to avoid breaking precompile: */
 288         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 289         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 290                 if (is_ir3(screen))
 291                         return 1;
 292                 return 0;
 293
 294         /* Stream output. */
 295         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 296                 if (is_ir3(screen))
 297                         return PIPE_MAX_SO_BUFFERS;
 298                 return 0;
 299         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 300                 if (is_ir3(screen))
 301                         return 1;
 302                 return 0;
 303         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 304         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 305                 if (is_ir3(screen))
 306                         return 16 * 4;   /* should only be shader out limit? */
 307                 return 0;
 308
 309         /* Geometry shader output, unsupported. */
 310         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 311         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 312         case PIPE_CAP_MAX_VERTEX_STREAMS:
 313                 return 0;
 314
 315         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 316                 return 2048;
 317
 318         /* Texturing. */
 319         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 320         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 321                 return MAX_MIP_LEVELS;
 322         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 323                 return 11;
 324
 325         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 326                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 327
 328         /* Render targets. */
 329         case PIPE_CAP_MAX_RENDER_TARGETS:
 330                 return screen->max_rts;
 331         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 332                 return is_a3xx(screen) ? 1 : 0;
 333
 334         /* Queries. */
 335         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 336                 return 0;
 337         case PIPE_CAP_OCCLUSION_QUERY:
 338                 return is_a3xx(screen) || is_a4xx(screen);
 339         case PIPE_CAP_QUERY_TIMESTAMP:
 340         case PIPE_CAP_QUERY_TIME_ELAPSED:
 341                 /* only a4xx, requires new enough kernel so we know max_freq: */
 342                 return (screen->max_freq > 0) && is_a4xx(screen);
 343
 344         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 345         case PIPE_CAP_MIN_TEXEL_OFFSET:
 346                 return -8;
 347
 348         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 349         case PIPE_CAP_MAX_TEXEL_OFFSET:
 350                 return 7;
 351
 352         case PIPE_CAP_ENDIANNESS:
 353                 return PIPE_ENDIAN_LITTLE;
 354
 355         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 356                 return 64;
 357
 358         case PIPE_CAP_VENDOR_ID:
 359                 return 0x5143;
 360         case PIPE_CAP_DEVICE_ID:
 361                 return 0xFFFFFFFF;
 362         case PIPE_CAP_ACCELERATED:
 363                 return 1;
 364         case PIPE_CAP_VIDEO_MEMORY:
 365                 DBG("FINISHME: The value returned is incorrect\n");
 366                 return 10;
 367         case PIPE_CAP_UMA:
 368                 return 1;
 369         }
 370         debug_printf("unknown param %d\n", param);
 371         return 0;
 372 }
 373
 374 static float
 375 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 376 {
 377         switch (param) {
 378         case PIPE_CAPF_MAX_LINE_WIDTH:
 379         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 380                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 381                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 382                  * uses too small of a render target size, and gets confused when
 383                  * the lines start going offscreen.
 384                  *
 385                  * See: https://code.google.com/p/android/issues/detail?id=206513
 386                  */
 387                 if (fd_mesa_debug & FD_DBG_DEQP)
 388                         return 48.0f;
 389                 return 127.0f;
 390         case PIPE_CAPF_MAX_POINT_WIDTH:
 391         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 392                 return 4092.0f;
 393         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 394                 return 16.0f;
 395         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 396                 return 15.0f;
 397         case PIPE_CAPF_GUARD_BAND_LEFT:
 398         case PIPE_CAPF_GUARD_BAND_TOP:
 399         case PIPE_CAPF_GUARD_BAND_RIGHT:
 400         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 401                 return 0.0f;
 402         }
 403         debug_printf("unknown paramf %d\n", param);
 404         return 0;
 405 }
 406
 407 static int
 408 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 409                 enum pipe_shader_cap param)
 410 {
 411         struct fd_screen *screen = fd_screen(pscreen);
 412
 413         switch(shader)
 414         {
 415         case PIPE_SHADER_FRAGMENT:
 416         case PIPE_SHADER_VERTEX:
 417                 break;
 418         case PIPE_SHADER_COMPUTE:
 419         case PIPE_SHADER_GEOMETRY:
 420                 /* maye we could emulate.. */
 421                 return 0;
 422         default:
 423                 DBG("unknown shader type %d", shader);
 424                 return 0;
 425         }
 426
 427         /* this is probably not totally correct.. but it's a start: */
 428         switch (param) {
 429         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 430         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 431         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 432         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 433                 return 16384;
 434         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 435                 return 8; /* XXX */
 436         case PIPE_SHADER_CAP_MAX_INPUTS:
 437         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 438                 return 16;
 439         case PIPE_SHADER_CAP_MAX_TEMPS:
 440                 return 64; /* Max native temporaries. */
 441         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 442                 /* NOTE: seems to be limit for a3xx is actually 512 but
 443                  * split between VS and FS.  Use lower limit of 256 to
 444                  * avoid getting into impossible situations:
 445                  */
 446                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 447         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 448                 return is_ir3(screen) ? 16 : 1;
 449         case PIPE_SHADER_CAP_MAX_PREDS:
 450                 return 0; /* nothing uses this */
 451         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 452                 return 1;
 453         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 454         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 455                 /* Technically this should be the same as for TEMP/CONST, since
 456                  * everything is just normal registers.  This is just temporary
 457                  * hack until load_input/store_output handle arrays in a similar
 458                  * way as load_var/store_var..
 459                  */
 460                 return 0;
 461         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 462         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 463                 /* a2xx compiler doesn't handle indirect: */
 464                 return is_ir3(screen) ? 1 : 0;
 465         case PIPE_SHADER_CAP_SUBROUTINES:
 466         case PIPE_SHADER_CAP_DOUBLES:
 467         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 468         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 469         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 470         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 471                 return 0;
 472         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 473                 return 1;
 474         case PIPE_SHADER_CAP_INTEGERS:
 475                 if (glsl120)
 476                         return 0;
 477                 return is_ir3(screen) ? 1 : 0;
 478         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 479         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 480                 return 16;
 481         case PIPE_SHADER_CAP_PREFERRED_IR:
 482                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 483                         return PIPE_SHADER_IR_NIR;
 484                 return PIPE_SHADER_IR_TGSI;
 485         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 486                 return 0;
 487         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 488                 return 32;
 489         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 490         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 491                 return 0;
 492         }
 493         debug_printf("unknown shader param %d\n", param);
 494         return 0;
 495 }
 496
 497 static const void *
 498 fd_get_compiler_options(struct pipe_screen *pscreen,
 499                 enum pipe_shader_ir ir, unsigned shader)
 500 {
 501         struct fd_screen *screen = fd_screen(pscreen);
 502
 503         if (is_ir3(screen))
 504                 return ir3_get_compiler_options();
 505
 506         return NULL;
 507 }
 508
 509 boolean
 510 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 511                 struct fd_bo *bo,
 512                 unsigned stride,
 513                 struct winsys_handle *whandle)
 514 {
 515         whandle->stride = stride;
 516
 517         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 518                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 519         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 520                 whandle->handle = fd_bo_handle(bo);
 521                 return TRUE;
 522         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 523                 whandle->handle = fd_bo_dmabuf(bo);
 524                 return TRUE;
 525         } else {
 526                 return FALSE;
 527         }
 528 }
 529
 530 struct fd_bo *
 531 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 532                 struct winsys_handle *whandle,
 533                 unsigned *out_stride)
 534 {
 535         struct fd_screen *screen = fd_screen(pscreen);
 536         struct fd_bo *bo;
 537
 538         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 539                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 540         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 541                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 542         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 543                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 544         } else {
 545                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 546                 return NULL;
 547         }
 548
 549         if (!bo) {
 550                 DBG("ref name 0x%08x failed", whandle->handle);
 551                 return NULL;
 552         }
 553
 554         *out_stride = whandle->stride;
 555
 556         return bo;
 557 }
 558
 559 struct pipe_screen *
 560 fd_screen_create(struct fd_device *dev)
 561 {
 562         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 563         struct pipe_screen *pscreen;
 564         uint64_t val;
 565
 566         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 567
 568         if (fd_mesa_debug & FD_DBG_NOBIN)
 569                 fd_binning_enabled = false;
 570
 571         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 572
 573         if (!screen)
 574                 return NULL;
 575
 576         pscreen = &screen->base;
 577
 578         screen->dev = dev;
 579         screen->refcnt = 1;
 580
 581         // maybe this should be in context?
 582         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 583         if (!screen->pipe) {
 584                 DBG("could not create 3d pipe");
 585                 goto fail;
 586         }
 587
 588         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 589                 DBG("could not get GMEM size");
 590                 goto fail;
 591         }
 592         screen->gmemsize_bytes = val;
 593
 594         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 595                 DBG("could not get device-id");
 596                 goto fail;
 597         }
 598         screen->device_id = val;
 599
 600         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 601                 DBG("could not get gpu freq");
 602                 /* this limits what performance related queries are
 603                  * supported but is not fatal
 604                  */
 605                 screen->max_freq = 0;
 606         } else {
 607                 screen->max_freq = val;
 608                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 609                         screen->has_timestamp = true;
 610         }
 611
 612         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 613                 DBG("could not get gpu-id");
 614                 goto fail;
 615         }
 616         screen->gpu_id = val;
 617
 618         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 619                 DBG("could not get chip-id");
 620                 /* older kernels may not have this property: */
 621                 unsigned core  = screen->gpu_id / 100;
 622                 unsigned major = (screen->gpu_id % 100) / 10;
 623                 unsigned minor = screen->gpu_id % 10;
 624                 unsigned patch = 0;  /* assume the worst */
 625                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 626                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 627         }
 628         screen->chip_id = val;
 629
 630         DBG("Pipe Info:");
 631         DBG(" GPU-id:          %d", screen->gpu_id);
 632         DBG(" Chip-id:         0x%08x", screen->chip_id);
 633         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 634
 635         /* explicitly checking for GPU revisions that are known to work.  This
 636          * may be overly conservative for a3xx, where spoofing the gpu_id with
 637          * the blob driver seems to generate identical cmdstream dumps.  But
 638          * on a2xx, there seem to be small differences between the GPU revs
 639          * so it is probably better to actually test first on real hardware
 640          * before enabling:
 641          *
 642          * If you have a different adreno version, feel free to add it to one
 643          * of the cases below and see what happens.  And if it works, please
 644          * send a patch ;-)
 645          */
 646         switch (screen->gpu_id) {
 647         case 220:
 648                 fd2_screen_init(pscreen);
 649                 break;
 650         case 305:
 651         case 307:
 652         case 320:
 653         case 330:
 654                 fd3_screen_init(pscreen);
 655                 break;
 656         case 420:
 657         case 430:
 658                 fd4_screen_init(pscreen);
 659                 break;
 660         default:
 661                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 662                 goto fail;
 663         }
 664
 665         pscreen->destroy = fd_screen_destroy;
 666         pscreen->get_param = fd_screen_get_param;
 667         pscreen->get_paramf = fd_screen_get_paramf;
 668         pscreen->get_shader_param = fd_screen_get_shader_param;
 669         pscreen->get_compiler_options = fd_get_compiler_options;
 670
 671         fd_resource_screen_init(pscreen);
 672         fd_query_screen_init(pscreen);
 673
 674         pscreen->get_name = fd_screen_get_name;
 675         pscreen->get_vendor = fd_screen_get_vendor;
 676         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 677
 678         pscreen->get_timestamp = fd_screen_get_timestamp;
 679
 680         pscreen->fence_reference = fd_screen_fence_ref;
 681         pscreen->fence_finish = fd_screen_fence_finish;
 682
 683         util_format_s3tc_init();
 684
 685         return pscreen;
 686
 687 fail:
 688         fd_screen_destroy(pscreen);
 689         return NULL;
 690 }