src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55
  56 /* XXX this should go away */
  57 #include "state_tracker/drm_driver.h"
  58
  59 static const struct debug_named_value debug_options[] = {
  60                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  61                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  62                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  63                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  64                 {"dscis",     FD_DBG_DSCIS,  "Disable scissor optimization"},
  65                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  66                 {"dbypass",   FD_DBG_DBYPASS,"Disable GMEM bypass"},
  67                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  68                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  69                 {"noopt",     FD_DBG_NOOPT , "Disable optimization passes in compiler"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizater debug messages"},
  71                 {"optdump",   FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
  72                 {"glsl130",   FD_DBG_GLSL130,"Temporary flag to enable GLSL 130 on a3xx+"},
  73                 DEBUG_NAMED_VALUE_END
  74 };
  75
  76 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  77
  78 int fd_mesa_debug = 0;
  79 bool fd_binning_enabled = true;
  80 static bool glsl130 = false;
  81
  82 static const char *
  83 fd_screen_get_name(struct pipe_screen *pscreen)
  84 {
  85         static char buffer[128];
  86         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  87                         fd_screen(pscreen)->device_id);
  88         return buffer;
  89 }
  90
  91 static const char *
  92 fd_screen_get_vendor(struct pipe_screen *pscreen)
  93 {
  94         return "freedreno";
  95 }
  96
  97 static uint64_t
  98 fd_screen_get_timestamp(struct pipe_screen *pscreen)
  99 {
 100         int64_t cpu_time = os_time_get() * 1000;
 101         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 102 }
 103
 104 static void
 105 fd_screen_fence_ref(struct pipe_screen *pscreen,
 106                 struct pipe_fence_handle **ptr,
 107                 struct pipe_fence_handle *pfence)
 108 {
 109         fd_fence_ref(fd_fence(pfence), (struct fd_fence **)ptr);
 110 }
 111
 112 static boolean
 113 fd_screen_fence_signalled(struct pipe_screen *screen,
 114                 struct pipe_fence_handle *pfence)
 115 {
 116         return fd_fence_signalled(fd_fence(pfence));
 117 }
 118
 119 static boolean
 120 fd_screen_fence_finish(struct pipe_screen *screen,
 121                 struct pipe_fence_handle *pfence,
 122                 uint64_t timeout)
 123 {
 124         return fd_fence_wait(fd_fence(pfence));
 125 }
 126
 127 static void
 128 fd_screen_destroy(struct pipe_screen *pscreen)
 129 {
 130         struct fd_screen *screen = fd_screen(pscreen);
 131
 132         if (screen->pipe)
 133                 fd_pipe_del(screen->pipe);
 134
 135         if (screen->dev)
 136                 fd_device_del(screen->dev);
 137
 138         free(screen);
 139 }
 140
 141 /*
 142 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 143 tables for things that differ if the delta is not too much..
 144  */
 145 static int
 146 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 147 {
 148         struct fd_screen *screen = fd_screen(pscreen);
 149
 150         /* this is probably not totally correct.. but it's a start: */
 151         switch (param) {
 152         /* Supported features (boolean caps). */
 153         case PIPE_CAP_NPOT_TEXTURES:
 154         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 155         case PIPE_CAP_TWO_SIDED_STENCIL:
 156         case PIPE_CAP_ANISOTROPIC_FILTER:
 157         case PIPE_CAP_POINT_SPRITE:
 158         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 159         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 160         case PIPE_CAP_TEXTURE_SWIZZLE:
 161         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 162         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 163         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 164         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 165         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 166         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 167         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 168         case PIPE_CAP_TGSI_INSTANCEID:
 169         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 170         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 171         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 172         case PIPE_CAP_COMPUTE:
 173         case PIPE_CAP_START_INSTANCE:
 174         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 175         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 176         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 177                 return 1;
 178
 179         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 180         case PIPE_CAP_TGSI_TEXCOORD:
 181         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 182         case PIPE_CAP_CONDITIONAL_RENDER:
 183         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 184         case PIPE_CAP_TEXTURE_BARRIER:
 185         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 186         case PIPE_CAP_SM3:
 187                 return 0;
 188
 189         case PIPE_CAP_PRIMITIVE_RESTART:
 190                 return (screen->gpu_id >= 300) ? 1 : 0;
 191
 192         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 193                 return 256;
 194
 195         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 196                 return ((screen->gpu_id >= 300) && glsl130) ? 130 : 120;
 197
 198         /* Unsupported features. */
 199         case PIPE_CAP_INDEP_BLEND_ENABLE:
 200         case PIPE_CAP_INDEP_BLEND_FUNC:
 201         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 202         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 203         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 204         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 205         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 206         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 207         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 208         case PIPE_CAP_USER_VERTEX_BUFFERS:
 209         case PIPE_CAP_USER_INDEX_BUFFERS:
 210         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 211         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 212         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 213         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 214         case PIPE_CAP_TEXTURE_GATHER_SM5:
 215         case PIPE_CAP_FAKE_SW_MSAA:
 216         case PIPE_CAP_TEXTURE_QUERY_LOD:
 217         case PIPE_CAP_SAMPLE_SHADING:
 218         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 219         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 220         case PIPE_CAP_DRAW_INDIRECT:
 221         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 222         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 223         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 224                 return 0;
 225
 226         /* Stream output. */
 227         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 228         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 229         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 230         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 231                 return 0;
 232
 233         /* Geometry shader output, unsupported. */
 234         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 235         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 236         case PIPE_CAP_MAX_VERTEX_STREAMS:
 237                 return 0;
 238
 239         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 240                 return 2048;
 241
 242         /* Texturing. */
 243         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 244         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 245                 return MAX_MIP_LEVELS;
 246         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 247                 return 11;
 248
 249         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 250                 return (screen->gpu_id >= 300) ? 256 : 0;
 251
 252         /* Render targets. */
 253         case PIPE_CAP_MAX_RENDER_TARGETS:
 254                 return 1;
 255
 256         /* Queries. */
 257         case PIPE_CAP_QUERY_TIME_ELAPSED:
 258         case PIPE_CAP_QUERY_TIMESTAMP:
 259                 return 0;
 260         case PIPE_CAP_OCCLUSION_QUERY:
 261                 return (screen->gpu_id >= 300) ? 1 : 0;
 262
 263         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 264         case PIPE_CAP_MIN_TEXEL_OFFSET:
 265                 return -8;
 266
 267         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 268         case PIPE_CAP_MAX_TEXEL_OFFSET:
 269                 return 7;
 270
 271         case PIPE_CAP_ENDIANNESS:
 272                 return PIPE_ENDIAN_LITTLE;
 273
 274         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 275                 return 64;
 276
 277         case PIPE_CAP_VENDOR_ID:
 278                 return 0x5143;
 279         case PIPE_CAP_DEVICE_ID:
 280                 return 0xFFFFFFFF;
 281         case PIPE_CAP_ACCELERATED:
 282                 return 1;
 283         case PIPE_CAP_VIDEO_MEMORY:
 284                 DBG("FINISHME: The value returned is incorrect\n");
 285                 return 10;
 286         case PIPE_CAP_UMA:
 287                 return 1;
 288
 289         default:
 290                 DBG("unknown param %d", param);
 291                 return 0;
 292         }
 293 }
 294
 295 static float
 296 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 297 {
 298         switch (param) {
 299         case PIPE_CAPF_MAX_LINE_WIDTH:
 300         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 301         case PIPE_CAPF_MAX_POINT_WIDTH:
 302         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 303                 return 8192.0f;
 304         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 305                 return 16.0f;
 306         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 307                 return 16.0f;
 308         case PIPE_CAPF_GUARD_BAND_LEFT:
 309         case PIPE_CAPF_GUARD_BAND_TOP:
 310         case PIPE_CAPF_GUARD_BAND_RIGHT:
 311         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 312                 return 0.0f;
 313         default:
 314                 DBG("unknown paramf %d", param);
 315                 return 0;
 316         }
 317 }
 318
 319 static int
 320 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 321                 enum pipe_shader_cap param)
 322 {
 323         struct fd_screen *screen = fd_screen(pscreen);
 324
 325         switch(shader)
 326         {
 327         case PIPE_SHADER_FRAGMENT:
 328         case PIPE_SHADER_VERTEX:
 329                 break;
 330         case PIPE_SHADER_COMPUTE:
 331         case PIPE_SHADER_GEOMETRY:
 332                 /* maye we could emulate.. */
 333                 return 0;
 334         default:
 335                 DBG("unknown shader type %d", shader);
 336                 return 0;
 337         }
 338
 339         /* this is probably not totally correct.. but it's a start: */
 340         switch (param) {
 341         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 342         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 343         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 344         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 345                 return 16384;
 346         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 347                 return 8; /* XXX */
 348         case PIPE_SHADER_CAP_MAX_INPUTS:
 349                 return 16;
 350         case PIPE_SHADER_CAP_MAX_TEMPS:
 351                 return 64; /* Max native temporaries. */
 352         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 353                 return ((screen->gpu_id >= 300) ? 1024 : 64) * sizeof(float[4]);
 354         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 355                 return 1;
 356         case PIPE_SHADER_CAP_MAX_PREDS:
 357                 return 0; /* nothing uses this */
 358         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 359                 return 1;
 360         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 361         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 362         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 363         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 364                 return 1;
 365         case PIPE_SHADER_CAP_SUBROUTINES:
 366                 return 0;
 367         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 368                 return 1;
 369         case PIPE_SHADER_CAP_INTEGERS:
 370                 /* we should be able to support this on a3xx, but not
 371                  * implemented yet:
 372                  */
 373                 return ((screen->gpu_id >= 300) && glsl130) ? 1 : 0;
 374         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 375         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 376                 return 16;
 377         case PIPE_SHADER_CAP_PREFERRED_IR:
 378                 return PIPE_SHADER_IR_TGSI;
 379         default:
 380                 DBG("unknown shader param %d", param);
 381                 return 0;
 382         }
 383         return 0;
 384 }
 385
 386 boolean
 387 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 388                 struct fd_bo *bo,
 389                 unsigned stride,
 390                 struct winsys_handle *whandle)
 391 {
 392         whandle->stride = stride;
 393
 394         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 395                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 396         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 397                 whandle->handle = fd_bo_handle(bo);
 398                 return TRUE;
 399         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 400                 whandle->handle = fd_bo_dmabuf(bo);
 401                 return TRUE;
 402         } else {
 403                 return FALSE;
 404         }
 405 }
 406
 407 struct fd_bo *
 408 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 409                 struct winsys_handle *whandle,
 410                 unsigned *out_stride)
 411 {
 412         struct fd_screen *screen = fd_screen(pscreen);
 413         struct fd_bo *bo;
 414
 415         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 416                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 417         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 418                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 419         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 420                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 421         } else {
 422                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 423                 return NULL;
 424         }
 425
 426         if (!bo) {
 427                 DBG("ref name 0x%08x failed", whandle->handle);
 428                 return NULL;
 429         }
 430
 431         *out_stride = whandle->stride;
 432
 433         return bo;
 434 }
 435
 436 struct pipe_screen *
 437 fd_screen_create(struct fd_device *dev)
 438 {
 439         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 440         struct pipe_screen *pscreen;
 441         uint64_t val;
 442
 443         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 444
 445         if (fd_mesa_debug & FD_DBG_NOBIN)
 446                 fd_binning_enabled = false;
 447
 448         glsl130 = !!(fd_mesa_debug & FD_DBG_GLSL130);
 449
 450         if (!screen)
 451                 return NULL;
 452
 453         pscreen = &screen->base;
 454
 455         screen->dev = dev;
 456
 457         // maybe this should be in context?
 458         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 459         if (!screen->pipe) {
 460                 DBG("could not create 3d pipe");
 461                 goto fail;
 462         }
 463
 464         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 465                 DBG("could not get GMEM size");
 466                 goto fail;
 467         }
 468         screen->gmemsize_bytes = val;
 469
 470         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 471                 DBG("could not get device-id");
 472                 goto fail;
 473         }
 474         screen->device_id = val;
 475
 476         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 477                 DBG("could not get gpu-id");
 478                 goto fail;
 479         }
 480         screen->gpu_id = val;
 481
 482         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 483                 DBG("could not get chip-id");
 484                 /* older kernels may not have this property: */
 485                 unsigned core  = screen->gpu_id / 100;
 486                 unsigned major = (screen->gpu_id % 100) / 10;
 487                 unsigned minor = screen->gpu_id % 10;
 488                 unsigned patch = 0;  /* assume the worst */
 489                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 490                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 491         }
 492         screen->chip_id = val;
 493
 494         DBG("Pipe Info:");
 495         DBG(" GPU-id:          %d", screen->gpu_id);
 496         DBG(" Chip-id:         0x%08x", screen->chip_id);
 497         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 498
 499         /* explicitly checking for GPU revisions that are known to work.  This
 500          * may be overly conservative for a3xx, where spoofing the gpu_id with
 501          * the blob driver seems to generate identical cmdstream dumps.  But
 502          * on a2xx, there seem to be small differences between the GPU revs
 503          * so it is probably better to actually test first on real hardware
 504          * before enabling:
 505          *
 506          * If you have a different adreno version, feel free to add it to one
 507          * of the two cases below and see what happens.  And if it works, please
 508          * send a patch ;-)
 509          */
 510         switch (screen->gpu_id) {
 511         case 220:
 512                 fd2_screen_init(pscreen);
 513                 break;
 514         case 320:
 515         case 330:
 516                 fd3_screen_init(pscreen);
 517                 break;
 518         default:
 519                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 520                 goto fail;
 521         }
 522
 523         pscreen->destroy = fd_screen_destroy;
 524         pscreen->get_param = fd_screen_get_param;
 525         pscreen->get_paramf = fd_screen_get_paramf;
 526         pscreen->get_shader_param = fd_screen_get_shader_param;
 527
 528         fd_resource_screen_init(pscreen);
 529         fd_query_screen_init(pscreen);
 530
 531         pscreen->get_name = fd_screen_get_name;
 532         pscreen->get_vendor = fd_screen_get_vendor;
 533
 534         pscreen->get_timestamp = fd_screen_get_timestamp;
 535
 536         pscreen->fence_reference = fd_screen_fence_ref;
 537         pscreen->fence_signalled = fd_screen_fence_signalled;
 538         pscreen->fence_finish = fd_screen_fence_finish;
 539
 540         util_format_s3tc_init();
 541
 542         return pscreen;
 543
 544 fail:
 545         fd_screen_destroy(pscreen);
 546         return NULL;
 547 }