src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 /* XXX this should go away */
  58 #include "state_tracker/drm_driver.h"
  59
  60 static const struct debug_named_value debug_options[] = {
  61                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  62                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  63                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  64                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  65                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  66                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  67                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  68                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  69                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  71                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  72                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  73                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  74                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  75                 DEBUG_NAMED_VALUE_END
  76 };
  77
  78 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  79
  80 int fd_mesa_debug = 0;
  81 bool fd_binning_enabled = true;
  82 static bool glsl120 = false;
  83
  84 static const char *
  85 fd_screen_get_name(struct pipe_screen *pscreen)
  86 {
  87         static char buffer[128];
  88         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  89                         fd_screen(pscreen)->device_id);
  90         return buffer;
  91 }
  92
  93 static const char *
  94 fd_screen_get_vendor(struct pipe_screen *pscreen)
  95 {
  96         return "freedreno";
  97 }
  98
  99 static const char *
 100 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 101 {
 102         return "Qualcomm";
 103 }
 104
 105
 106 static uint64_t
 107 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 108 {
 109         int64_t cpu_time = os_time_get() * 1000;
 110         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 111 }
 112
 113 static void
 114 fd_screen_destroy(struct pipe_screen *pscreen)
 115 {
 116         struct fd_screen *screen = fd_screen(pscreen);
 117
 118         if (screen->pipe)
 119                 fd_pipe_del(screen->pipe);
 120
 121         if (screen->dev)
 122                 fd_device_del(screen->dev);
 123
 124         free(screen);
 125 }
 126
 127 /*
 128 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 129 tables for things that differ if the delta is not too much..
 130  */
 131 static int
 132 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 133 {
 134         struct fd_screen *screen = fd_screen(pscreen);
 135
 136         /* this is probably not totally correct.. but it's a start: */
 137         switch (param) {
 138         /* Supported features (boolean caps). */
 139         case PIPE_CAP_NPOT_TEXTURES:
 140         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 141         case PIPE_CAP_TWO_SIDED_STENCIL:
 142         case PIPE_CAP_ANISOTROPIC_FILTER:
 143         case PIPE_CAP_POINT_SPRITE:
 144         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 145         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 146         case PIPE_CAP_TEXTURE_SWIZZLE:
 147         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 148         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 149         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 150         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 151         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 152         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 153         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 154         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 155         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 156         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 157         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 158         case PIPE_CAP_VERTEXID_NOBASE:
 159         case PIPE_CAP_STRING_MARKER:
 160                 return 1;
 161
 162         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 163         case PIPE_CAP_TGSI_TEXCOORD:
 164         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 165         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 166         case PIPE_CAP_TEXTURE_BARRIER:
 167         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 168         case PIPE_CAP_COMPUTE:
 169         case PIPE_CAP_QUERY_MEMORY_INFO:
 170         case PIPE_CAP_PCI_GROUP:
 171         case PIPE_CAP_PCI_BUS:
 172         case PIPE_CAP_PCI_DEVICE:
 173         case PIPE_CAP_PCI_FUNCTION:
 174                 return 0;
 175
 176         case PIPE_CAP_SM3:
 177         case PIPE_CAP_PRIMITIVE_RESTART:
 178         case PIPE_CAP_TGSI_INSTANCEID:
 179         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 180         case PIPE_CAP_INDEP_BLEND_ENABLE:
 181         case PIPE_CAP_INDEP_BLEND_FUNC:
 182         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 183         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 184         case PIPE_CAP_CONDITIONAL_RENDER:
 185         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 186         case PIPE_CAP_FAKE_SW_MSAA:
 187         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 188         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 189         case PIPE_CAP_CLIP_HALFZ:
 190                 return is_a3xx(screen) || is_a4xx(screen);
 191
 192         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 193                 return 0;
 194         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 195                 if (is_a3xx(screen)) return 16;
 196                 if (is_a4xx(screen)) return 32;
 197                 return 0;
 198         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 199                 /* We could possibly emulate more by pretending 2d/rect textures and
 200                  * splitting high bits of index into 2nd dimension..
 201                  */
 202                 if (is_a3xx(screen)) return 8192;
 203                 if (is_a4xx(screen)) return 16384;
 204                 return 0;
 205
 206         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 207         case PIPE_CAP_CUBE_MAP_ARRAY:
 208         case PIPE_CAP_START_INSTANCE:
 209         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 210         case PIPE_CAP_TEXTURE_QUERY_LOD:
 211                 return is_a4xx(screen);
 212
 213         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 214                 return 256;
 215
 216         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 217                 if (glsl120)
 218                         return 120;
 219                 return is_ir3(screen) ? 140 : 120;
 220
 221         /* Unsupported features. */
 222         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 223         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 224         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 225         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 226         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 227         case PIPE_CAP_USER_VERTEX_BUFFERS:
 228         case PIPE_CAP_USER_INDEX_BUFFERS:
 229         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 230         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 231         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 232         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 233         case PIPE_CAP_TEXTURE_GATHER_SM5:
 234         case PIPE_CAP_SAMPLE_SHADING:
 235         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 236         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 237         case PIPE_CAP_DRAW_INDIRECT:
 238         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 239         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 240         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 241         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 242         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 243         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 244         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 245         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 246         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 247         case PIPE_CAP_TGSI_TXQS:
 248         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 249         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 250         case PIPE_CAP_CLEAR_TEXTURE:
 251         case PIPE_CAP_DRAW_PARAMETERS:
 252         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 253         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 254         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 255         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 256         case PIPE_CAP_INVALIDATE_BUFFER:
 257         case PIPE_CAP_GENERATE_MIPMAP:
 258         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 259         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 260         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 261                 return 0;
 262
 263         case PIPE_CAP_MAX_VIEWPORTS:
 264                 return 1;
 265
 266         case PIPE_CAP_SHAREABLE_SHADERS:
 267                 if (is_ir3(screen))
 268                         return 1;
 269                 return 0;
 270
 271         /* Stream output. */
 272         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 273                 if (is_ir3(screen))
 274                         return PIPE_MAX_SO_BUFFERS;
 275                 return 0;
 276         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 277                 if (is_ir3(screen))
 278                         return 1;
 279                 return 0;
 280         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 281         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 282                 if (is_ir3(screen))
 283                         return 16 * 4;   /* should only be shader out limit? */
 284                 return 0;
 285
 286         /* Geometry shader output, unsupported. */
 287         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 288         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 289         case PIPE_CAP_MAX_VERTEX_STREAMS:
 290                 return 0;
 291
 292         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 293                 return 2048;
 294
 295         /* Texturing. */
 296         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 297         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 298                 return MAX_MIP_LEVELS;
 299         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 300                 return 11;
 301
 302         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 303                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 304
 305         /* Render targets. */
 306         case PIPE_CAP_MAX_RENDER_TARGETS:
 307                 return screen->max_rts;
 308         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 309                 return is_a3xx(screen) ? 1 : 0;
 310
 311         /* Queries. */
 312         case PIPE_CAP_QUERY_TIMESTAMP:
 313         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 314                 return 0;
 315         case PIPE_CAP_OCCLUSION_QUERY:
 316                 return is_a3xx(screen) || is_a4xx(screen);
 317         case PIPE_CAP_QUERY_TIME_ELAPSED:
 318                 /* only a4xx, requires new enough kernel so we know max_freq: */
 319                 return (screen->max_freq > 0) && is_a4xx(screen);
 320
 321         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 322         case PIPE_CAP_MIN_TEXEL_OFFSET:
 323                 return -8;
 324
 325         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 326         case PIPE_CAP_MAX_TEXEL_OFFSET:
 327                 return 7;
 328
 329         case PIPE_CAP_ENDIANNESS:
 330                 return PIPE_ENDIAN_LITTLE;
 331
 332         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 333                 return 64;
 334
 335         case PIPE_CAP_VENDOR_ID:
 336                 return 0x5143;
 337         case PIPE_CAP_DEVICE_ID:
 338                 return 0xFFFFFFFF;
 339         case PIPE_CAP_ACCELERATED:
 340                 return 1;
 341         case PIPE_CAP_VIDEO_MEMORY:
 342                 DBG("FINISHME: The value returned is incorrect\n");
 343                 return 10;
 344         case PIPE_CAP_UMA:
 345                 return 1;
 346         }
 347         debug_printf("unknown param %d\n", param);
 348         return 0;
 349 }
 350
 351 static float
 352 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 353 {
 354         switch (param) {
 355         case PIPE_CAPF_MAX_LINE_WIDTH:
 356         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 357         case PIPE_CAPF_MAX_POINT_WIDTH:
 358         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 359                 return 4092.0f;
 360         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 361                 return 16.0f;
 362         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 363                 return 15.0f;
 364         case PIPE_CAPF_GUARD_BAND_LEFT:
 365         case PIPE_CAPF_GUARD_BAND_TOP:
 366         case PIPE_CAPF_GUARD_BAND_RIGHT:
 367         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 368                 return 0.0f;
 369         }
 370         debug_printf("unknown paramf %d\n", param);
 371         return 0;
 372 }
 373
 374 static int
 375 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 376                 enum pipe_shader_cap param)
 377 {
 378         struct fd_screen *screen = fd_screen(pscreen);
 379
 380         switch(shader)
 381         {
 382         case PIPE_SHADER_FRAGMENT:
 383         case PIPE_SHADER_VERTEX:
 384                 break;
 385         case PIPE_SHADER_COMPUTE:
 386         case PIPE_SHADER_GEOMETRY:
 387                 /* maye we could emulate.. */
 388                 return 0;
 389         default:
 390                 DBG("unknown shader type %d", shader);
 391                 return 0;
 392         }
 393
 394         /* this is probably not totally correct.. but it's a start: */
 395         switch (param) {
 396         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 397         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 398         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 399         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 400                 return 16384;
 401         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 402                 return 8; /* XXX */
 403         case PIPE_SHADER_CAP_MAX_INPUTS:
 404         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 405                 return 16;
 406         case PIPE_SHADER_CAP_MAX_TEMPS:
 407                 return 64; /* Max native temporaries. */
 408         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 409                 /* NOTE: seems to be limit for a3xx is actually 512 but
 410                  * split between VS and FS.  Use lower limit of 256 to
 411                  * avoid getting into impossible situations:
 412                  */
 413                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 414         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 415                 return is_ir3(screen) ? 16 : 1;
 416         case PIPE_SHADER_CAP_MAX_PREDS:
 417                 return 0; /* nothing uses this */
 418         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 419                 return 1;
 420         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 421         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 422                 /* Technically this should be the same as for TEMP/CONST, since
 423                  * everything is just normal registers.  This is just temporary
 424                  * hack until load_input/store_output handle arrays in a similar
 425                  * way as load_var/store_var..
 426                  */
 427                 return 0;
 428         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 429         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 430                 /* a2xx compiler doesn't handle indirect: */
 431                 return is_ir3(screen) ? 1 : 0;
 432         case PIPE_SHADER_CAP_SUBROUTINES:
 433         case PIPE_SHADER_CAP_DOUBLES:
 434         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 435         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 436         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 437         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 438                 return 0;
 439         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 440                 return 1;
 441         case PIPE_SHADER_CAP_INTEGERS:
 442                 if (glsl120)
 443                         return 0;
 444                 return is_ir3(screen) ? 1 : 0;
 445         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 446         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 447                 return 16;
 448         case PIPE_SHADER_CAP_PREFERRED_IR:
 449                 return PIPE_SHADER_IR_TGSI;
 450         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 451                 return 0;
 452         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 453                 return 32;
 454         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 455         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 456                 return 0;
 457         }
 458         debug_printf("unknown shader param %d\n", param);
 459         return 0;
 460 }
 461
 462 boolean
 463 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 464                 struct fd_bo *bo,
 465                 unsigned stride,
 466                 struct winsys_handle *whandle)
 467 {
 468         whandle->stride = stride;
 469
 470         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 471                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 472         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 473                 whandle->handle = fd_bo_handle(bo);
 474                 return TRUE;
 475         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 476                 whandle->handle = fd_bo_dmabuf(bo);
 477                 return TRUE;
 478         } else {
 479                 return FALSE;
 480         }
 481 }
 482
 483 struct fd_bo *
 484 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 485                 struct winsys_handle *whandle,
 486                 unsigned *out_stride)
 487 {
 488         struct fd_screen *screen = fd_screen(pscreen);
 489         struct fd_bo *bo;
 490
 491         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 492                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 493         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 494                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 495         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 496                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 497         } else {
 498                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 499                 return NULL;
 500         }
 501
 502         if (!bo) {
 503                 DBG("ref name 0x%08x failed", whandle->handle);
 504                 return NULL;
 505         }
 506
 507         *out_stride = whandle->stride;
 508
 509         return bo;
 510 }
 511
 512 struct pipe_screen *
 513 fd_screen_create(struct fd_device *dev)
 514 {
 515         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 516         struct pipe_screen *pscreen;
 517         uint64_t val;
 518
 519         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 520
 521         if (fd_mesa_debug & FD_DBG_NOBIN)
 522                 fd_binning_enabled = false;
 523
 524         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 525
 526         if (!screen)
 527                 return NULL;
 528
 529         pscreen = &screen->base;
 530
 531         screen->dev = dev;
 532         screen->refcnt = 1;
 533
 534         // maybe this should be in context?
 535         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 536         if (!screen->pipe) {
 537                 DBG("could not create 3d pipe");
 538                 goto fail;
 539         }
 540
 541         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 542                 DBG("could not get GMEM size");
 543                 goto fail;
 544         }
 545         screen->gmemsize_bytes = val;
 546
 547         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 548                 DBG("could not get device-id");
 549                 goto fail;
 550         }
 551         screen->device_id = val;
 552
 553         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 554                 DBG("could not get gpu freq");
 555                 /* this limits what performance related queries are
 556                  * supported but is not fatal
 557                  */
 558                 screen->max_freq = 0;
 559         } else {
 560                 screen->max_freq = val;
 561         }
 562
 563         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 564                 DBG("could not get gpu-id");
 565                 goto fail;
 566         }
 567         screen->gpu_id = val;
 568
 569         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 570                 DBG("could not get chip-id");
 571                 /* older kernels may not have this property: */
 572                 unsigned core  = screen->gpu_id / 100;
 573                 unsigned major = (screen->gpu_id % 100) / 10;
 574                 unsigned minor = screen->gpu_id % 10;
 575                 unsigned patch = 0;  /* assume the worst */
 576                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 577                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 578         }
 579         screen->chip_id = val;
 580
 581         DBG("Pipe Info:");
 582         DBG(" GPU-id:          %d", screen->gpu_id);
 583         DBG(" Chip-id:         0x%08x", screen->chip_id);
 584         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 585
 586         /* explicitly checking for GPU revisions that are known to work.  This
 587          * may be overly conservative for a3xx, where spoofing the gpu_id with
 588          * the blob driver seems to generate identical cmdstream dumps.  But
 589          * on a2xx, there seem to be small differences between the GPU revs
 590          * so it is probably better to actually test first on real hardware
 591          * before enabling:
 592          *
 593          * If you have a different adreno version, feel free to add it to one
 594          * of the cases below and see what happens.  And if it works, please
 595          * send a patch ;-)
 596          */
 597         switch (screen->gpu_id) {
 598         case 220:
 599                 fd2_screen_init(pscreen);
 600                 break;
 601         case 305:
 602         case 307:
 603         case 320:
 604         case 330:
 605                 fd3_screen_init(pscreen);
 606                 break;
 607         case 420:
 608         case 430:
 609                 fd4_screen_init(pscreen);
 610                 break;
 611         default:
 612                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 613                 goto fail;
 614         }
 615
 616         pscreen->destroy = fd_screen_destroy;
 617         pscreen->get_param = fd_screen_get_param;
 618         pscreen->get_paramf = fd_screen_get_paramf;
 619         pscreen->get_shader_param = fd_screen_get_shader_param;
 620
 621         fd_resource_screen_init(pscreen);
 622         fd_query_screen_init(pscreen);
 623
 624         pscreen->get_name = fd_screen_get_name;
 625         pscreen->get_vendor = fd_screen_get_vendor;
 626         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 627
 628         pscreen->get_timestamp = fd_screen_get_timestamp;
 629
 630         pscreen->fence_reference = fd_screen_fence_ref;
 631         pscreen->fence_finish = fd_screen_fence_finish;
 632
 633         util_format_s3tc_init();
 634
 635         return pscreen;
 636
 637 fail:
 638         fd_screen_destroy(pscreen);
 639         return NULL;
 640 }