1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
41 #include "os/os_time.h"
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
58 #include "ir3/ir3_nir.h"
60 /* XXX this should go away */
61 #include "state_tracker/drm_driver.h"
63 static const struct debug_named_value debug_options
[] = {
64 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
65 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
66 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
67 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
68 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
69 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
70 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
71 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
72 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
73 {"optmsgs", FD_DBG_OPTMSGS
,"Enable optimizer debug messages"},
74 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
75 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
76 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
77 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
78 {"nir", FD_DBG_NIR
, "Prefer NIR as native IR"},
79 {"reorder", FD_DBG_REORDER
,"Enable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
87 int fd_mesa_debug
= 0;
88 bool fd_binning_enabled
= true;
89 static bool glsl120
= false;
92 fd_screen_get_name(struct pipe_screen
*pscreen
)
94 static char buffer
[128];
95 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
96 fd_screen(pscreen
)->device_id
);
101 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
107 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
114 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
116 struct fd_screen
*screen
= fd_screen(pscreen
);
118 if (screen
->has_timestamp
) {
120 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
121 debug_assert(screen
->max_freq
> 0);
122 return n
* 1000000000 / screen
->max_freq
;
124 int64_t cpu_time
= os_time_get() * 1000;
125 return cpu_time
+ screen
->cpu_gpu_time_delta
;
131 fd_screen_destroy(struct pipe_screen
*pscreen
)
133 struct fd_screen
*screen
= fd_screen(pscreen
);
136 fd_pipe_del(screen
->pipe
);
139 fd_device_del(screen
->dev
);
141 fd_bc_fini(&screen
->batch_cache
);
143 slab_destroy_parent(&screen
->transfer_pool
);
145 pipe_mutex_destroy(screen
->lock
);
151 TODO either move caps to a2xx/a3xx specific code, or maybe have some
152 tables for things that differ if the delta is not too much..
155 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
157 struct fd_screen
*screen
= fd_screen(pscreen
);
159 /* this is probably not totally correct.. but it's a start: */
161 /* Supported features (boolean caps). */
162 case PIPE_CAP_NPOT_TEXTURES
:
163 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
164 case PIPE_CAP_TWO_SIDED_STENCIL
:
165 case PIPE_CAP_ANISOTROPIC_FILTER
:
166 case PIPE_CAP_POINT_SPRITE
:
167 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
168 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
169 case PIPE_CAP_TEXTURE_SWIZZLE
:
170 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
171 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
172 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
173 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
174 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
175 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
176 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
177 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
178 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
179 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
180 case PIPE_CAP_STRING_MARKER
:
181 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
184 case PIPE_CAP_VERTEXID_NOBASE
:
185 return is_a3xx(screen
) || is_a4xx(screen
);
187 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
188 return is_a4xx(screen
) ? 0 : 1;
190 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
191 case PIPE_CAP_TGSI_TEXCOORD
:
192 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
193 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
194 case PIPE_CAP_TEXTURE_BARRIER
:
195 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
196 case PIPE_CAP_COMPUTE
:
197 case PIPE_CAP_QUERY_MEMORY_INFO
:
198 case PIPE_CAP_PCI_GROUP
:
199 case PIPE_CAP_PCI_BUS
:
200 case PIPE_CAP_PCI_DEVICE
:
201 case PIPE_CAP_PCI_FUNCTION
:
205 case PIPE_CAP_PRIMITIVE_RESTART
:
206 case PIPE_CAP_TGSI_INSTANCEID
:
207 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
208 case PIPE_CAP_INDEP_BLEND_ENABLE
:
209 case PIPE_CAP_INDEP_BLEND_FUNC
:
210 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
211 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
212 case PIPE_CAP_CONDITIONAL_RENDER
:
213 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
214 case PIPE_CAP_FAKE_SW_MSAA
:
215 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
216 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
217 case PIPE_CAP_CLIP_HALFZ
:
218 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
);
220 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
222 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
223 if (is_a3xx(screen
)) return 16;
224 if (is_a4xx(screen
)) return 32;
225 if (is_a5xx(screen
)) return 32;
227 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
228 /* We could possibly emulate more by pretending 2d/rect textures and
229 * splitting high bits of index into 2nd dimension..
231 if (is_a3xx(screen
)) return 8192;
232 if (is_a4xx(screen
)) return 16384;
233 if (is_a5xx(screen
)) return 16384;
236 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
237 case PIPE_CAP_CUBE_MAP_ARRAY
:
238 case PIPE_CAP_START_INSTANCE
:
239 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
240 case PIPE_CAP_TEXTURE_QUERY_LOD
:
241 return is_a4xx(screen
) || is_a5xx(screen
);
243 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
246 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
249 return is_ir3(screen
) ? 140 : 120;
251 /* Unsupported features. */
252 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
254 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
255 case PIPE_CAP_USER_VERTEX_BUFFERS
:
256 case PIPE_CAP_USER_INDEX_BUFFERS
:
257 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
258 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
259 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
260 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
261 case PIPE_CAP_TEXTURE_GATHER_SM5
:
262 case PIPE_CAP_SAMPLE_SHADING
:
263 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
264 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
265 case PIPE_CAP_DRAW_INDIRECT
:
266 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
267 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
268 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
269 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
270 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
271 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
272 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
273 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
274 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
275 case PIPE_CAP_TGSI_TXQS
:
276 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
277 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
278 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
279 case PIPE_CAP_CLEAR_TEXTURE
:
280 case PIPE_CAP_DRAW_PARAMETERS
:
281 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
282 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
283 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
284 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
285 case PIPE_CAP_INVALIDATE_BUFFER
:
286 case PIPE_CAP_GENERATE_MIPMAP
:
287 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
288 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
289 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
290 case PIPE_CAP_CULL_DISTANCE
:
291 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
292 case PIPE_CAP_TGSI_VOTE
:
293 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
294 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
295 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
296 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
297 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
298 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
299 case PIPE_CAP_TGSI_FS_FBFETCH
:
300 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
303 case PIPE_CAP_MAX_VIEWPORTS
:
306 case PIPE_CAP_SHAREABLE_SHADERS
:
307 /* manage the variants for these ourself, to avoid breaking precompile: */
308 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
309 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
315 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
317 return PIPE_MAX_SO_BUFFERS
;
319 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
320 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
324 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
325 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
327 return 16 * 4; /* should only be shader out limit? */
330 /* Geometry shader output, unsupported. */
331 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
332 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
333 case PIPE_CAP_MAX_VERTEX_STREAMS
:
336 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
340 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
341 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
342 return MAX_MIP_LEVELS
;
343 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
346 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
347 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
)) ? 256 : 0;
349 /* Render targets. */
350 case PIPE_CAP_MAX_RENDER_TARGETS
:
351 return screen
->max_rts
;
352 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
353 return is_a3xx(screen
) ? 1 : 0;
356 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
358 case PIPE_CAP_OCCLUSION_QUERY
:
359 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
);
360 case PIPE_CAP_QUERY_TIMESTAMP
:
361 case PIPE_CAP_QUERY_TIME_ELAPSED
:
362 /* only a4xx, requires new enough kernel so we know max_freq: */
363 return (screen
->max_freq
> 0) && is_a4xx(screen
);
365 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
366 case PIPE_CAP_MIN_TEXEL_OFFSET
:
369 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
370 case PIPE_CAP_MAX_TEXEL_OFFSET
:
373 case PIPE_CAP_ENDIANNESS
:
374 return PIPE_ENDIAN_LITTLE
;
376 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
379 case PIPE_CAP_VENDOR_ID
:
381 case PIPE_CAP_DEVICE_ID
:
383 case PIPE_CAP_ACCELERATED
:
385 case PIPE_CAP_VIDEO_MEMORY
:
386 DBG("FINISHME: The value returned is incorrect\n");
390 case PIPE_CAP_NATIVE_FENCE_FD
:
391 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
393 debug_printf("unknown param %d\n", param
);
398 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
401 case PIPE_CAPF_MAX_LINE_WIDTH
:
402 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
403 /* NOTE: actual value is 127.0f, but this is working around a deqp
404 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
405 * uses too small of a render target size, and gets confused when
406 * the lines start going offscreen.
408 * See: https://code.google.com/p/android/issues/detail?id=206513
410 if (fd_mesa_debug
& FD_DBG_DEQP
)
413 case PIPE_CAPF_MAX_POINT_WIDTH
:
414 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
416 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
418 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
420 case PIPE_CAPF_GUARD_BAND_LEFT
:
421 case PIPE_CAPF_GUARD_BAND_TOP
:
422 case PIPE_CAPF_GUARD_BAND_RIGHT
:
423 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
426 debug_printf("unknown paramf %d\n", param
);
431 fd_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
432 enum pipe_shader_cap param
)
434 struct fd_screen
*screen
= fd_screen(pscreen
);
438 case PIPE_SHADER_FRAGMENT
:
439 case PIPE_SHADER_VERTEX
:
441 case PIPE_SHADER_COMPUTE
:
442 case PIPE_SHADER_GEOMETRY
:
443 /* maye we could emulate.. */
446 DBG("unknown shader type %d", shader
);
450 /* this is probably not totally correct.. but it's a start: */
452 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
453 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
454 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
455 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
457 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
459 case PIPE_SHADER_CAP_MAX_INPUTS
:
460 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
462 case PIPE_SHADER_CAP_MAX_TEMPS
:
463 return 64; /* Max native temporaries. */
464 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
465 /* NOTE: seems to be limit for a3xx is actually 512 but
466 * split between VS and FS. Use lower limit of 256 to
467 * avoid getting into impossible situations:
469 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
470 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
471 return is_ir3(screen
) ? 16 : 1;
472 case PIPE_SHADER_CAP_MAX_PREDS
:
473 return 0; /* nothing uses this */
474 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
476 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
477 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
478 /* Technically this should be the same as for TEMP/CONST, since
479 * everything is just normal registers. This is just temporary
480 * hack until load_input/store_output handle arrays in a similar
481 * way as load_var/store_var..
484 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
485 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
486 /* a2xx compiler doesn't handle indirect: */
487 return is_ir3(screen
) ? 1 : 0;
488 case PIPE_SHADER_CAP_SUBROUTINES
:
489 case PIPE_SHADER_CAP_DOUBLES
:
490 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
491 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
492 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
493 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
495 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
497 case PIPE_SHADER_CAP_INTEGERS
:
500 return is_ir3(screen
) ? 1 : 0;
501 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
502 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
504 case PIPE_SHADER_CAP_PREFERRED_IR
:
505 if ((fd_mesa_debug
& FD_DBG_NIR
) && is_ir3(screen
))
506 return PIPE_SHADER_IR_NIR
;
507 return PIPE_SHADER_IR_TGSI
;
508 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
510 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
512 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
513 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
514 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
517 debug_printf("unknown shader param %d\n", param
);
522 fd_get_compiler_options(struct pipe_screen
*pscreen
,
523 enum pipe_shader_ir ir
, unsigned shader
)
525 struct fd_screen
*screen
= fd_screen(pscreen
);
528 return ir3_get_compiler_options();
534 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
537 struct winsys_handle
*whandle
)
539 whandle
->stride
= stride
;
541 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
542 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
543 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
544 whandle
->handle
= fd_bo_handle(bo
);
546 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
547 whandle
->handle
= fd_bo_dmabuf(bo
);
555 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
556 struct winsys_handle
*whandle
)
558 struct fd_screen
*screen
= fd_screen(pscreen
);
561 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
562 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
563 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
564 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
565 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
566 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
568 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
573 DBG("ref name 0x%08x failed", whandle
->handle
);
581 fd_screen_create(struct fd_device
*dev
)
583 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
584 struct pipe_screen
*pscreen
;
587 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
589 if (fd_mesa_debug
& FD_DBG_NOBIN
)
590 fd_binning_enabled
= false;
592 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
597 pscreen
= &screen
->base
;
602 // maybe this should be in context?
603 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
605 DBG("could not create 3d pipe");
609 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
610 DBG("could not get GMEM size");
613 screen
->gmemsize_bytes
= val
;
615 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
616 DBG("could not get device-id");
619 screen
->device_id
= val
;
621 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
622 DBG("could not get gpu freq");
623 /* this limits what performance related queries are
624 * supported but is not fatal
626 screen
->max_freq
= 0;
628 screen
->max_freq
= val
;
629 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
630 screen
->has_timestamp
= true;
633 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
634 DBG("could not get gpu-id");
637 screen
->gpu_id
= val
;
639 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
640 DBG("could not get chip-id");
641 /* older kernels may not have this property: */
642 unsigned core
= screen
->gpu_id
/ 100;
643 unsigned major
= (screen
->gpu_id
% 100) / 10;
644 unsigned minor
= screen
->gpu_id
% 10;
645 unsigned patch
= 0; /* assume the worst */
646 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
647 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
649 screen
->chip_id
= val
;
652 DBG(" GPU-id: %d", screen
->gpu_id
);
653 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
654 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
656 /* explicitly checking for GPU revisions that are known to work. This
657 * may be overly conservative for a3xx, where spoofing the gpu_id with
658 * the blob driver seems to generate identical cmdstream dumps. But
659 * on a2xx, there seem to be small differences between the GPU revs
660 * so it is probably better to actually test first on real hardware
663 * If you have a different adreno version, feel free to add it to one
664 * of the cases below and see what happens. And if it works, please
667 switch (screen
->gpu_id
) {
669 fd2_screen_init(pscreen
);
675 fd3_screen_init(pscreen
);
679 fd4_screen_init(pscreen
);
682 fd5_screen_init(pscreen
);
685 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
689 if (screen
->gpu_id
>= 500) {
690 screen
->gmem_alignw
= 64;
691 screen
->gmem_alignh
= 32;
693 screen
->gmem_alignw
= 32;
694 screen
->gmem_alignh
= 32;
697 /* NOTE: don't enable reordering on a2xx, since completely untested.
698 * Also, don't enable if we have too old of a kernel to support
699 * growable cmdstream buffers, since memory requirement for cmdstream
700 * buffers would be too much otherwise.
702 if ((screen
->gpu_id
>= 300) && (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
))
703 screen
->reorder
= !!(fd_mesa_debug
& FD_DBG_REORDER
);
705 fd_bc_init(&screen
->batch_cache
);
707 pipe_mutex_init(screen
->lock
);
709 pscreen
->destroy
= fd_screen_destroy
;
710 pscreen
->get_param
= fd_screen_get_param
;
711 pscreen
->get_paramf
= fd_screen_get_paramf
;
712 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
713 pscreen
->get_compiler_options
= fd_get_compiler_options
;
715 fd_resource_screen_init(pscreen
);
716 fd_query_screen_init(pscreen
);
718 pscreen
->get_name
= fd_screen_get_name
;
719 pscreen
->get_vendor
= fd_screen_get_vendor
;
720 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
722 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
724 pscreen
->fence_reference
= fd_fence_ref
;
725 pscreen
->fence_finish
= fd_fence_finish
;
726 pscreen
->fence_get_fd
= fd_fence_get_fd
;
728 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
730 util_format_s3tc_init();
735 fd_screen_destroy(pscreen
);