src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 /* XXX this should go away */
  58 #include "state_tracker/drm_driver.h"
  59
  60 static const struct debug_named_value debug_options[] = {
  61                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  62                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  63                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  64                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  65                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  66                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  67                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  68                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  69                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  71                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  72                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  73                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  74                 DEBUG_NAMED_VALUE_END
  75 };
  76
  77 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  78
  79 int fd_mesa_debug = 0;
  80 bool fd_binning_enabled = true;
  81 static bool glsl120 = false;
  82
  83 static const char *
  84 fd_screen_get_name(struct pipe_screen *pscreen)
  85 {
  86         static char buffer[128];
  87         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  88                         fd_screen(pscreen)->device_id);
  89         return buffer;
  90 }
  91
  92 static const char *
  93 fd_screen_get_vendor(struct pipe_screen *pscreen)
  94 {
  95         return "freedreno";
  96 }
  97
  98 static const char *
  99 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 100 {
 101         return "Qualcomm";
 102 }
 103
 104
 105 static uint64_t
 106 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 107 {
 108         int64_t cpu_time = os_time_get() * 1000;
 109         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 110 }
 111
 112 static void
 113 fd_screen_destroy(struct pipe_screen *pscreen)
 114 {
 115         struct fd_screen *screen = fd_screen(pscreen);
 116
 117         if (screen->pipe)
 118                 fd_pipe_del(screen->pipe);
 119
 120         if (screen->dev)
 121                 fd_device_del(screen->dev);
 122
 123         free(screen);
 124 }
 125
 126 /*
 127 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 128 tables for things that differ if the delta is not too much..
 129  */
 130 static int
 131 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         /* this is probably not totally correct.. but it's a start: */
 136         switch (param) {
 137         /* Supported features (boolean caps). */
 138         case PIPE_CAP_NPOT_TEXTURES:
 139         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 140         case PIPE_CAP_TWO_SIDED_STENCIL:
 141         case PIPE_CAP_ANISOTROPIC_FILTER:
 142         case PIPE_CAP_POINT_SPRITE:
 143         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 144         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 145         case PIPE_CAP_TEXTURE_SWIZZLE:
 146         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 148         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 149         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 150         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 151         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 152         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 153         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 154         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 155         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 156         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 157         case PIPE_CAP_VERTEXID_NOBASE:
 158         case PIPE_CAP_STRING_MARKER:
 159                 return 1;
 160
 161         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 162         case PIPE_CAP_TGSI_TEXCOORD:
 163         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 164         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 165         case PIPE_CAP_TEXTURE_BARRIER:
 166         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 167         case PIPE_CAP_COMPUTE:
 168         case PIPE_CAP_QUERY_MEMORY_INFO:
 169         case PIPE_CAP_PCI_GROUP:
 170         case PIPE_CAP_PCI_BUS:
 171         case PIPE_CAP_PCI_DEVICE:
 172         case PIPE_CAP_PCI_FUNCTION:
 173                 return 0;
 174
 175         case PIPE_CAP_SM3:
 176         case PIPE_CAP_PRIMITIVE_RESTART:
 177         case PIPE_CAP_TGSI_INSTANCEID:
 178         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 179         case PIPE_CAP_INDEP_BLEND_ENABLE:
 180         case PIPE_CAP_INDEP_BLEND_FUNC:
 181         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 182         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 183         case PIPE_CAP_CONDITIONAL_RENDER:
 184         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 185         case PIPE_CAP_FAKE_SW_MSAA:
 186         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 187         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 188         case PIPE_CAP_CLIP_HALFZ:
 189                 return is_a3xx(screen) || is_a4xx(screen);
 190
 191         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 192                 return 0;
 193         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 194                 if (is_a3xx(screen)) return 16;
 195                 if (is_a4xx(screen)) return 32;
 196                 return 0;
 197         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 198                 /* We could possibly emulate more by pretending 2d/rect textures and
 199                  * splitting high bits of index into 2nd dimension..
 200                  */
 201                 if (is_a3xx(screen)) return 8192;
 202                 if (is_a4xx(screen)) return 16384;
 203                 return 0;
 204
 205         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 206         case PIPE_CAP_CUBE_MAP_ARRAY:
 207         case PIPE_CAP_START_INSTANCE:
 208         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 209         case PIPE_CAP_TEXTURE_QUERY_LOD:
 210                 return is_a4xx(screen);
 211
 212         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 213                 return 256;
 214
 215         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 216                 if (glsl120)
 217                         return 120;
 218                 return is_ir3(screen) ? 140 : 120;
 219
 220         /* Unsupported features. */
 221         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 222         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 223         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 224         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 225         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 226         case PIPE_CAP_USER_VERTEX_BUFFERS:
 227         case PIPE_CAP_USER_INDEX_BUFFERS:
 228         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 229         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 230         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 231         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 232         case PIPE_CAP_TEXTURE_GATHER_SM5:
 233         case PIPE_CAP_SAMPLE_SHADING:
 234         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 235         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 236         case PIPE_CAP_DRAW_INDIRECT:
 237         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 238         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 239         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 240         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 241         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 242         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 243         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 244         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 245         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 246         case PIPE_CAP_TGSI_TXQS:
 247         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 248         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 249         case PIPE_CAP_CLEAR_TEXTURE:
 250         case PIPE_CAP_DRAW_PARAMETERS:
 251         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 252         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 253         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 254         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 255         case PIPE_CAP_INVALIDATE_BUFFER:
 256         case PIPE_CAP_GENERATE_MIPMAP:
 257         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 258                 return 0;
 259
 260         case PIPE_CAP_MAX_VIEWPORTS:
 261                 return 1;
 262
 263         case PIPE_CAP_SHAREABLE_SHADERS:
 264                 if (is_ir3(screen))
 265                         return 1;
 266                 return 0;
 267
 268         /* Stream output. */
 269         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 270                 if (is_ir3(screen))
 271                         return PIPE_MAX_SO_BUFFERS;
 272                 return 0;
 273         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 274                 if (is_ir3(screen))
 275                         return 1;
 276                 return 0;
 277         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 278         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 279                 if (is_ir3(screen))
 280                         return 16 * 4;   /* should only be shader out limit? */
 281                 return 0;
 282
 283         /* Geometry shader output, unsupported. */
 284         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 285         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 286         case PIPE_CAP_MAX_VERTEX_STREAMS:
 287                 return 0;
 288
 289         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 290                 return 2048;
 291
 292         /* Texturing. */
 293         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 294         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 295                 return MAX_MIP_LEVELS;
 296         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 297                 return 11;
 298
 299         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 300                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 301
 302         /* Render targets. */
 303         case PIPE_CAP_MAX_RENDER_TARGETS:
 304                 return screen->max_rts;
 305         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 306                 return is_a3xx(screen) ? 1 : 0;
 307
 308         /* Queries. */
 309         case PIPE_CAP_QUERY_TIMESTAMP:
 310         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 311                 return 0;
 312         case PIPE_CAP_OCCLUSION_QUERY:
 313                 return is_a3xx(screen) || is_a4xx(screen);
 314         case PIPE_CAP_QUERY_TIME_ELAPSED:
 315                 /* only a4xx, requires new enough kernel so we know max_freq: */
 316                 return (screen->max_freq > 0) && is_a4xx(screen);
 317
 318         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 319         case PIPE_CAP_MIN_TEXEL_OFFSET:
 320                 return -8;
 321
 322         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 323         case PIPE_CAP_MAX_TEXEL_OFFSET:
 324                 return 7;
 325
 326         case PIPE_CAP_ENDIANNESS:
 327                 return PIPE_ENDIAN_LITTLE;
 328
 329         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 330                 return 64;
 331
 332         case PIPE_CAP_VENDOR_ID:
 333                 return 0x5143;
 334         case PIPE_CAP_DEVICE_ID:
 335                 return 0xFFFFFFFF;
 336         case PIPE_CAP_ACCELERATED:
 337                 return 1;
 338         case PIPE_CAP_VIDEO_MEMORY:
 339                 DBG("FINISHME: The value returned is incorrect\n");
 340                 return 10;
 341         case PIPE_CAP_UMA:
 342                 return 1;
 343         }
 344         debug_printf("unknown param %d\n", param);
 345         return 0;
 346 }
 347
 348 static float
 349 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 350 {
 351         switch (param) {
 352         case PIPE_CAPF_MAX_LINE_WIDTH:
 353         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 354         case PIPE_CAPF_MAX_POINT_WIDTH:
 355         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 356                 return 4092.0f;
 357         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 358                 return 16.0f;
 359         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 360                 return 15.0f;
 361         case PIPE_CAPF_GUARD_BAND_LEFT:
 362         case PIPE_CAPF_GUARD_BAND_TOP:
 363         case PIPE_CAPF_GUARD_BAND_RIGHT:
 364         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 365                 return 0.0f;
 366         }
 367         debug_printf("unknown paramf %d\n", param);
 368         return 0;
 369 }
 370
 371 static int
 372 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 373                 enum pipe_shader_cap param)
 374 {
 375         struct fd_screen *screen = fd_screen(pscreen);
 376
 377         switch(shader)
 378         {
 379         case PIPE_SHADER_FRAGMENT:
 380         case PIPE_SHADER_VERTEX:
 381                 break;
 382         case PIPE_SHADER_COMPUTE:
 383         case PIPE_SHADER_GEOMETRY:
 384                 /* maye we could emulate.. */
 385                 return 0;
 386         default:
 387                 DBG("unknown shader type %d", shader);
 388                 return 0;
 389         }
 390
 391         /* this is probably not totally correct.. but it's a start: */
 392         switch (param) {
 393         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 394         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 395         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 396         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 397                 return 16384;
 398         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 399                 return 8; /* XXX */
 400         case PIPE_SHADER_CAP_MAX_INPUTS:
 401         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 402                 return 16;
 403         case PIPE_SHADER_CAP_MAX_TEMPS:
 404                 return 64; /* Max native temporaries. */
 405         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 406                 /* NOTE: seems to be limit for a3xx is actually 512 but
 407                  * split between VS and FS.  Use lower limit of 256 to
 408                  * avoid getting into impossible situations:
 409                  */
 410                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 411         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 412                 return is_ir3(screen) ? 16 : 1;
 413         case PIPE_SHADER_CAP_MAX_PREDS:
 414                 return 0; /* nothing uses this */
 415         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 416                 return 1;
 417         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 418         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 419                 /* Technically this should be the same as for TEMP/CONST, since
 420                  * everything is just normal registers.  This is just temporary
 421                  * hack until load_input/store_output handle arrays in a similar
 422                  * way as load_var/store_var..
 423                  */
 424                 return 0;
 425         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 426         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 427                 /* a2xx compiler doesn't handle indirect: */
 428                 return is_ir3(screen) ? 1 : 0;
 429         case PIPE_SHADER_CAP_SUBROUTINES:
 430         case PIPE_SHADER_CAP_DOUBLES:
 431         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 432         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 433         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 434         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 435                 return 0;
 436         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 437                 return 1;
 438         case PIPE_SHADER_CAP_INTEGERS:
 439                 if (glsl120)
 440                         return 0;
 441                 return is_ir3(screen) ? 1 : 0;
 442         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 443         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 444                 return 16;
 445         case PIPE_SHADER_CAP_PREFERRED_IR:
 446                 return PIPE_SHADER_IR_TGSI;
 447         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 448                 return 0;
 449         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 450                 return 32;
 451         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 452         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 453                 return 0;
 454         }
 455         debug_printf("unknown shader param %d\n", param);
 456         return 0;
 457 }
 458
 459 boolean
 460 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 461                 struct fd_bo *bo,
 462                 unsigned stride,
 463                 struct winsys_handle *whandle)
 464 {
 465         whandle->stride = stride;
 466
 467         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 468                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 469         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 470                 whandle->handle = fd_bo_handle(bo);
 471                 return TRUE;
 472         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 473                 whandle->handle = fd_bo_dmabuf(bo);
 474                 return TRUE;
 475         } else {
 476                 return FALSE;
 477         }
 478 }
 479
 480 struct fd_bo *
 481 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 482                 struct winsys_handle *whandle,
 483                 unsigned *out_stride)
 484 {
 485         struct fd_screen *screen = fd_screen(pscreen);
 486         struct fd_bo *bo;
 487
 488         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 489                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 490         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 491                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 492         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 493                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 494         } else {
 495                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 496                 return NULL;
 497         }
 498
 499         if (!bo) {
 500                 DBG("ref name 0x%08x failed", whandle->handle);
 501                 return NULL;
 502         }
 503
 504         *out_stride = whandle->stride;
 505
 506         return bo;
 507 }
 508
 509 struct pipe_screen *
 510 fd_screen_create(struct fd_device *dev)
 511 {
 512         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 513         struct pipe_screen *pscreen;
 514         uint64_t val;
 515
 516         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 517
 518         if (fd_mesa_debug & FD_DBG_NOBIN)
 519                 fd_binning_enabled = false;
 520
 521         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 522
 523         if (!screen)
 524                 return NULL;
 525
 526         pscreen = &screen->base;
 527
 528         screen->dev = dev;
 529         screen->refcnt = 1;
 530
 531         // maybe this should be in context?
 532         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 533         if (!screen->pipe) {
 534                 DBG("could not create 3d pipe");
 535                 goto fail;
 536         }
 537
 538         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 539                 DBG("could not get GMEM size");
 540                 goto fail;
 541         }
 542         screen->gmemsize_bytes = val;
 543
 544         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 545                 DBG("could not get device-id");
 546                 goto fail;
 547         }
 548         screen->device_id = val;
 549
 550         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 551                 DBG("could not get gpu freq");
 552                 /* this limits what performance related queries are
 553                  * supported but is not fatal
 554                  */
 555                 screen->max_freq = 0;
 556         } else {
 557                 screen->max_freq = val;
 558         }
 559
 560         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 561                 DBG("could not get gpu-id");
 562                 goto fail;
 563         }
 564         screen->gpu_id = val;
 565
 566         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 567                 DBG("could not get chip-id");
 568                 /* older kernels may not have this property: */
 569                 unsigned core  = screen->gpu_id / 100;
 570                 unsigned major = (screen->gpu_id % 100) / 10;
 571                 unsigned minor = screen->gpu_id % 10;
 572                 unsigned patch = 0;  /* assume the worst */
 573                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 574                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 575         }
 576         screen->chip_id = val;
 577
 578         DBG("Pipe Info:");
 579         DBG(" GPU-id:          %d", screen->gpu_id);
 580         DBG(" Chip-id:         0x%08x", screen->chip_id);
 581         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 582
 583         /* explicitly checking for GPU revisions that are known to work.  This
 584          * may be overly conservative for a3xx, where spoofing the gpu_id with
 585          * the blob driver seems to generate identical cmdstream dumps.  But
 586          * on a2xx, there seem to be small differences between the GPU revs
 587          * so it is probably better to actually test first on real hardware
 588          * before enabling:
 589          *
 590          * If you have a different adreno version, feel free to add it to one
 591          * of the cases below and see what happens.  And if it works, please
 592          * send a patch ;-)
 593          */
 594         switch (screen->gpu_id) {
 595         case 220:
 596                 fd2_screen_init(pscreen);
 597                 break;
 598         case 305:
 599         case 307:
 600         case 320:
 601         case 330:
 602                 fd3_screen_init(pscreen);
 603                 break;
 604         case 420:
 605         case 430:
 606                 fd4_screen_init(pscreen);
 607                 break;
 608         default:
 609                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 610                 goto fail;
 611         }
 612
 613         pscreen->destroy = fd_screen_destroy;
 614         pscreen->get_param = fd_screen_get_param;
 615         pscreen->get_paramf = fd_screen_get_paramf;
 616         pscreen->get_shader_param = fd_screen_get_shader_param;
 617
 618         fd_resource_screen_init(pscreen);
 619         fd_query_screen_init(pscreen);
 620
 621         pscreen->get_name = fd_screen_get_name;
 622         pscreen->get_vendor = fd_screen_get_vendor;
 623         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 624
 625         pscreen->get_timestamp = fd_screen_get_timestamp;
 626
 627         pscreen->fence_reference = fd_screen_fence_ref;
 628         pscreen->fence_finish = fd_screen_fence_finish;
 629
 630         util_format_s3tc_init();
 631
 632         return pscreen;
 633
 634 fail:
 635         fd_screen_destroy(pscreen);
 636         return NULL;
 637 }