2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
42 #include "drm-uapi/drm_fourcc.h"
46 #include <sys/sysinfo.h>
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
61 #include "ir3/ir3_nir.h"
64 /* XXX this should go away */
65 #include "state_tracker/drm_driver.h"
67 static const struct debug_named_value debug_options
[] = {
68 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
69 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
70 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
71 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
72 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
73 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
74 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
75 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
76 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
77 {"nogmem", FD_DBG_NOGMEM
, "Disable GMEM rendering (bypass only)"},
78 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
79 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
80 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
81 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
82 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
83 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
84 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
85 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
86 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
87 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
88 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
89 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a2xx/a3xx/a5xx)"},
90 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
91 {"noubwc", FD_DBG_NOUBWC
, "Disable UBWC for all internal buffers"},
95 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
97 int fd_mesa_debug
= 0;
98 bool fd_binning_enabled
= true;
99 static bool glsl120
= false;
102 fd_screen_get_name(struct pipe_screen
*pscreen
)
104 static char buffer
[128];
105 snprintf(buffer
, sizeof(buffer
), "FD%03d",
106 fd_screen(pscreen
)->device_id
);
111 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
117 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
124 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
126 struct fd_screen
*screen
= fd_screen(pscreen
);
128 if (screen
->has_timestamp
) {
130 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
131 debug_assert(screen
->max_freq
> 0);
132 return n
* 1000000000 / screen
->max_freq
;
134 int64_t cpu_time
= os_time_get() * 1000;
135 return cpu_time
+ screen
->cpu_gpu_time_delta
;
141 fd_screen_destroy(struct pipe_screen
*pscreen
)
143 struct fd_screen
*screen
= fd_screen(pscreen
);
146 fd_pipe_del(screen
->pipe
);
149 fd_device_del(screen
->dev
);
154 fd_bc_fini(&screen
->batch_cache
);
156 slab_destroy_parent(&screen
->transfer_pool
);
158 mtx_destroy(&screen
->lock
);
160 ralloc_free(screen
->compiler
);
162 free(screen
->perfcntr_queries
);
167 TODO either move caps to a2xx/a3xx specific code, or maybe have some
168 tables for things that differ if the delta is not too much..
171 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
173 struct fd_screen
*screen
= fd_screen(pscreen
);
175 /* this is probably not totally correct.. but it's a start: */
177 /* Supported features (boolean caps). */
178 case PIPE_CAP_NPOT_TEXTURES
:
179 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
180 case PIPE_CAP_ANISOTROPIC_FILTER
:
181 case PIPE_CAP_POINT_SPRITE
:
182 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
183 case PIPE_CAP_TEXTURE_SWIZZLE
:
184 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
185 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
186 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
187 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
188 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
189 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
190 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
191 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
192 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
193 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
194 case PIPE_CAP_STRING_MARKER
:
195 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
196 case PIPE_CAP_TEXTURE_BARRIER
:
197 case PIPE_CAP_INVALIDATE_BUFFER
:
200 case PIPE_CAP_PACKED_UNIFORMS
:
201 return !is_a2xx(screen
);
203 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
204 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
205 return screen
->has_robustness
;
207 case PIPE_CAP_VERTEXID_NOBASE
:
208 return is_a3xx(screen
) || is_a4xx(screen
);
210 case PIPE_CAP_COMPUTE
:
211 return has_compute(screen
);
213 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
214 case PIPE_CAP_PCI_GROUP
:
215 case PIPE_CAP_PCI_BUS
:
216 case PIPE_CAP_PCI_DEVICE
:
217 case PIPE_CAP_PCI_FUNCTION
:
218 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
221 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
222 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
223 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
224 case PIPE_CAP_PRIMITIVE_RESTART
:
225 case PIPE_CAP_TGSI_INSTANCEID
:
226 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
227 case PIPE_CAP_INDEP_BLEND_ENABLE
:
228 case PIPE_CAP_INDEP_BLEND_FUNC
:
229 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
230 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
231 case PIPE_CAP_CONDITIONAL_RENDER
:
232 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
233 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
234 case PIPE_CAP_CLIP_HALFZ
:
235 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
237 case PIPE_CAP_FAKE_SW_MSAA
:
238 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
240 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
241 return is_a5xx(screen
) || is_a6xx(screen
);
243 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
244 return is_a6xx(screen
);
246 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
247 return is_a3xx(screen
) || is_a4xx(screen
);
249 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
250 return is_a5xx(screen
) || is_a6xx(screen
);
252 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
253 if (is_a3xx(screen
)) return 16;
254 if (is_a4xx(screen
)) return 32;
255 if (is_a5xx(screen
)) return 32;
256 if (is_a6xx(screen
)) return 64;
258 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
259 /* We could possibly emulate more by pretending 2d/rect textures and
260 * splitting high bits of index into 2nd dimension..
262 if (is_a3xx(screen
)) return 8192;
263 if (is_a4xx(screen
)) return 16384;
264 if (is_a5xx(screen
)) return 16384;
265 if (is_a6xx(screen
)) return 1 << 27;
268 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
269 case PIPE_CAP_CUBE_MAP_ARRAY
:
270 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
271 case PIPE_CAP_TEXTURE_QUERY_LOD
:
272 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
274 case PIPE_CAP_START_INSTANCE
:
275 /* Note that a5xx can do this, it just can't (at least with
276 * current firmware) do draw_indirect with base_instance.
277 * Since draw_indirect is needed sooner (gles31 and gl40 vs
278 * gl42), hide base_instance on a5xx. :-/
280 return is_a4xx(screen
);
282 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
285 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
286 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
289 return is_ir3(screen
) ? 140 : 120;
291 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
292 /* we can probably enable 320 for a5xx too, but need to test: */
293 if (is_a6xx(screen
)) return 320;
294 if (is_a5xx(screen
)) return 310;
295 if (is_ir3(screen
)) return 300;
298 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
299 if (is_a6xx(screen
)) return 64;
300 if (is_a5xx(screen
)) return 4;
303 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
304 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
308 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
309 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
312 case PIPE_CAP_FBFETCH
:
313 if (fd_device_version(screen
->dev
) >= FD_VERSION_GMEM_BASE
&&
317 case PIPE_CAP_SAMPLE_SHADING
:
318 if (is_a6xx(screen
)) return 1;
321 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
324 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
325 return screen
->priority_mask
;
327 case PIPE_CAP_DRAW_INDIRECT
:
328 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
332 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
333 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
337 case PIPE_CAP_LOAD_CONSTBUF
:
338 /* name is confusing, but this turns on std430 packing */
343 case PIPE_CAP_MAX_VIEWPORTS
:
346 case PIPE_CAP_MAX_VARYINGS
:
349 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
350 /* We don't really have a limit on this, it all goes into the main
351 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
352 * for GL_MAX_TESS_PATCH_COMPONENTS).
356 case PIPE_CAP_SHAREABLE_SHADERS
:
357 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
358 /* manage the variants for these ourself, to avoid breaking precompile: */
359 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
360 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
365 /* Geometry shaders.. */
366 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
368 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
370 case PIPE_CAP_MAX_GS_INVOCATIONS
:
374 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
376 return PIPE_MAX_SO_BUFFERS
;
378 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
379 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
380 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
384 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
386 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
387 return is_a2xx(screen
);
388 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
389 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
391 return 16 * 4; /* should only be shader out limit? */
395 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
396 return 1 << (MAX_MIP_LEVELS
- 1);
397 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
398 return MAX_MIP_LEVELS
;
399 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
402 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
403 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
405 /* Render targets. */
406 case PIPE_CAP_MAX_RENDER_TARGETS
:
407 return screen
->max_rts
;
408 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
409 return is_a3xx(screen
) ? 1 : 0;
412 case PIPE_CAP_OCCLUSION_QUERY
:
413 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
414 case PIPE_CAP_QUERY_TIMESTAMP
:
415 case PIPE_CAP_QUERY_TIME_ELAPSED
:
416 /* only a4xx, requires new enough kernel so we know max_freq: */
417 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
419 case PIPE_CAP_VENDOR_ID
:
421 case PIPE_CAP_DEVICE_ID
:
423 case PIPE_CAP_ACCELERATED
:
425 case PIPE_CAP_VIDEO_MEMORY
:
426 DBG("FINISHME: The value returned is incorrect\n");
430 case PIPE_CAP_NATIVE_FENCE_FD
:
431 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
433 return u_pipe_screen_get_param_defaults(pscreen
, param
);
438 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
441 case PIPE_CAPF_MAX_LINE_WIDTH
:
442 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
443 /* NOTE: actual value is 127.0f, but this is working around a deqp
444 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
445 * uses too small of a render target size, and gets confused when
446 * the lines start going offscreen.
448 * See: https://code.google.com/p/android/issues/detail?id=206513
450 if (fd_mesa_debug
& FD_DBG_DEQP
)
453 case PIPE_CAPF_MAX_POINT_WIDTH
:
454 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
456 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
458 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
460 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
461 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
462 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
465 debug_printf("unknown paramf %d\n", param
);
470 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
471 enum pipe_shader_type shader
,
472 enum pipe_shader_cap param
)
474 struct fd_screen
*screen
= fd_screen(pscreen
);
478 case PIPE_SHADER_FRAGMENT
:
479 case PIPE_SHADER_VERTEX
:
481 case PIPE_SHADER_TESS_CTRL
:
482 case PIPE_SHADER_TESS_EVAL
:
483 case PIPE_SHADER_GEOMETRY
:
487 case PIPE_SHADER_COMPUTE
:
488 if (has_compute(screen
))
492 DBG("unknown shader type %d", shader
);
496 /* this is probably not totally correct.. but it's a start: */
498 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
499 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
500 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
501 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
503 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
505 case PIPE_SHADER_CAP_MAX_INPUTS
:
506 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
508 case PIPE_SHADER_CAP_MAX_TEMPS
:
509 return 64; /* Max native temporaries. */
510 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
511 /* NOTE: seems to be limit for a3xx is actually 512 but
512 * split between VS and FS. Use lower limit of 256 to
513 * avoid getting into impossible situations:
515 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
516 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
517 return is_ir3(screen
) ? 16 : 1;
518 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
520 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
521 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
522 /* Technically this should be the same as for TEMP/CONST, since
523 * everything is just normal registers. This is just temporary
524 * hack until load_input/store_output handle arrays in a similar
525 * way as load_var/store_var..
527 * For tessellation stages, inputs are loaded using ldlw or ldg, both
528 * of which support indirection.
530 return shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
;
531 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
532 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
533 /* a2xx compiler doesn't handle indirect: */
534 return is_ir3(screen
) ? 1 : 0;
535 case PIPE_SHADER_CAP_SUBROUTINES
:
536 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
537 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
538 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
539 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
540 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
541 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
542 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
543 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
544 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
546 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
548 case PIPE_SHADER_CAP_INTEGERS
:
551 return is_ir3(screen
) ? 1 : 0;
552 case PIPE_SHADER_CAP_INT64_ATOMICS
:
554 case PIPE_SHADER_CAP_FP16
:
556 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
557 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
559 case PIPE_SHADER_CAP_PREFERRED_IR
:
560 return PIPE_SHADER_IR_NIR
;
561 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
562 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
563 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
565 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
566 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
567 if (is_a5xx(screen
) || is_a6xx(screen
)) {
568 /* a5xx (and a4xx for that matter) has one state-block
569 * for compute-shader SSBO's and another that is shared
570 * by VS/HS/DS/GS/FS.. so to simplify things for now
571 * just advertise SSBOs for FS and CS. We could possibly
572 * do what blob does, and partition the space for
573 * VS/HS/DS/GS/FS. The blob advertises:
575 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
576 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
577 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
578 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
579 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
580 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
581 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
583 * I think that way we could avoid having to patch shaders
584 * for actual SSBO indexes by using a static partitioning.
586 * Note same state block is used for images and buffers,
587 * but images also need texture state for read access
592 case PIPE_SHADER_FRAGMENT
:
593 case PIPE_SHADER_COMPUTE
:
601 debug_printf("unknown shader param %d\n", param
);
605 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
606 * into per-generation backend?
609 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
610 enum pipe_compute_cap param
, void *ret
)
612 struct fd_screen
*screen
= fd_screen(pscreen
);
613 const char * const ir
= "ir3";
615 if (!has_compute(screen
))
618 #define RET(x) do { \
620 memcpy(ret, x, sizeof(x)); \
625 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
626 // don't expose 64b pointer support yet, until ir3 supports 64b
627 // math, otherwise spir64 target is used and we get 64b pointer
628 // calculations that we can't do yet
629 // if (is_a5xx(screen))
630 // RET((uint32_t []){ 64 });
631 RET((uint32_t []){ 32 });
633 case PIPE_COMPUTE_CAP_IR_TARGET
:
635 sprintf(ret
, "%s", ir
);
636 return strlen(ir
) * sizeof(char);
638 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
639 RET((uint64_t []) { 3 });
641 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
642 RET(((uint64_t []) { 65535, 65535, 65535 }));
644 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
645 RET(((uint64_t []) { 1024, 1024, 64 }));
647 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
648 RET((uint64_t []) { 1024 });
650 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
651 RET((uint64_t []) { screen
->ram_size
});
653 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
654 RET((uint64_t []) { 32768 });
656 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
657 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
658 RET((uint64_t []) { 4096 });
660 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
661 RET((uint64_t []) { screen
->ram_size
});
663 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
664 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
666 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
667 RET((uint32_t []) { 9999 }); // TODO
669 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
670 RET((uint32_t []) { 1 });
672 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
673 RET((uint32_t []) { 32 }); // TODO
675 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
676 RET((uint64_t []) { 1024 }); // TODO
683 fd_get_compiler_options(struct pipe_screen
*pscreen
,
684 enum pipe_shader_ir ir
, unsigned shader
)
686 struct fd_screen
*screen
= fd_screen(pscreen
);
689 return ir3_get_compiler_options(screen
->compiler
);
691 return ir2_get_compiler_options();
695 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
697 struct renderonly_scanout
*scanout
,
699 struct winsys_handle
*whandle
)
701 whandle
->stride
= stride
;
703 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
704 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
705 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
706 if (renderonly_get_handle(scanout
, whandle
))
708 whandle
->handle
= fd_bo_handle(bo
);
710 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
711 whandle
->handle
= fd_bo_dmabuf(bo
);
719 fd_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
720 enum pipe_format format
,
721 int max
, uint64_t *modifiers
,
722 unsigned int *external_only
,
725 struct fd_screen
*screen
= fd_screen(pscreen
);
728 max
= MIN2(max
, screen
->num_supported_modifiers
);
731 max
= screen
->num_supported_modifiers
;
732 external_only
= NULL
;
736 for (i
= 0; i
< max
; i
++) {
738 modifiers
[num
] = screen
->supported_modifiers
[i
];
741 external_only
[num
] = 0;
750 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
751 struct winsys_handle
*whandle
)
753 struct fd_screen
*screen
= fd_screen(pscreen
);
756 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
757 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
758 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
759 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
760 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
761 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
763 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
768 DBG("ref name 0x%08x failed", whandle
->handle
);
775 static void _fd_fence_ref(struct pipe_screen
*pscreen
,
776 struct pipe_fence_handle
**ptr
,
777 struct pipe_fence_handle
*pfence
)
779 fd_fence_ref(ptr
, pfence
);
783 fd_screen_create(struct fd_device
*dev
, struct renderonly
*ro
)
785 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
786 struct pipe_screen
*pscreen
;
789 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
791 if (fd_mesa_debug
& FD_DBG_NOBIN
)
792 fd_binning_enabled
= false;
794 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
799 pscreen
= &screen
->base
;
805 screen
->ro
= renderonly_dup(ro
);
807 DBG("could not create renderonly object");
812 // maybe this should be in context?
813 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
815 DBG("could not create 3d pipe");
819 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
820 DBG("could not get GMEM size");
823 screen
->gmemsize_bytes
= val
;
825 if (fd_device_version(dev
) >= FD_VERSION_GMEM_BASE
) {
826 fd_pipe_get_param(screen
->pipe
, FD_GMEM_BASE
, &screen
->gmem_base
);
829 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
830 DBG("could not get device-id");
833 screen
->device_id
= val
;
835 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
836 DBG("could not get gpu freq");
837 /* this limits what performance related queries are
838 * supported but is not fatal
840 screen
->max_freq
= 0;
842 screen
->max_freq
= val
;
843 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
844 screen
->has_timestamp
= true;
847 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
848 DBG("could not get gpu-id");
851 screen
->gpu_id
= val
;
853 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
854 DBG("could not get chip-id");
855 /* older kernels may not have this property: */
856 unsigned core
= screen
->gpu_id
/ 100;
857 unsigned major
= (screen
->gpu_id
% 100) / 10;
858 unsigned minor
= screen
->gpu_id
% 10;
859 unsigned patch
= 0; /* assume the worst */
860 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
861 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
863 screen
->chip_id
= val
;
865 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
866 DBG("could not get # of rings");
867 screen
->priority_mask
= 0;
869 /* # of rings equates to number of unique priority values: */
870 screen
->priority_mask
= (1 << val
) - 1;
873 if ((fd_device_version(dev
) >= FD_VERSION_ROBUSTNESS
) &&
874 (fd_pipe_get_param(screen
->pipe
, FD_PP_PGTABLE
, &val
) == 0)) {
875 screen
->has_robustness
= val
;
880 screen
->ram_size
= si
.totalram
;
883 DBG(" GPU-id: %d", screen
->gpu_id
);
884 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
885 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
887 /* explicitly checking for GPU revisions that are known to work. This
888 * may be overly conservative for a3xx, where spoofing the gpu_id with
889 * the blob driver seems to generate identical cmdstream dumps. But
890 * on a2xx, there seem to be small differences between the GPU revs
891 * so it is probably better to actually test first on real hardware
894 * If you have a different adreno version, feel free to add it to one
895 * of the cases below and see what happens. And if it works, please
898 switch (screen
->gpu_id
) {
903 fd2_screen_init(pscreen
);
909 fd3_screen_init(pscreen
);
913 fd4_screen_init(pscreen
);
918 fd5_screen_init(pscreen
);
923 fd6_screen_init(pscreen
);
926 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
930 if (screen
->gpu_id
>= 600) {
931 screen
->gmem_alignw
= 32;
932 screen
->gmem_alignh
= 32;
933 screen
->num_vsc_pipes
= 32;
934 } else if (screen
->gpu_id
>= 500) {
935 screen
->gmem_alignw
= 64;
936 screen
->gmem_alignh
= 32;
937 screen
->num_vsc_pipes
= 16;
939 screen
->gmem_alignw
= 32;
940 screen
->gmem_alignh
= 32;
941 screen
->num_vsc_pipes
= 8;
944 /* NOTE: don't enable if we have too old of a kernel to support
945 * growable cmdstream buffers, since memory requirement for cmdstream
946 * buffers would be too much otherwise.
948 if (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
)
949 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
951 fd_bc_init(&screen
->batch_cache
);
953 (void) mtx_init(&screen
->lock
, mtx_plain
);
955 pscreen
->destroy
= fd_screen_destroy
;
956 pscreen
->get_param
= fd_screen_get_param
;
957 pscreen
->get_paramf
= fd_screen_get_paramf
;
958 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
959 pscreen
->get_compute_param
= fd_get_compute_param
;
960 pscreen
->get_compiler_options
= fd_get_compiler_options
;
962 fd_resource_screen_init(pscreen
);
963 fd_query_screen_init(pscreen
);
965 pscreen
->get_name
= fd_screen_get_name
;
966 pscreen
->get_vendor
= fd_screen_get_vendor
;
967 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
969 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
971 pscreen
->fence_reference
= _fd_fence_ref
;
972 pscreen
->fence_finish
= fd_fence_finish
;
973 pscreen
->fence_get_fd
= fd_fence_get_fd
;
975 pscreen
->query_dmabuf_modifiers
= fd_screen_query_dmabuf_modifiers
;
977 if (!screen
->supported_modifiers
) {
978 static const uint64_t supported_modifiers
[] = {
979 DRM_FORMAT_MOD_LINEAR
,
982 screen
->supported_modifiers
= supported_modifiers
;
983 screen
->num_supported_modifiers
= ARRAY_SIZE(supported_modifiers
);
986 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
991 fd_screen_destroy(pscreen
);