freedreno/a5xx: hw binning support
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
40
41 #include "os/os_time.h"
42
43 #include <stdio.h>
44 #include <errno.h>
45 #include <stdlib.h>
46
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
52
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57
58 #include "ir3/ir3_nir.h"
59
60 /* XXX this should go away */
61 #include "state_tracker/drm_driver.h"
62
63 static const struct debug_named_value debug_options[] = {
64 {"msgs", FD_DBG_MSGS, "Print debug messages"},
65 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
66 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
67 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
68 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
69 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
70 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
71 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
72 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
73 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
74 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
75 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
76 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
77 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
78 {"nir", FD_DBG_NIR, "Prefer NIR as native IR"},
79 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 DEBUG_NAMED_VALUE_END
83 };
84
85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
86
87 int fd_mesa_debug = 0;
88 bool fd_binning_enabled = true;
89 static bool glsl120 = false;
90
91 static const char *
92 fd_screen_get_name(struct pipe_screen *pscreen)
93 {
94 static char buffer[128];
95 util_snprintf(buffer, sizeof(buffer), "FD%03d",
96 fd_screen(pscreen)->device_id);
97 return buffer;
98 }
99
100 static const char *
101 fd_screen_get_vendor(struct pipe_screen *pscreen)
102 {
103 return "freedreno";
104 }
105
106 static const char *
107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
108 {
109 return "Qualcomm";
110 }
111
112
113 static uint64_t
114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
115 {
116 struct fd_screen *screen = fd_screen(pscreen);
117
118 if (screen->has_timestamp) {
119 uint64_t n;
120 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
121 debug_assert(screen->max_freq > 0);
122 return n * 1000000000 / screen->max_freq;
123 } else {
124 int64_t cpu_time = os_time_get() * 1000;
125 return cpu_time + screen->cpu_gpu_time_delta;
126 }
127
128 }
129
130 static void
131 fd_screen_destroy(struct pipe_screen *pscreen)
132 {
133 struct fd_screen *screen = fd_screen(pscreen);
134
135 if (screen->pipe)
136 fd_pipe_del(screen->pipe);
137
138 if (screen->dev)
139 fd_device_del(screen->dev);
140
141 fd_bc_fini(&screen->batch_cache);
142
143 slab_destroy_parent(&screen->transfer_pool);
144
145 mtx_destroy(&screen->lock);
146
147 ralloc_free(screen->compiler);
148
149 free(screen);
150 }
151
152 /*
153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
154 tables for things that differ if the delta is not too much..
155 */
156 static int
157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
158 {
159 struct fd_screen *screen = fd_screen(pscreen);
160
161 /* this is probably not totally correct.. but it's a start: */
162 switch (param) {
163 /* Supported features (boolean caps). */
164 case PIPE_CAP_NPOT_TEXTURES:
165 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
166 case PIPE_CAP_TWO_SIDED_STENCIL:
167 case PIPE_CAP_ANISOTROPIC_FILTER:
168 case PIPE_CAP_POINT_SPRITE:
169 case PIPE_CAP_TEXTURE_SHADOW_MAP:
170 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
171 case PIPE_CAP_TEXTURE_SWIZZLE:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
173 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP:
176 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
177 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
178 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
179 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
180 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
182 case PIPE_CAP_STRING_MARKER:
183 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
184 return 1;
185
186 case PIPE_CAP_VERTEXID_NOBASE:
187 return is_a3xx(screen) || is_a4xx(screen);
188
189 case PIPE_CAP_USER_CONSTANT_BUFFERS:
190 return is_a4xx(screen) ? 0 : 1;
191
192 case PIPE_CAP_COMPUTE:
193 return has_compute(screen);
194
195 case PIPE_CAP_SHADER_STENCIL_EXPORT:
196 case PIPE_CAP_TGSI_TEXCOORD:
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
198 case PIPE_CAP_TEXTURE_MULTISAMPLE:
199 case PIPE_CAP_TEXTURE_BARRIER:
200 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
201 case PIPE_CAP_QUERY_MEMORY_INFO:
202 case PIPE_CAP_PCI_GROUP:
203 case PIPE_CAP_PCI_BUS:
204 case PIPE_CAP_PCI_DEVICE:
205 case PIPE_CAP_PCI_FUNCTION:
206 return 0;
207
208 case PIPE_CAP_SM3:
209 case PIPE_CAP_PRIMITIVE_RESTART:
210 case PIPE_CAP_TGSI_INSTANCEID:
211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
212 case PIPE_CAP_INDEP_BLEND_ENABLE:
213 case PIPE_CAP_INDEP_BLEND_FUNC:
214 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
215 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
216 case PIPE_CAP_CONDITIONAL_RENDER:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
218 case PIPE_CAP_FAKE_SW_MSAA:
219 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
220 case PIPE_CAP_DEPTH_CLIP_DISABLE:
221 case PIPE_CAP_CLIP_HALFZ:
222 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
223
224 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
225 return 0;
226 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
227 if (is_a3xx(screen)) return 16;
228 if (is_a4xx(screen)) return 32;
229 if (is_a5xx(screen)) return 32;
230 return 0;
231 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
232 /* We could possibly emulate more by pretending 2d/rect textures and
233 * splitting high bits of index into 2nd dimension..
234 */
235 if (is_a3xx(screen)) return 8192;
236 if (is_a4xx(screen)) return 16384;
237 if (is_a5xx(screen)) return 16384;
238 return 0;
239
240 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
241 case PIPE_CAP_CUBE_MAP_ARRAY:
242 case PIPE_CAP_START_INSTANCE:
243 case PIPE_CAP_SAMPLER_VIEW_TARGET:
244 case PIPE_CAP_TEXTURE_QUERY_LOD:
245 return is_a4xx(screen) || is_a5xx(screen);
246
247 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
248 return 64;
249
250 case PIPE_CAP_GLSL_FEATURE_LEVEL:
251 if (glsl120)
252 return 120;
253 return is_ir3(screen) ? 140 : 120;
254
255 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
256 if (is_a5xx(screen))
257 return 4;
258 return 0;
259
260 /* Unsupported features. */
261 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
262 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
263 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
264 case PIPE_CAP_USER_VERTEX_BUFFERS:
265 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
266 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
267 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
268 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
269 case PIPE_CAP_TEXTURE_GATHER_SM5:
270 case PIPE_CAP_SAMPLE_SHADING:
271 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
272 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
273 case PIPE_CAP_DRAW_INDIRECT:
274 case PIPE_CAP_MULTI_DRAW_INDIRECT:
275 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
276 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
277 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
278 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
279 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
280 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
281 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
282 case PIPE_CAP_DEPTH_BOUNDS_TEST:
283 case PIPE_CAP_TGSI_TXQS:
284 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
285 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
286 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
287 case PIPE_CAP_CLEAR_TEXTURE:
288 case PIPE_CAP_DRAW_PARAMETERS:
289 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
290 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
291 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
292 case PIPE_CAP_INVALIDATE_BUFFER:
293 case PIPE_CAP_GENERATE_MIPMAP:
294 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
295 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
296 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
297 case PIPE_CAP_CULL_DISTANCE:
298 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
299 case PIPE_CAP_TGSI_VOTE:
300 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
301 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
302 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
303 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
304 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
305 case PIPE_CAP_TGSI_FS_FBFETCH:
306 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
307 case PIPE_CAP_DOUBLES:
308 case PIPE_CAP_INT64:
309 case PIPE_CAP_INT64_DIVMOD:
310 case PIPE_CAP_TGSI_TEX_TXF_LZ:
311 case PIPE_CAP_TGSI_CLOCK:
312 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
313 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
314 case PIPE_CAP_TGSI_BALLOT:
315 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
316 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
317 return 0;
318
319 case PIPE_CAP_MAX_VIEWPORTS:
320 return 1;
321
322 case PIPE_CAP_SHAREABLE_SHADERS:
323 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
324 /* manage the variants for these ourself, to avoid breaking precompile: */
325 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
326 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
327 if (is_ir3(screen))
328 return 1;
329 return 0;
330
331 /* Stream output. */
332 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
333 if (is_ir3(screen))
334 return PIPE_MAX_SO_BUFFERS;
335 return 0;
336 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
337 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
338 if (is_ir3(screen))
339 return 1;
340 return 0;
341 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
342 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
343 if (is_ir3(screen))
344 return 16 * 4; /* should only be shader out limit? */
345 return 0;
346
347 /* Geometry shader output, unsupported. */
348 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
349 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
350 case PIPE_CAP_MAX_VERTEX_STREAMS:
351 return 0;
352
353 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
354 return 2048;
355
356 /* Texturing. */
357 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
358 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
359 return MAX_MIP_LEVELS;
360 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
361 return 11;
362
363 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
364 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
365
366 /* Render targets. */
367 case PIPE_CAP_MAX_RENDER_TARGETS:
368 return screen->max_rts;
369 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
370 return is_a3xx(screen) ? 1 : 0;
371
372 /* Queries. */
373 case PIPE_CAP_QUERY_BUFFER_OBJECT:
374 return 0;
375 case PIPE_CAP_OCCLUSION_QUERY:
376 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
377 case PIPE_CAP_QUERY_TIMESTAMP:
378 case PIPE_CAP_QUERY_TIME_ELAPSED:
379 /* only a4xx, requires new enough kernel so we know max_freq: */
380 return (screen->max_freq > 0) && is_a4xx(screen);
381
382 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
383 case PIPE_CAP_MIN_TEXEL_OFFSET:
384 return -8;
385
386 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
387 case PIPE_CAP_MAX_TEXEL_OFFSET:
388 return 7;
389
390 case PIPE_CAP_ENDIANNESS:
391 return PIPE_ENDIAN_LITTLE;
392
393 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
394 return 64;
395
396 case PIPE_CAP_VENDOR_ID:
397 return 0x5143;
398 case PIPE_CAP_DEVICE_ID:
399 return 0xFFFFFFFF;
400 case PIPE_CAP_ACCELERATED:
401 return 1;
402 case PIPE_CAP_VIDEO_MEMORY:
403 DBG("FINISHME: The value returned is incorrect\n");
404 return 10;
405 case PIPE_CAP_UMA:
406 return 1;
407 case PIPE_CAP_NATIVE_FENCE_FD:
408 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
409 }
410 debug_printf("unknown param %d\n", param);
411 return 0;
412 }
413
414 static float
415 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
416 {
417 switch (param) {
418 case PIPE_CAPF_MAX_LINE_WIDTH:
419 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
420 /* NOTE: actual value is 127.0f, but this is working around a deqp
421 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
422 * uses too small of a render target size, and gets confused when
423 * the lines start going offscreen.
424 *
425 * See: https://code.google.com/p/android/issues/detail?id=206513
426 */
427 if (fd_mesa_debug & FD_DBG_DEQP)
428 return 48.0f;
429 return 127.0f;
430 case PIPE_CAPF_MAX_POINT_WIDTH:
431 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
432 return 4092.0f;
433 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
434 return 16.0f;
435 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
436 return 15.0f;
437 case PIPE_CAPF_GUARD_BAND_LEFT:
438 case PIPE_CAPF_GUARD_BAND_TOP:
439 case PIPE_CAPF_GUARD_BAND_RIGHT:
440 case PIPE_CAPF_GUARD_BAND_BOTTOM:
441 return 0.0f;
442 }
443 debug_printf("unknown paramf %d\n", param);
444 return 0;
445 }
446
447 static int
448 fd_screen_get_shader_param(struct pipe_screen *pscreen,
449 enum pipe_shader_type shader,
450 enum pipe_shader_cap param)
451 {
452 struct fd_screen *screen = fd_screen(pscreen);
453
454 switch(shader)
455 {
456 case PIPE_SHADER_FRAGMENT:
457 case PIPE_SHADER_VERTEX:
458 break;
459 case PIPE_SHADER_COMPUTE:
460 if (has_compute(screen))
461 break;
462 return 0;
463 case PIPE_SHADER_GEOMETRY:
464 /* maye we could emulate.. */
465 return 0;
466 default:
467 DBG("unknown shader type %d", shader);
468 return 0;
469 }
470
471 /* this is probably not totally correct.. but it's a start: */
472 switch (param) {
473 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
474 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
475 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
476 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
477 return 16384;
478 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
479 return 8; /* XXX */
480 case PIPE_SHADER_CAP_MAX_INPUTS:
481 case PIPE_SHADER_CAP_MAX_OUTPUTS:
482 return 16;
483 case PIPE_SHADER_CAP_MAX_TEMPS:
484 return 64; /* Max native temporaries. */
485 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
486 /* NOTE: seems to be limit for a3xx is actually 512 but
487 * split between VS and FS. Use lower limit of 256 to
488 * avoid getting into impossible situations:
489 */
490 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
491 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
492 return is_ir3(screen) ? 16 : 1;
493 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
494 return 1;
495 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
496 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
497 /* Technically this should be the same as for TEMP/CONST, since
498 * everything is just normal registers. This is just temporary
499 * hack until load_input/store_output handle arrays in a similar
500 * way as load_var/store_var..
501 */
502 return 0;
503 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
504 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
505 /* a2xx compiler doesn't handle indirect: */
506 return is_ir3(screen) ? 1 : 0;
507 case PIPE_SHADER_CAP_SUBROUTINES:
508 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
509 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
510 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
511 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
512 return 0;
513 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
514 return 1;
515 case PIPE_SHADER_CAP_INTEGERS:
516 if (glsl120)
517 return 0;
518 return is_ir3(screen) ? 1 : 0;
519 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
520 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
521 return 16;
522 case PIPE_SHADER_CAP_PREFERRED_IR:
523 switch (shader) {
524 case PIPE_SHADER_FRAGMENT:
525 case PIPE_SHADER_VERTEX:
526 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
527 return PIPE_SHADER_IR_NIR;
528 return PIPE_SHADER_IR_TGSI;
529 default:
530 /* tgsi_to_nir doesn't really support much beyond FS/VS: */
531 debug_assert(is_ir3(screen));
532 return PIPE_SHADER_IR_NIR;
533 }
534 break;
535 case PIPE_SHADER_CAP_SUPPORTED_IRS:
536 if (is_ir3(screen)) {
537 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
538 } else {
539 return (1 << PIPE_SHADER_IR_TGSI);
540 }
541 return 0;
542 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
543 return 32;
544 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
545 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
546 return 0;
547 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
548 if (is_a5xx(screen)) {
549 /* a5xx (and a4xx for that matter) has one state-block
550 * for compute-shader SSBO's and another that is shared
551 * by VS/HS/DS/GS/FS.. so to simplify things for now
552 * just advertise SSBOs for FS and CS. We could possibly
553 * do what blob does, and partition the space for
554 * VS/HS/DS/GS/FS. The blob advertises:
555 *
556 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
557 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
558 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
559 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
560 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
561 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
562 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
563 *
564 * I think that way we could avoid having to patch shaders
565 * for actual SSBO indexes by using a static partitioning.
566 */
567 switch(shader)
568 {
569 case PIPE_SHADER_FRAGMENT:
570 case PIPE_SHADER_COMPUTE:
571 return 24;
572 default:
573 return 0;
574 }
575 }
576 return 0;
577 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
578 /* probably should be same as MAX_SHADRER_BUFFERS but not implemented yet */
579 return 0;
580 }
581 debug_printf("unknown shader param %d\n", param);
582 return 0;
583 }
584
585 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
586 * into per-generation backend?
587 */
588 static int
589 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
590 enum pipe_compute_cap param, void *ret)
591 {
592 struct fd_screen *screen = fd_screen(pscreen);
593 const char * const ir = "ir3";
594
595 if (!has_compute(screen))
596 return 0;
597
598 switch (param) {
599 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
600 if (ret) {
601 uint32_t *address_bits = ret;
602 address_bits[0] = 32;
603
604 if (is_a5xx(screen))
605 address_bits[0] = 64;
606 }
607 return 1 * sizeof(uint32_t);
608
609 case PIPE_COMPUTE_CAP_IR_TARGET:
610 if (ret)
611 sprintf(ret, ir);
612 return strlen(ir) * sizeof(char);
613
614 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
615 if (ret) {
616 uint64_t *grid_dimension = ret;
617 grid_dimension[0] = 3;
618 }
619 return 1 * sizeof(uint64_t);
620
621 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
622 if (ret) {
623 uint64_t *grid_size = ret;
624 grid_size[0] = 65535;
625 grid_size[1] = 65535;
626 grid_size[2] = 65535;
627 }
628 return 3 * sizeof(uint64_t) ;
629
630 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
631 if (ret) {
632 uint64_t *grid_size = ret;
633 grid_size[0] = 1024;
634 grid_size[1] = 1024;
635 grid_size[2] = 64;
636 }
637 return 3 * sizeof(uint64_t) ;
638
639 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
640 if (ret) {
641 uint64_t *max_threads_per_block = ret;
642 *max_threads_per_block = 1024;
643 }
644 return sizeof(uint64_t);
645
646 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
647 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
648 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
649 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
650 break;
651 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
652 if (ret) {
653 uint64_t *max = ret;
654 *max = 32768;
655 }
656 return sizeof(uint64_t);
657 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
658 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
659 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
660 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
661 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
662 break;
663 }
664
665 return 0;
666 }
667
668 static const void *
669 fd_get_compiler_options(struct pipe_screen *pscreen,
670 enum pipe_shader_ir ir, unsigned shader)
671 {
672 struct fd_screen *screen = fd_screen(pscreen);
673
674 if (is_ir3(screen))
675 return ir3_get_compiler_options();
676
677 return NULL;
678 }
679
680 boolean
681 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
682 struct fd_bo *bo,
683 unsigned stride,
684 struct winsys_handle *whandle)
685 {
686 whandle->stride = stride;
687
688 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
689 return fd_bo_get_name(bo, &whandle->handle) == 0;
690 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
691 whandle->handle = fd_bo_handle(bo);
692 return TRUE;
693 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
694 whandle->handle = fd_bo_dmabuf(bo);
695 return TRUE;
696 } else {
697 return FALSE;
698 }
699 }
700
701 struct fd_bo *
702 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
703 struct winsys_handle *whandle)
704 {
705 struct fd_screen *screen = fd_screen(pscreen);
706 struct fd_bo *bo;
707
708 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
709 bo = fd_bo_from_name(screen->dev, whandle->handle);
710 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
711 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
712 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
713 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
714 } else {
715 DBG("Attempt to import unsupported handle type %d", whandle->type);
716 return NULL;
717 }
718
719 if (!bo) {
720 DBG("ref name 0x%08x failed", whandle->handle);
721 return NULL;
722 }
723
724 return bo;
725 }
726
727 struct pipe_screen *
728 fd_screen_create(struct fd_device *dev)
729 {
730 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
731 struct pipe_screen *pscreen;
732 uint64_t val;
733
734 fd_mesa_debug = debug_get_option_fd_mesa_debug();
735
736 if (fd_mesa_debug & FD_DBG_NOBIN)
737 fd_binning_enabled = false;
738
739 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
740
741 if (!screen)
742 return NULL;
743
744 pscreen = &screen->base;
745
746 screen->dev = dev;
747 screen->refcnt = 1;
748
749 // maybe this should be in context?
750 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
751 if (!screen->pipe) {
752 DBG("could not create 3d pipe");
753 goto fail;
754 }
755
756 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
757 DBG("could not get GMEM size");
758 goto fail;
759 }
760 screen->gmemsize_bytes = val;
761
762 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
763 DBG("could not get device-id");
764 goto fail;
765 }
766 screen->device_id = val;
767
768 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
769 DBG("could not get gpu freq");
770 /* this limits what performance related queries are
771 * supported but is not fatal
772 */
773 screen->max_freq = 0;
774 } else {
775 screen->max_freq = val;
776 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
777 screen->has_timestamp = true;
778 }
779
780 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
781 DBG("could not get gpu-id");
782 goto fail;
783 }
784 screen->gpu_id = val;
785
786 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
787 DBG("could not get chip-id");
788 /* older kernels may not have this property: */
789 unsigned core = screen->gpu_id / 100;
790 unsigned major = (screen->gpu_id % 100) / 10;
791 unsigned minor = screen->gpu_id % 10;
792 unsigned patch = 0; /* assume the worst */
793 val = (patch & 0xff) | ((minor & 0xff) << 8) |
794 ((major & 0xff) << 16) | ((core & 0xff) << 24);
795 }
796 screen->chip_id = val;
797
798 DBG("Pipe Info:");
799 DBG(" GPU-id: %d", screen->gpu_id);
800 DBG(" Chip-id: 0x%08x", screen->chip_id);
801 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
802
803 /* explicitly checking for GPU revisions that are known to work. This
804 * may be overly conservative for a3xx, where spoofing the gpu_id with
805 * the blob driver seems to generate identical cmdstream dumps. But
806 * on a2xx, there seem to be small differences between the GPU revs
807 * so it is probably better to actually test first on real hardware
808 * before enabling:
809 *
810 * If you have a different adreno version, feel free to add it to one
811 * of the cases below and see what happens. And if it works, please
812 * send a patch ;-)
813 */
814 switch (screen->gpu_id) {
815 case 220:
816 fd2_screen_init(pscreen);
817 break;
818 case 305:
819 case 307:
820 case 320:
821 case 330:
822 fd3_screen_init(pscreen);
823 break;
824 case 420:
825 case 430:
826 fd4_screen_init(pscreen);
827 break;
828 case 530:
829 fd5_screen_init(pscreen);
830 break;
831 default:
832 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
833 goto fail;
834 }
835
836 if (screen->gpu_id >= 500) {
837 screen->gmem_alignw = 64;
838 screen->gmem_alignh = 32;
839 screen->num_vsc_pipes = 16;
840 } else {
841 screen->gmem_alignw = 32;
842 screen->gmem_alignh = 32;
843 screen->num_vsc_pipes = 8;
844 }
845
846 /* NOTE: don't enable reordering on a2xx, since completely untested.
847 * Also, don't enable if we have too old of a kernel to support
848 * growable cmdstream buffers, since memory requirement for cmdstream
849 * buffers would be too much otherwise.
850 */
851 if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
852 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
853
854 fd_bc_init(&screen->batch_cache);
855
856 (void) mtx_init(&screen->lock, mtx_plain);
857
858 pscreen->destroy = fd_screen_destroy;
859 pscreen->get_param = fd_screen_get_param;
860 pscreen->get_paramf = fd_screen_get_paramf;
861 pscreen->get_shader_param = fd_screen_get_shader_param;
862 pscreen->get_compute_param = fd_get_compute_param;
863 pscreen->get_compiler_options = fd_get_compiler_options;
864
865 fd_resource_screen_init(pscreen);
866 fd_query_screen_init(pscreen);
867
868 pscreen->get_name = fd_screen_get_name;
869 pscreen->get_vendor = fd_screen_get_vendor;
870 pscreen->get_device_vendor = fd_screen_get_device_vendor;
871
872 pscreen->get_timestamp = fd_screen_get_timestamp;
873
874 pscreen->fence_reference = fd_fence_ref;
875 pscreen->fence_finish = fd_fence_finish;
876 pscreen->fence_get_fd = fd_fence_get_fd;
877
878 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
879
880 util_format_s3tc_init();
881
882 return pscreen;
883
884 fail:
885 fd_screen_destroy(pscreen);
886 return NULL;
887 }