src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_screen.h"
  39 #include "util/u_string.h"
  40 #include "util/u_debug.h"
  41
  42 #include "util/os_time.h"
  43
  44 #include <errno.h>
  45 #include <stdio.h>
  46 #include <stdlib.h>
  47 #include <sys/sysinfo.h>
  48
  49 #include "freedreno_screen.h"
  50 #include "freedreno_resource.h"
  51 #include "freedreno_fence.h"
  52 #include "freedreno_query.h"
  53 #include "freedreno_util.h"
  54
  55 #include "a2xx/fd2_screen.h"
  56 #include "a3xx/fd3_screen.h"
  57 #include "a4xx/fd4_screen.h"
  58 #include "a5xx/fd5_screen.h"
  59 #include "a6xx/fd6_screen.h"
  60
  61
  62 #include "ir3/ir3_nir.h"
  63
  64 /* XXX this should go away */
  65 #include "state_tracker/drm_driver.h"
  66
  67 static const struct debug_named_value debug_options[] = {
  68                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  69                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  70                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  71                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  72                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  73                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  74                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  75                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  76                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  77                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  78                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  79                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  80                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  81                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  82                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  83                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  84                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  85                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  86                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  87                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  88                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  89                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  90                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  91                 DEBUG_NAMED_VALUE_END
  92 };
  93
  94 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  95
  96 int fd_mesa_debug = 0;
  97 bool fd_binning_enabled = true;
  98 static bool glsl120 = false;
  99
 100 static const struct debug_named_value shader_debug_options[] = {
 101                 {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
 102                 {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
 103                 {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
 104                 DEBUG_NAMED_VALUE_END
 105 };
 106
 107 DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
 108
 109 enum fd_shader_debug fd_shader_debug = 0;
 110
 111 static const char *
 112 fd_screen_get_name(struct pipe_screen *pscreen)
 113 {
 114         static char buffer[128];
 115         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 116                         fd_screen(pscreen)->device_id);
 117         return buffer;
 118 }
 119
 120 static const char *
 121 fd_screen_get_vendor(struct pipe_screen *pscreen)
 122 {
 123         return "freedreno";
 124 }
 125
 126 static const char *
 127 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 128 {
 129         return "Qualcomm";
 130 }
 131
 132
 133 static uint64_t
 134 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 135 {
 136         struct fd_screen *screen = fd_screen(pscreen);
 137
 138         if (screen->has_timestamp) {
 139                 uint64_t n;
 140                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 141                 debug_assert(screen->max_freq > 0);
 142                 return n * 1000000000 / screen->max_freq;
 143         } else {
 144                 int64_t cpu_time = os_time_get() * 1000;
 145                 return cpu_time + screen->cpu_gpu_time_delta;
 146         }
 147
 148 }
 149
 150 static void
 151 fd_screen_destroy(struct pipe_screen *pscreen)
 152 {
 153         struct fd_screen *screen = fd_screen(pscreen);
 154
 155         if (screen->pipe)
 156                 fd_pipe_del(screen->pipe);
 157
 158         if (screen->dev)
 159                 fd_device_del(screen->dev);
 160
 161         fd_bc_fini(&screen->batch_cache);
 162
 163         slab_destroy_parent(&screen->transfer_pool);
 164
 165         mtx_destroy(&screen->lock);
 166
 167         ralloc_free(screen->compiler);
 168
 169         free(screen->perfcntr_queries);
 170         free(screen);
 171 }
 172
 173 /*
 174 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 175 tables for things that differ if the delta is not too much..
 176  */
 177 static int
 178 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 179 {
 180         struct fd_screen *screen = fd_screen(pscreen);
 181
 182         /* this is probably not totally correct.. but it's a start: */
 183         switch (param) {
 184         /* Supported features (boolean caps). */
 185         case PIPE_CAP_NPOT_TEXTURES:
 186         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 187         case PIPE_CAP_ANISOTROPIC_FILTER:
 188         case PIPE_CAP_POINT_SPRITE:
 189         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 190         case PIPE_CAP_TEXTURE_SWIZZLE:
 191         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 192         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 193         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 194         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 195         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 196         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 197         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 199         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 200         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 201         case PIPE_CAP_STRING_MARKER:
 202         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 203         case PIPE_CAP_TEXTURE_BARRIER:
 204         case PIPE_CAP_INVALIDATE_BUFFER:
 205                 return 1;
 206
 207         case PIPE_CAP_VERTEXID_NOBASE:
 208                 return is_a3xx(screen) || is_a4xx(screen);
 209
 210         case PIPE_CAP_COMPUTE:
 211                 return has_compute(screen);
 212
 213         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 214         case PIPE_CAP_TGSI_TEXCOORD:
 215         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 216         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 217         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 218         case PIPE_CAP_QUERY_MEMORY_INFO:
 219         case PIPE_CAP_PCI_GROUP:
 220         case PIPE_CAP_PCI_BUS:
 221         case PIPE_CAP_PCI_DEVICE:
 222         case PIPE_CAP_PCI_FUNCTION:
 223                 return 0;
 224
 225         case PIPE_CAP_SM3:
 226         case PIPE_CAP_PRIMITIVE_RESTART:
 227         case PIPE_CAP_TGSI_INSTANCEID:
 228         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 229         case PIPE_CAP_INDEP_BLEND_ENABLE:
 230         case PIPE_CAP_INDEP_BLEND_FUNC:
 231         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 232         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 233         case PIPE_CAP_CONDITIONAL_RENDER:
 234         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 235         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 236         case PIPE_CAP_CLIP_HALFZ:
 237                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 238
 239         case PIPE_CAP_FAKE_SW_MSAA:
 240                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 241
 242         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 243                 return is_a5xx(screen) || is_a6xx(screen);
 244
 245         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 246                 return is_a3xx(screen) || is_a4xx(screen);
 247
 248         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 249                 return is_a5xx(screen) || is_a6xx(screen);
 250
 251         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 252                 return 0;
 253         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 254                 if (is_a3xx(screen)) return 16;
 255                 if (is_a4xx(screen)) return 32;
 256                 if (is_a5xx(screen)) return 32;
 257                 if (is_a6xx(screen)) return 32;
 258                 return 0;
 259         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 260                 /* We could possibly emulate more by pretending 2d/rect textures and
 261                  * splitting high bits of index into 2nd dimension..
 262                  */
 263                 if (is_a3xx(screen)) return 8192;
 264                 if (is_a4xx(screen)) return 16384;
 265                 if (is_a5xx(screen)) return 16384;
 266                 if (is_a6xx(screen)) return 16384;
 267                 return 0;
 268
 269         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 270         case PIPE_CAP_CUBE_MAP_ARRAY:
 271         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 272         case PIPE_CAP_TEXTURE_QUERY_LOD:
 273                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 274
 275         case PIPE_CAP_START_INSTANCE:
 276                 /* Note that a5xx can do this, it just can't (at least with
 277                  * current firmware) do draw_indirect with base_instance.
 278                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 279                  * gl42), hide base_instance on a5xx.  :-/
 280                  */
 281                 return is_a4xx(screen);
 282
 283         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 284                 return 64;
 285
 286         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 287         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 288                 if (glsl120)
 289                         return 120;
 290                 return is_ir3(screen) ? 140 : 120;
 291
 292         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 293                 if (is_a5xx(screen) || is_a6xx(screen))
 294                         return 4;
 295                 return 0;
 296
 297         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 298                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 299                         return 4;
 300                 return 0;
 301
 302         /* Unsupported features. */
 303         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 304         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 305         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 306         case PIPE_CAP_USER_VERTEX_BUFFERS:
 307         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 308         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 309         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 310         case PIPE_CAP_TEXTURE_GATHER_SM5:
 311         case PIPE_CAP_SAMPLE_SHADING:
 312         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 313         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 314         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 315         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 316         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 317         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 318         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 319         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 320         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 321         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 322         case PIPE_CAP_TGSI_TXQS:
 323         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 324         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 325         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 326         case PIPE_CAP_CLEAR_TEXTURE:
 327         case PIPE_CAP_DRAW_PARAMETERS:
 328         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 329         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 330         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 331         case PIPE_CAP_GENERATE_MIPMAP:
 332         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 333         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 334         case PIPE_CAP_CULL_DISTANCE:
 335         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 336         case PIPE_CAP_TGSI_VOTE:
 337         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 338         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 339         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 340         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 341         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 342         case PIPE_CAP_TGSI_FS_FBFETCH:
 343         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 344         case PIPE_CAP_DOUBLES:
 345         case PIPE_CAP_INT64:
 346         case PIPE_CAP_INT64_DIVMOD:
 347         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 348         case PIPE_CAP_TGSI_CLOCK:
 349         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 350         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 351         case PIPE_CAP_TGSI_BALLOT:
 352         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 353         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 354         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 355         case PIPE_CAP_POST_DEPTH_COVERAGE:
 356         case PIPE_CAP_BINDLESS_TEXTURE:
 357         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 358         case PIPE_CAP_QUERY_SO_OVERFLOW:
 359         case PIPE_CAP_MEMOBJ:
 360         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 361         case PIPE_CAP_TILE_RASTER_ORDER:
 362         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 363         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 364         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 365         case PIPE_CAP_FENCE_SIGNAL:
 366         case PIPE_CAP_CONSTBUF0_FLAGS:
 367         case PIPE_CAP_PACKED_UNIFORMS:
 368         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 369         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 370         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 371         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 372         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 373         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 374         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 375                 return 0;
 376
 377         case PIPE_CAP_MAX_GS_INVOCATIONS:
 378                 return 32;
 379
 380         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 381                 return 1 << 27;
 382
 383         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 384                 return screen->priority_mask;
 385
 386         case PIPE_CAP_DRAW_INDIRECT:
 387                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 388                         return 1;
 389                 return 0;
 390
 391         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 392                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 393                         return 1;
 394                 return 0;
 395
 396         case PIPE_CAP_LOAD_CONSTBUF:
 397                 /* name is confusing, but this turns on std430 packing */
 398                 if (is_ir3(screen))
 399                         return 1;
 400                 return 0;
 401
 402         case PIPE_CAP_MAX_VIEWPORTS:
 403                 return 1;
 404
 405         case PIPE_CAP_SHAREABLE_SHADERS:
 406         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 407         /* manage the variants for these ourself, to avoid breaking precompile: */
 408         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 409         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 410                 if (is_ir3(screen))
 411                         return 1;
 412                 return 0;
 413
 414         /* Stream output. */
 415         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 416                 if (is_ir3(screen))
 417                         return PIPE_MAX_SO_BUFFERS;
 418                 return 0;
 419         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 420         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 421                 if (is_ir3(screen))
 422                         return 1;
 423                 return 0;
 424         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 425         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 426                 if (is_ir3(screen))
 427                         return 16 * 4;   /* should only be shader out limit? */
 428                 return 0;
 429
 430         /* Geometry shader output, unsupported. */
 431         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 432         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 433         case PIPE_CAP_MAX_VERTEX_STREAMS:
 434                 return 0;
 435
 436         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 437                 return 2048;
 438
 439         /* Texturing. */
 440         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 441         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 442                 return MAX_MIP_LEVELS;
 443         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 444                 return 11;
 445
 446         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 447                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 448
 449         /* Render targets. */
 450         case PIPE_CAP_MAX_RENDER_TARGETS:
 451                 return screen->max_rts;
 452         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 453                 return is_a3xx(screen) ? 1 : 0;
 454
 455         /* Queries. */
 456         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 457                 return 0;
 458         case PIPE_CAP_OCCLUSION_QUERY:
 459                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 460         case PIPE_CAP_QUERY_TIMESTAMP:
 461         case PIPE_CAP_QUERY_TIME_ELAPSED:
 462                 /* only a4xx, requires new enough kernel so we know max_freq: */
 463                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 464
 465         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 466         case PIPE_CAP_MIN_TEXEL_OFFSET:
 467                 return -8;
 468
 469         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 470         case PIPE_CAP_MAX_TEXEL_OFFSET:
 471                 return 7;
 472
 473         case PIPE_CAP_ENDIANNESS:
 474                 return PIPE_ENDIAN_LITTLE;
 475
 476         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 477                 return 64;
 478
 479         case PIPE_CAP_VENDOR_ID:
 480                 return 0x5143;
 481         case PIPE_CAP_DEVICE_ID:
 482                 return 0xFFFFFFFF;
 483         case PIPE_CAP_ACCELERATED:
 484                 return 1;
 485         case PIPE_CAP_VIDEO_MEMORY:
 486                 DBG("FINISHME: The value returned is incorrect\n");
 487                 return 10;
 488         case PIPE_CAP_UMA:
 489                 return 1;
 490         case PIPE_CAP_NATIVE_FENCE_FD:
 491                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 492         default:
 493                 return u_pipe_screen_get_param_defaults(pscreen, param);
 494         }
 495 }
 496
 497 static float
 498 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 499 {
 500         switch (param) {
 501         case PIPE_CAPF_MAX_LINE_WIDTH:
 502         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 503                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 504                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 505                  * uses too small of a render target size, and gets confused when
 506                  * the lines start going offscreen.
 507                  *
 508                  * See: https://code.google.com/p/android/issues/detail?id=206513
 509                  */
 510                 if (fd_mesa_debug & FD_DBG_DEQP)
 511                         return 48.0f;
 512                 return 127.0f;
 513         case PIPE_CAPF_MAX_POINT_WIDTH:
 514         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 515                 return 4092.0f;
 516         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 517                 return 16.0f;
 518         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 519                 return 15.0f;
 520         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 521         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 522         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 523                 return 0.0f;
 524         }
 525         debug_printf("unknown paramf %d\n", param);
 526         return 0;
 527 }
 528
 529 static int
 530 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 531                 enum pipe_shader_type shader,
 532                 enum pipe_shader_cap param)
 533 {
 534         struct fd_screen *screen = fd_screen(pscreen);
 535
 536         switch(shader)
 537         {
 538         case PIPE_SHADER_FRAGMENT:
 539         case PIPE_SHADER_VERTEX:
 540                 break;
 541         case PIPE_SHADER_COMPUTE:
 542                 if (has_compute(screen))
 543                         break;
 544                 return 0;
 545         case PIPE_SHADER_GEOMETRY:
 546                 /* maye we could emulate.. */
 547                 return 0;
 548         default:
 549                 DBG("unknown shader type %d", shader);
 550                 return 0;
 551         }
 552
 553         /* this is probably not totally correct.. but it's a start: */
 554         switch (param) {
 555         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 556         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 557         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 558         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 559                 return 16384;
 560         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 561                 return 8; /* XXX */
 562         case PIPE_SHADER_CAP_MAX_INPUTS:
 563         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 564                 return 16;
 565         case PIPE_SHADER_CAP_MAX_TEMPS:
 566                 return 64; /* Max native temporaries. */
 567         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 568                 /* NOTE: seems to be limit for a3xx is actually 512 but
 569                  * split between VS and FS.  Use lower limit of 256 to
 570                  * avoid getting into impossible situations:
 571                  */
 572                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 573         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 574                 return is_ir3(screen) ? 16 : 1;
 575         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 576                 return 1;
 577         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 578         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 579                 /* Technically this should be the same as for TEMP/CONST, since
 580                  * everything is just normal registers.  This is just temporary
 581                  * hack until load_input/store_output handle arrays in a similar
 582                  * way as load_var/store_var..
 583                  */
 584                 return 0;
 585         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 586         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 587                 /* a2xx compiler doesn't handle indirect: */
 588                 return is_ir3(screen) ? 1 : 0;
 589         case PIPE_SHADER_CAP_SUBROUTINES:
 590         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 591         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 592         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 593         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 594         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 595         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 596         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 597         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 598         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 599                 return 0;
 600         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 601                 return 1;
 602         case PIPE_SHADER_CAP_INTEGERS:
 603                 if (glsl120)
 604                         return 0;
 605                 return is_ir3(screen) ? 1 : 0;
 606         case PIPE_SHADER_CAP_INT64_ATOMICS:
 607                 return 0;
 608         case PIPE_SHADER_CAP_FP16:
 609                 return 0;
 610         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 611         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 612                 return 16;
 613         case PIPE_SHADER_CAP_PREFERRED_IR:
 614                 if (is_ir3(screen))
 615                         return PIPE_SHADER_IR_NIR;
 616                 return PIPE_SHADER_IR_TGSI;
 617         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 618                 if (is_ir3(screen)) {
 619                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 620                 } else {
 621                         return (1 << PIPE_SHADER_IR_TGSI);
 622                 }
 623                 return 0;
 624         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 625                 return 32;
 626         case PIPE_SHADER_CAP_SCALAR_ISA:
 627                 return is_ir3(screen) ? 1 : 0;
 628         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 629         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 630                 if (is_a5xx(screen) || is_a6xx(screen)) {
 631                         /* a5xx (and a4xx for that matter) has one state-block
 632                          * for compute-shader SSBO's and another that is shared
 633                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 634                          * just advertise SSBOs for FS and CS.  We could possibly
 635                          * do what blob does, and partition the space for
 636                          * VS/HS/DS/GS/FS.  The blob advertises:
 637                          *
 638                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 639                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 640                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 641                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 642                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 643                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 644                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 645                          *
 646                          * I think that way we could avoid having to patch shaders
 647                          * for actual SSBO indexes by using a static partitioning.
 648                          *
 649                          * Note same state block is used for images and buffers,
 650                          * but images also need texture state for read access
 651                          * (isam/isam.3d)
 652                          */
 653                         switch(shader)
 654                         {
 655                         case PIPE_SHADER_FRAGMENT:
 656                         case PIPE_SHADER_COMPUTE:
 657                                 return 24;
 658                         default:
 659                                 return 0;
 660                         }
 661                 }
 662                 return 0;
 663         }
 664         debug_printf("unknown shader param %d\n", param);
 665         return 0;
 666 }
 667
 668 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 669  * into per-generation backend?
 670  */
 671 static int
 672 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 673                 enum pipe_compute_cap param, void *ret)
 674 {
 675         struct fd_screen *screen = fd_screen(pscreen);
 676         const char * const ir = "ir3";
 677
 678         if (!has_compute(screen))
 679                 return 0;
 680
 681 #define RET(x) do {                  \
 682    if (ret)                          \
 683       memcpy(ret, x, sizeof(x));     \
 684    return sizeof(x);                 \
 685 } while (0)
 686
 687         switch (param) {
 688         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 689 // don't expose 64b pointer support yet, until ir3 supports 64b
 690 // math, otherwise spir64 target is used and we get 64b pointer
 691 // calculations that we can't do yet
 692 //              if (is_a5xx(screen))
 693 //                      RET((uint32_t []){ 64 });
 694                 RET((uint32_t []){ 32 });
 695
 696         case PIPE_COMPUTE_CAP_IR_TARGET:
 697                 if (ret)
 698                         sprintf(ret, ir);
 699                 return strlen(ir) * sizeof(char);
 700
 701         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 702                 RET((uint64_t []) { 3 });
 703
 704         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 705                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 706
 707         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 708                 RET(((uint64_t []) { 1024, 1024, 64 }));
 709
 710         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 711                 RET((uint64_t []) { 1024 });
 712
 713         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 714                 RET((uint64_t []) { screen->ram_size });
 715
 716         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 717                 RET((uint64_t []) { 32768 });
 718
 719         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 720         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 721                 RET((uint64_t []) { 4096 });
 722
 723         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 724                 RET((uint64_t []) { screen->ram_size });
 725
 726         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 727                 RET((uint32_t []) { screen->max_freq / 1000000 });
 728
 729         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 730                 RET((uint32_t []) { 9999 });  // TODO
 731
 732         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 733                 RET((uint32_t []) { 1 });
 734
 735         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 736                 RET((uint32_t []) { 32 });  // TODO
 737
 738         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 739                 RET((uint64_t []) { 1024 }); // TODO
 740         }
 741
 742         return 0;
 743 }
 744
 745 static const void *
 746 fd_get_compiler_options(struct pipe_screen *pscreen,
 747                 enum pipe_shader_ir ir, unsigned shader)
 748 {
 749         struct fd_screen *screen = fd_screen(pscreen);
 750
 751         if (is_ir3(screen))
 752                 return ir3_get_compiler_options(screen->compiler);
 753
 754         return NULL;
 755 }
 756
 757 boolean
 758 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 759                 struct fd_bo *bo,
 760                 unsigned stride,
 761                 struct winsys_handle *whandle)
 762 {
 763         whandle->stride = stride;
 764
 765         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 766                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 767         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 768                 whandle->handle = fd_bo_handle(bo);
 769                 return TRUE;
 770         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 771                 whandle->handle = fd_bo_dmabuf(bo);
 772                 return TRUE;
 773         } else {
 774                 return FALSE;
 775         }
 776 }
 777
 778 struct fd_bo *
 779 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 780                 struct winsys_handle *whandle)
 781 {
 782         struct fd_screen *screen = fd_screen(pscreen);
 783         struct fd_bo *bo;
 784
 785         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 786                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 787         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 788                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 789         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 790                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 791         } else {
 792                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 793                 return NULL;
 794         }
 795
 796         if (!bo) {
 797                 DBG("ref name 0x%08x failed", whandle->handle);
 798                 return NULL;
 799         }
 800
 801         return bo;
 802 }
 803
 804 struct pipe_screen *
 805 fd_screen_create(struct fd_device *dev)
 806 {
 807         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 808         struct pipe_screen *pscreen;
 809         uint64_t val;
 810
 811         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 812         fd_shader_debug = debug_get_option_fd_shader_debug();
 813
 814         if (fd_mesa_debug & FD_DBG_NOBIN)
 815                 fd_binning_enabled = false;
 816
 817         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 818
 819         if (!screen)
 820                 return NULL;
 821
 822         pscreen = &screen->base;
 823
 824         screen->dev = dev;
 825         screen->refcnt = 1;
 826
 827         // maybe this should be in context?
 828         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 829         if (!screen->pipe) {
 830                 DBG("could not create 3d pipe");
 831                 goto fail;
 832         }
 833
 834         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 835                 DBG("could not get GMEM size");
 836                 goto fail;
 837         }
 838         screen->gmemsize_bytes = val;
 839
 840         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 841                 DBG("could not get device-id");
 842                 goto fail;
 843         }
 844         screen->device_id = val;
 845
 846         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 847                 DBG("could not get gpu freq");
 848                 /* this limits what performance related queries are
 849                  * supported but is not fatal
 850                  */
 851                 screen->max_freq = 0;
 852         } else {
 853                 screen->max_freq = val;
 854                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 855                         screen->has_timestamp = true;
 856         }
 857
 858         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 859                 DBG("could not get gpu-id");
 860                 goto fail;
 861         }
 862         screen->gpu_id = val;
 863
 864         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 865                 DBG("could not get chip-id");
 866                 /* older kernels may not have this property: */
 867                 unsigned core  = screen->gpu_id / 100;
 868                 unsigned major = (screen->gpu_id % 100) / 10;
 869                 unsigned minor = screen->gpu_id % 10;
 870                 unsigned patch = 0;  /* assume the worst */
 871                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 872                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 873         }
 874         screen->chip_id = val;
 875
 876         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 877                 DBG("could not get # of rings");
 878                 screen->priority_mask = 0;
 879         } else {
 880                 /* # of rings equates to number of unique priority values: */
 881                 screen->priority_mask = (1 << val) - 1;
 882         }
 883
 884         struct sysinfo si;
 885         sysinfo(&si);
 886         screen->ram_size = si.totalram;
 887
 888         DBG("Pipe Info:");
 889         DBG(" GPU-id:          %d", screen->gpu_id);
 890         DBG(" Chip-id:         0x%08x", screen->chip_id);
 891         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 892
 893         /* explicitly checking for GPU revisions that are known to work.  This
 894          * may be overly conservative for a3xx, where spoofing the gpu_id with
 895          * the blob driver seems to generate identical cmdstream dumps.  But
 896          * on a2xx, there seem to be small differences between the GPU revs
 897          * so it is probably better to actually test first on real hardware
 898          * before enabling:
 899          *
 900          * If you have a different adreno version, feel free to add it to one
 901          * of the cases below and see what happens.  And if it works, please
 902          * send a patch ;-)
 903          */
 904         switch (screen->gpu_id) {
 905         case 205:
 906         case 220:
 907                 fd2_screen_init(pscreen);
 908                 break;
 909         case 305:
 910         case 307:
 911         case 320:
 912         case 330:
 913                 fd3_screen_init(pscreen);
 914                 break;
 915         case 420:
 916         case 430:
 917                 fd4_screen_init(pscreen);
 918                 break;
 919         case 530:
 920                 fd5_screen_init(pscreen);
 921                 break;
 922         case 630:
 923                 fd6_screen_init(pscreen);
 924                 break;
 925         default:
 926                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 927                 goto fail;
 928         }
 929
 930         if (screen->gpu_id >= 500) {
 931                 screen->gmem_alignw = 64;
 932                 screen->gmem_alignh = 32;
 933                 screen->num_vsc_pipes = 16;
 934         } else {
 935                 screen->gmem_alignw = 32;
 936                 screen->gmem_alignh = 32;
 937                 screen->num_vsc_pipes = 8;
 938         }
 939
 940         /* NOTE: don't enable reordering on a2xx, since completely untested.
 941          * Also, don't enable if we have too old of a kernel to support
 942          * growable cmdstream buffers, since memory requirement for cmdstream
 943          * buffers would be too much otherwise.
 944          */
 945         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 946                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 947
 948         fd_bc_init(&screen->batch_cache);
 949
 950         (void) mtx_init(&screen->lock, mtx_plain);
 951
 952         pscreen->destroy = fd_screen_destroy;
 953         pscreen->get_param = fd_screen_get_param;
 954         pscreen->get_paramf = fd_screen_get_paramf;
 955         pscreen->get_shader_param = fd_screen_get_shader_param;
 956         pscreen->get_compute_param = fd_get_compute_param;
 957         pscreen->get_compiler_options = fd_get_compiler_options;
 958
 959         fd_resource_screen_init(pscreen);
 960         fd_query_screen_init(pscreen);
 961
 962         pscreen->get_name = fd_screen_get_name;
 963         pscreen->get_vendor = fd_screen_get_vendor;
 964         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 965
 966         pscreen->get_timestamp = fd_screen_get_timestamp;
 967
 968         pscreen->fence_reference = fd_fence_ref;
 969         pscreen->fence_finish = fd_fence_finish;
 970         pscreen->fence_get_fd = fd_fence_get_fd;
 971
 972         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 973
 974         return pscreen;
 975
 976 fail:
 977         fd_screen_destroy(pscreen);
 978         return NULL;
 979 }