src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  81                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  82                 DEBUG_NAMED_VALUE_END
  83 };
  84
  85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  86
  87 int fd_mesa_debug = 0;
  88 bool fd_binning_enabled = true;
  89 static bool glsl120 = false;
  90
  91 static const char *
  92 fd_screen_get_name(struct pipe_screen *pscreen)
  93 {
  94         static char buffer[128];
  95         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  96                         fd_screen(pscreen)->device_id);
  97         return buffer;
  98 }
  99
 100 static const char *
 101 fd_screen_get_vendor(struct pipe_screen *pscreen)
 102 {
 103         return "freedreno";
 104 }
 105
 106 static const char *
 107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 108 {
 109         return "Qualcomm";
 110 }
 111
 112
 113 static uint64_t
 114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 115 {
 116         struct fd_screen *screen = fd_screen(pscreen);
 117
 118         if (screen->has_timestamp) {
 119                 uint64_t n;
 120                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 121                 debug_assert(screen->max_freq > 0);
 122                 return n * 1000000000 / screen->max_freq;
 123         } else {
 124                 int64_t cpu_time = os_time_get() * 1000;
 125                 return cpu_time + screen->cpu_gpu_time_delta;
 126         }
 127
 128 }
 129
 130 static void
 131 fd_screen_destroy(struct pipe_screen *pscreen)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         if (screen->pipe)
 136                 fd_pipe_del(screen->pipe);
 137
 138         if (screen->dev)
 139                 fd_device_del(screen->dev);
 140
 141         fd_bc_fini(&screen->batch_cache);
 142
 143         slab_destroy_parent(&screen->transfer_pool);
 144
 145         mtx_destroy(&screen->lock);
 146
 147         ralloc_free(screen->compiler);
 148
 149         free(screen);
 150 }
 151
 152 /*
 153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 154 tables for things that differ if the delta is not too much..
 155  */
 156 static int
 157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 158 {
 159         struct fd_screen *screen = fd_screen(pscreen);
 160
 161         /* this is probably not totally correct.. but it's a start: */
 162         switch (param) {
 163         /* Supported features (boolean caps). */
 164         case PIPE_CAP_NPOT_TEXTURES:
 165         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 166         case PIPE_CAP_TWO_SIDED_STENCIL:
 167         case PIPE_CAP_ANISOTROPIC_FILTER:
 168         case PIPE_CAP_POINT_SPRITE:
 169         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 170         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 171         case PIPE_CAP_TEXTURE_SWIZZLE:
 172         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 174         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 175         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 176         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 177         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 178         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 179         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 180         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 182         case PIPE_CAP_STRING_MARKER:
 183         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 184         case PIPE_CAP_TEXTURE_BARRIER:
 185         case PIPE_CAP_INVALIDATE_BUFFER:
 186                 return 1;
 187
 188         case PIPE_CAP_VERTEXID_NOBASE:
 189                 return is_a3xx(screen) || is_a4xx(screen);
 190
 191         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 192                 return is_a4xx(screen) ? 0 : 1;
 193
 194         case PIPE_CAP_COMPUTE:
 195                 return has_compute(screen);
 196
 197         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 198         case PIPE_CAP_TGSI_TEXCOORD:
 199         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 200         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 201         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 202         case PIPE_CAP_QUERY_MEMORY_INFO:
 203         case PIPE_CAP_PCI_GROUP:
 204         case PIPE_CAP_PCI_BUS:
 205         case PIPE_CAP_PCI_DEVICE:
 206         case PIPE_CAP_PCI_FUNCTION:
 207                 return 0;
 208
 209         case PIPE_CAP_SM3:
 210         case PIPE_CAP_PRIMITIVE_RESTART:
 211         case PIPE_CAP_TGSI_INSTANCEID:
 212         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 213         case PIPE_CAP_INDEP_BLEND_ENABLE:
 214         case PIPE_CAP_INDEP_BLEND_FUNC:
 215         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 216         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 217         case PIPE_CAP_CONDITIONAL_RENDER:
 218         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 219         case PIPE_CAP_FAKE_SW_MSAA:
 220         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 221         case PIPE_CAP_CLIP_HALFZ:
 222                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 223
 224         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 225                 return is_a3xx(screen) || is_a4xx(screen);
 226
 227         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 228                 return is_a5xx(screen);
 229
 230         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 231                 return 0;
 232         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 233                 if (is_a3xx(screen)) return 16;
 234                 if (is_a4xx(screen)) return 32;
 235                 if (is_a5xx(screen)) return 32;
 236                 return 0;
 237         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 238                 /* We could possibly emulate more by pretending 2d/rect textures and
 239                  * splitting high bits of index into 2nd dimension..
 240                  */
 241                 if (is_a3xx(screen)) return 8192;
 242                 if (is_a4xx(screen)) return 16384;
 243                 if (is_a5xx(screen)) return 16384;
 244                 return 0;
 245
 246         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 247         case PIPE_CAP_CUBE_MAP_ARRAY:
 248         case PIPE_CAP_START_INSTANCE:
 249         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 250         case PIPE_CAP_TEXTURE_QUERY_LOD:
 251                 return is_a4xx(screen) || is_a5xx(screen);
 252
 253         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 254                 return 64;
 255
 256         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 257                 if (glsl120)
 258                         return 120;
 259                 return is_ir3(screen) ? 140 : 120;
 260
 261         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 262                 if (is_a5xx(screen))
 263                         return 4;
 264                 return 0;
 265
 266         /* Unsupported features. */
 267         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 268         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 269         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 270         case PIPE_CAP_USER_VERTEX_BUFFERS:
 271         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 272         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 273         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 274         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 275         case PIPE_CAP_TEXTURE_GATHER_SM5:
 276         case PIPE_CAP_SAMPLE_SHADING:
 277         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 278         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 279         case PIPE_CAP_DRAW_INDIRECT:
 280         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 281         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 282         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 283         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 284         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 285         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 286         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 287         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 288         case PIPE_CAP_TGSI_TXQS:
 289         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 290         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 291         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 292         case PIPE_CAP_CLEAR_TEXTURE:
 293         case PIPE_CAP_DRAW_PARAMETERS:
 294         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 295         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 296         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 297         case PIPE_CAP_GENERATE_MIPMAP:
 298         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 299         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 300         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 301         case PIPE_CAP_CULL_DISTANCE:
 302         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 303         case PIPE_CAP_TGSI_VOTE:
 304         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 305         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 306         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 307         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 308         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 309         case PIPE_CAP_TGSI_FS_FBFETCH:
 310         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 311         case PIPE_CAP_DOUBLES:
 312         case PIPE_CAP_INT64:
 313         case PIPE_CAP_INT64_DIVMOD:
 314         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 315         case PIPE_CAP_TGSI_CLOCK:
 316         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 317         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 318         case PIPE_CAP_TGSI_BALLOT:
 319         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 320         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 321         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 322         case PIPE_CAP_POST_DEPTH_COVERAGE:
 323         case PIPE_CAP_BINDLESS_TEXTURE:
 324         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 325         case PIPE_CAP_QUERY_SO_OVERFLOW:
 326         case PIPE_CAP_MEMOBJ:
 327         case PIPE_CAP_LOAD_CONSTBUF:
 328         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 329         case PIPE_CAP_TILE_RASTER_ORDER:
 330         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 331         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 332                 return 0;
 333
 334         case PIPE_CAP_MAX_VIEWPORTS:
 335                 return 1;
 336
 337         case PIPE_CAP_SHAREABLE_SHADERS:
 338         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 339         /* manage the variants for these ourself, to avoid breaking precompile: */
 340         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 341         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 342                 if (is_ir3(screen))
 343                         return 1;
 344                 return 0;
 345
 346         /* Stream output. */
 347         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 348                 if (is_ir3(screen))
 349                         return PIPE_MAX_SO_BUFFERS;
 350                 return 0;
 351         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 352         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 353                 if (is_ir3(screen))
 354                         return 1;
 355                 return 0;
 356         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 357         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 358                 if (is_ir3(screen))
 359                         return 16 * 4;   /* should only be shader out limit? */
 360                 return 0;
 361
 362         /* Geometry shader output, unsupported. */
 363         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 364         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 365         case PIPE_CAP_MAX_VERTEX_STREAMS:
 366                 return 0;
 367
 368         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 369                 return 2048;
 370
 371         /* Texturing. */
 372         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 373         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 374                 return MAX_MIP_LEVELS;
 375         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 376                 return 11;
 377
 378         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 379                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 380
 381         /* Render targets. */
 382         case PIPE_CAP_MAX_RENDER_TARGETS:
 383                 return screen->max_rts;
 384         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 385                 return is_a3xx(screen) ? 1 : 0;
 386
 387         /* Queries. */
 388         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 389                 return 0;
 390         case PIPE_CAP_OCCLUSION_QUERY:
 391                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 392         case PIPE_CAP_QUERY_TIMESTAMP:
 393         case PIPE_CAP_QUERY_TIME_ELAPSED:
 394                 /* only a4xx, requires new enough kernel so we know max_freq: */
 395                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 396
 397         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 398         case PIPE_CAP_MIN_TEXEL_OFFSET:
 399                 return -8;
 400
 401         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 402         case PIPE_CAP_MAX_TEXEL_OFFSET:
 403                 return 7;
 404
 405         case PIPE_CAP_ENDIANNESS:
 406                 return PIPE_ENDIAN_LITTLE;
 407
 408         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 409                 return 64;
 410
 411         case PIPE_CAP_VENDOR_ID:
 412                 return 0x5143;
 413         case PIPE_CAP_DEVICE_ID:
 414                 return 0xFFFFFFFF;
 415         case PIPE_CAP_ACCELERATED:
 416                 return 1;
 417         case PIPE_CAP_VIDEO_MEMORY:
 418                 DBG("FINISHME: The value returned is incorrect\n");
 419                 return 10;
 420         case PIPE_CAP_UMA:
 421                 return 1;
 422         case PIPE_CAP_NATIVE_FENCE_FD:
 423                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 424         }
 425         debug_printf("unknown param %d\n", param);
 426         return 0;
 427 }
 428
 429 static float
 430 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 431 {
 432         switch (param) {
 433         case PIPE_CAPF_MAX_LINE_WIDTH:
 434         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 435                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 436                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 437                  * uses too small of a render target size, and gets confused when
 438                  * the lines start going offscreen.
 439                  *
 440                  * See: https://code.google.com/p/android/issues/detail?id=206513
 441                  */
 442                 if (fd_mesa_debug & FD_DBG_DEQP)
 443                         return 48.0f;
 444                 return 127.0f;
 445         case PIPE_CAPF_MAX_POINT_WIDTH:
 446         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 447                 return 4092.0f;
 448         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 449                 return 16.0f;
 450         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 451                 return 15.0f;
 452         case PIPE_CAPF_GUARD_BAND_LEFT:
 453         case PIPE_CAPF_GUARD_BAND_TOP:
 454         case PIPE_CAPF_GUARD_BAND_RIGHT:
 455         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 456                 return 0.0f;
 457         }
 458         debug_printf("unknown paramf %d\n", param);
 459         return 0;
 460 }
 461
 462 static int
 463 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 464                 enum pipe_shader_type shader,
 465                 enum pipe_shader_cap param)
 466 {
 467         struct fd_screen *screen = fd_screen(pscreen);
 468
 469         switch(shader)
 470         {
 471         case PIPE_SHADER_FRAGMENT:
 472         case PIPE_SHADER_VERTEX:
 473                 break;
 474         case PIPE_SHADER_COMPUTE:
 475                 if (has_compute(screen))
 476                         break;
 477                 return 0;
 478         case PIPE_SHADER_GEOMETRY:
 479                 /* maye we could emulate.. */
 480                 return 0;
 481         default:
 482                 DBG("unknown shader type %d", shader);
 483                 return 0;
 484         }
 485
 486         /* this is probably not totally correct.. but it's a start: */
 487         switch (param) {
 488         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 489         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 490         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 491         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 492                 return 16384;
 493         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 494                 return 8; /* XXX */
 495         case PIPE_SHADER_CAP_MAX_INPUTS:
 496         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 497                 return 16;
 498         case PIPE_SHADER_CAP_MAX_TEMPS:
 499                 return 64; /* Max native temporaries. */
 500         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 501                 /* NOTE: seems to be limit for a3xx is actually 512 but
 502                  * split between VS and FS.  Use lower limit of 256 to
 503                  * avoid getting into impossible situations:
 504                  */
 505                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 506         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 507                 return is_ir3(screen) ? 16 : 1;
 508         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 509                 return 1;
 510         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 511         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 512                 /* Technically this should be the same as for TEMP/CONST, since
 513                  * everything is just normal registers.  This is just temporary
 514                  * hack until load_input/store_output handle arrays in a similar
 515                  * way as load_var/store_var..
 516                  */
 517                 return 0;
 518         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 519         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 520                 /* a2xx compiler doesn't handle indirect: */
 521                 return is_ir3(screen) ? 1 : 0;
 522         case PIPE_SHADER_CAP_SUBROUTINES:
 523         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 524         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 525         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 526         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 527         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 528                 return 0;
 529         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 530                 return 1;
 531         case PIPE_SHADER_CAP_INTEGERS:
 532                 if (glsl120)
 533                         return 0;
 534                 return is_ir3(screen) ? 1 : 0;
 535         case PIPE_SHADER_CAP_INT64_ATOMICS:
 536                 return 0;
 537         case PIPE_SHADER_CAP_FP16:
 538                 return 0;
 539         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 540         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 541                 return 16;
 542         case PIPE_SHADER_CAP_PREFERRED_IR:
 543                 if (is_ir3(screen))
 544                         return PIPE_SHADER_IR_NIR;
 545                 return PIPE_SHADER_IR_TGSI;
 546         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 547                 if (is_ir3(screen)) {
 548                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 549                 } else {
 550                         return (1 << PIPE_SHADER_IR_TGSI);
 551                 }
 552                 return 0;
 553         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 554                 return 32;
 555         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 556         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 557         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 558         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 559                 return 0;
 560         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 561         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 562                 if (is_a5xx(screen)) {
 563                         /* a5xx (and a4xx for that matter) has one state-block
 564                          * for compute-shader SSBO's and another that is shared
 565                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 566                          * just advertise SSBOs for FS and CS.  We could possibly
 567                          * do what blob does, and partition the space for
 568                          * VS/HS/DS/GS/FS.  The blob advertises:
 569                          *
 570                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 571                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 572                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 573                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 574                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 575                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 576                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 577                          *
 578                          * I think that way we could avoid having to patch shaders
 579                          * for actual SSBO indexes by using a static partitioning.
 580                          *
 581                          * Note same state block is used for images and buffers,
 582                          * but images also need texture state for read access
 583                          * (isam/isam.3d)
 584                          */
 585                         switch(shader)
 586                         {
 587                         case PIPE_SHADER_FRAGMENT:
 588                         case PIPE_SHADER_COMPUTE:
 589                                 return 24;
 590                         default:
 591                                 return 0;
 592                         }
 593                 }
 594                 return 0;
 595         }
 596         debug_printf("unknown shader param %d\n", param);
 597         return 0;
 598 }
 599
 600 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 601  * into per-generation backend?
 602  */
 603 static int
 604 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 605                 enum pipe_compute_cap param, void *ret)
 606 {
 607         struct fd_screen *screen = fd_screen(pscreen);
 608         const char * const ir = "ir3";
 609
 610         if (!has_compute(screen))
 611                 return 0;
 612
 613         switch (param) {
 614         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 615                 if (ret) {
 616                         uint32_t *address_bits = ret;
 617                         address_bits[0] = 32;
 618
 619                         if (is_a5xx(screen))
 620                                 address_bits[0] = 64;
 621                 }
 622                 return 1 * sizeof(uint32_t);
 623
 624         case PIPE_COMPUTE_CAP_IR_TARGET:
 625                 if (ret)
 626                         sprintf(ret, ir);
 627                 return strlen(ir) * sizeof(char);
 628
 629         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 630                 if (ret) {
 631                         uint64_t *grid_dimension = ret;
 632                         grid_dimension[0] = 3;
 633                 }
 634                 return 1 * sizeof(uint64_t);
 635
 636         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 637                 if (ret) {
 638                         uint64_t *grid_size = ret;
 639                         grid_size[0] = 65535;
 640                         grid_size[1] = 65535;
 641                         grid_size[2] = 65535;
 642                 }
 643                 return 3 * sizeof(uint64_t) ;
 644
 645         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 646                 if (ret) {
 647                         uint64_t *block_size = ret;
 648                         block_size[0] = 1024;
 649                         block_size[1] = 1024;
 650                         block_size[2] = 64;
 651                 }
 652                 return 3 * sizeof(uint64_t) ;
 653
 654         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 655                 if (ret) {
 656                         uint64_t *max_threads_per_block = ret;
 657                         *max_threads_per_block = 1024;
 658                 }
 659                 return sizeof(uint64_t);
 660
 661         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 662         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 663         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 664         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 665                 break;
 666         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 667                 if (ret) {
 668                         uint64_t *max = ret;
 669                         *max = 32768;
 670                 }
 671                 return sizeof(uint64_t);
 672         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 673         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 674         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 675         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 676         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 677                 break;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static const void *
 684 fd_get_compiler_options(struct pipe_screen *pscreen,
 685                 enum pipe_shader_ir ir, unsigned shader)
 686 {
 687         struct fd_screen *screen = fd_screen(pscreen);
 688
 689         if (is_ir3(screen))
 690                 return ir3_get_compiler_options(screen->compiler);
 691
 692         return NULL;
 693 }
 694
 695 boolean
 696 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 697                 struct fd_bo *bo,
 698                 unsigned stride,
 699                 struct winsys_handle *whandle)
 700 {
 701         whandle->stride = stride;
 702
 703         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 704                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 705         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 706                 whandle->handle = fd_bo_handle(bo);
 707                 return TRUE;
 708         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 709                 whandle->handle = fd_bo_dmabuf(bo);
 710                 return TRUE;
 711         } else {
 712                 return FALSE;
 713         }
 714 }
 715
 716 struct fd_bo *
 717 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 718                 struct winsys_handle *whandle)
 719 {
 720         struct fd_screen *screen = fd_screen(pscreen);
 721         struct fd_bo *bo;
 722
 723         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 724                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 725         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 726                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 727         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 728                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 729         } else {
 730                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 731                 return NULL;
 732         }
 733
 734         if (!bo) {
 735                 DBG("ref name 0x%08x failed", whandle->handle);
 736                 return NULL;
 737         }
 738
 739         return bo;
 740 }
 741
 742 struct pipe_screen *
 743 fd_screen_create(struct fd_device *dev)
 744 {
 745         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 746         struct pipe_screen *pscreen;
 747         uint64_t val;
 748
 749         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 750
 751         if (fd_mesa_debug & FD_DBG_NOBIN)
 752                 fd_binning_enabled = false;
 753
 754         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 755
 756         if (!screen)
 757                 return NULL;
 758
 759         pscreen = &screen->base;
 760
 761         screen->dev = dev;
 762         screen->refcnt = 1;
 763
 764         // maybe this should be in context?
 765         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 766         if (!screen->pipe) {
 767                 DBG("could not create 3d pipe");
 768                 goto fail;
 769         }
 770
 771         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 772                 DBG("could not get GMEM size");
 773                 goto fail;
 774         }
 775         screen->gmemsize_bytes = val;
 776
 777         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 778                 DBG("could not get device-id");
 779                 goto fail;
 780         }
 781         screen->device_id = val;
 782
 783         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 784                 DBG("could not get gpu freq");
 785                 /* this limits what performance related queries are
 786                  * supported but is not fatal
 787                  */
 788                 screen->max_freq = 0;
 789         } else {
 790                 screen->max_freq = val;
 791                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 792                         screen->has_timestamp = true;
 793         }
 794
 795         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 796                 DBG("could not get gpu-id");
 797                 goto fail;
 798         }
 799         screen->gpu_id = val;
 800
 801         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 802                 DBG("could not get chip-id");
 803                 /* older kernels may not have this property: */
 804                 unsigned core  = screen->gpu_id / 100;
 805                 unsigned major = (screen->gpu_id % 100) / 10;
 806                 unsigned minor = screen->gpu_id % 10;
 807                 unsigned patch = 0;  /* assume the worst */
 808                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 809                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 810         }
 811         screen->chip_id = val;
 812
 813         DBG("Pipe Info:");
 814         DBG(" GPU-id:          %d", screen->gpu_id);
 815         DBG(" Chip-id:         0x%08x", screen->chip_id);
 816         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 817
 818         /* explicitly checking for GPU revisions that are known to work.  This
 819          * may be overly conservative for a3xx, where spoofing the gpu_id with
 820          * the blob driver seems to generate identical cmdstream dumps.  But
 821          * on a2xx, there seem to be small differences between the GPU revs
 822          * so it is probably better to actually test first on real hardware
 823          * before enabling:
 824          *
 825          * If you have a different adreno version, feel free to add it to one
 826          * of the cases below and see what happens.  And if it works, please
 827          * send a patch ;-)
 828          */
 829         switch (screen->gpu_id) {
 830         case 220:
 831                 fd2_screen_init(pscreen);
 832                 break;
 833         case 305:
 834         case 307:
 835         case 320:
 836         case 330:
 837                 fd3_screen_init(pscreen);
 838                 break;
 839         case 420:
 840         case 430:
 841                 fd4_screen_init(pscreen);
 842                 break;
 843         case 530:
 844                 fd5_screen_init(pscreen);
 845                 break;
 846         default:
 847                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 848                 goto fail;
 849         }
 850
 851         if (screen->gpu_id >= 500) {
 852                 screen->gmem_alignw = 64;
 853                 screen->gmem_alignh = 32;
 854                 screen->num_vsc_pipes = 16;
 855         } else {
 856                 screen->gmem_alignw = 32;
 857                 screen->gmem_alignh = 32;
 858                 screen->num_vsc_pipes = 8;
 859         }
 860
 861         /* NOTE: don't enable reordering on a2xx, since completely untested.
 862          * Also, don't enable if we have too old of a kernel to support
 863          * growable cmdstream buffers, since memory requirement for cmdstream
 864          * buffers would be too much otherwise.
 865          */
 866         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 867                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 868
 869         fd_bc_init(&screen->batch_cache);
 870
 871         (void) mtx_init(&screen->lock, mtx_plain);
 872
 873         pscreen->destroy = fd_screen_destroy;
 874         pscreen->get_param = fd_screen_get_param;
 875         pscreen->get_paramf = fd_screen_get_paramf;
 876         pscreen->get_shader_param = fd_screen_get_shader_param;
 877         pscreen->get_compute_param = fd_get_compute_param;
 878         pscreen->get_compiler_options = fd_get_compiler_options;
 879
 880         fd_resource_screen_init(pscreen);
 881         fd_query_screen_init(pscreen);
 882
 883         pscreen->get_name = fd_screen_get_name;
 884         pscreen->get_vendor = fd_screen_get_vendor;
 885         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 886
 887         pscreen->get_timestamp = fd_screen_get_timestamp;
 888
 889         pscreen->fence_reference = fd_fence_ref;
 890         pscreen->fence_finish = fd_fence_finish;
 891         pscreen->fence_get_fd = fd_fence_get_fd;
 892
 893         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 894
 895         return pscreen;
 896
 897 fail:
 898         fd_screen_destroy(pscreen);
 899         return NULL;
 900 }