src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  79                 {"reorder",   FD_DBG_REORDER,"Enable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 DEBUG_NAMED_VALUE_END
  82 };
  83
  84 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  85
  86 int fd_mesa_debug = 0;
  87 bool fd_binning_enabled = true;
  88 static bool glsl120 = false;
  89
  90 static const char *
  91 fd_screen_get_name(struct pipe_screen *pscreen)
  92 {
  93         static char buffer[128];
  94         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  95                         fd_screen(pscreen)->device_id);
  96         return buffer;
  97 }
  98
  99 static const char *
 100 fd_screen_get_vendor(struct pipe_screen *pscreen)
 101 {
 102         return "freedreno";
 103 }
 104
 105 static const char *
 106 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 107 {
 108         return "Qualcomm";
 109 }
 110
 111
 112 static uint64_t
 113 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 114 {
 115         struct fd_screen *screen = fd_screen(pscreen);
 116
 117         if (screen->has_timestamp) {
 118                 uint64_t n;
 119                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 120                 debug_assert(screen->max_freq > 0);
 121                 return n * 1000000000 / screen->max_freq;
 122         } else {
 123                 int64_t cpu_time = os_time_get() * 1000;
 124                 return cpu_time + screen->cpu_gpu_time_delta;
 125         }
 126
 127 }
 128
 129 static void
 130 fd_screen_destroy(struct pipe_screen *pscreen)
 131 {
 132         struct fd_screen *screen = fd_screen(pscreen);
 133
 134         if (screen->pipe)
 135                 fd_pipe_del(screen->pipe);
 136
 137         if (screen->dev)
 138                 fd_device_del(screen->dev);
 139
 140         fd_bc_fini(&screen->batch_cache);
 141
 142         slab_destroy_parent(&screen->transfer_pool);
 143
 144         pipe_mutex_destroy(screen->lock);
 145
 146         free(screen);
 147 }
 148
 149 /*
 150 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 151 tables for things that differ if the delta is not too much..
 152  */
 153 static int
 154 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 155 {
 156         struct fd_screen *screen = fd_screen(pscreen);
 157
 158         /* this is probably not totally correct.. but it's a start: */
 159         switch (param) {
 160         /* Supported features (boolean caps). */
 161         case PIPE_CAP_NPOT_TEXTURES:
 162         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 163         case PIPE_CAP_TWO_SIDED_STENCIL:
 164         case PIPE_CAP_ANISOTROPIC_FILTER:
 165         case PIPE_CAP_POINT_SPRITE:
 166         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 167         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 168         case PIPE_CAP_TEXTURE_SWIZZLE:
 169         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 170         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 171         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 172         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 173         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 174         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 175         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 176         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 177         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 178         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 179         case PIPE_CAP_VERTEXID_NOBASE:
 180         case PIPE_CAP_STRING_MARKER:
 181         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 182                 return 1;
 183
 184         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 185                 return is_a4xx(screen) ? 0 : 1;
 186
 187         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 188         case PIPE_CAP_TGSI_TEXCOORD:
 189         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 190         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 191         case PIPE_CAP_TEXTURE_BARRIER:
 192         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 193         case PIPE_CAP_COMPUTE:
 194         case PIPE_CAP_QUERY_MEMORY_INFO:
 195         case PIPE_CAP_PCI_GROUP:
 196         case PIPE_CAP_PCI_BUS:
 197         case PIPE_CAP_PCI_DEVICE:
 198         case PIPE_CAP_PCI_FUNCTION:
 199                 return 0;
 200
 201         case PIPE_CAP_SM3:
 202         case PIPE_CAP_PRIMITIVE_RESTART:
 203         case PIPE_CAP_TGSI_INSTANCEID:
 204         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 205         case PIPE_CAP_INDEP_BLEND_ENABLE:
 206         case PIPE_CAP_INDEP_BLEND_FUNC:
 207         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 209         case PIPE_CAP_CONDITIONAL_RENDER:
 210         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 211         case PIPE_CAP_FAKE_SW_MSAA:
 212         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 213         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 214         case PIPE_CAP_CLIP_HALFZ:
 215                 return is_a3xx(screen) || is_a4xx(screen);
 216
 217         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 218                 return 0;
 219         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 220                 if (is_a3xx(screen)) return 16;
 221                 if (is_a4xx(screen)) return 32;
 222                 return 0;
 223         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 224                 /* We could possibly emulate more by pretending 2d/rect textures and
 225                  * splitting high bits of index into 2nd dimension..
 226                  */
 227                 if (is_a3xx(screen)) return 8192;
 228                 if (is_a4xx(screen)) return 16384;
 229                 return 0;
 230
 231         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 232         case PIPE_CAP_CUBE_MAP_ARRAY:
 233         case PIPE_CAP_START_INSTANCE:
 234         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 235         case PIPE_CAP_TEXTURE_QUERY_LOD:
 236                 return is_a4xx(screen);
 237
 238         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 239                 return 64;
 240
 241         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 242                 if (glsl120)
 243                         return 120;
 244                 return is_ir3(screen) ? 140 : 120;
 245
 246         /* Unsupported features. */
 247         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 248         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 249         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 250         case PIPE_CAP_USER_VERTEX_BUFFERS:
 251         case PIPE_CAP_USER_INDEX_BUFFERS:
 252         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 253         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 254         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 255         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 256         case PIPE_CAP_TEXTURE_GATHER_SM5:
 257         case PIPE_CAP_SAMPLE_SHADING:
 258         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 259         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 260         case PIPE_CAP_DRAW_INDIRECT:
 261         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 262         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 263         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 264         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 265         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 266         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 267         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 268         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 269         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 270         case PIPE_CAP_TGSI_TXQS:
 271         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 272         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 273         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 274         case PIPE_CAP_CLEAR_TEXTURE:
 275         case PIPE_CAP_DRAW_PARAMETERS:
 276         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 277         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 278         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 279         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 280         case PIPE_CAP_INVALIDATE_BUFFER:
 281         case PIPE_CAP_GENERATE_MIPMAP:
 282         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 283         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 284         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 285         case PIPE_CAP_CULL_DISTANCE:
 286         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 287         case PIPE_CAP_TGSI_VOTE:
 288         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 289         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 290         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 291         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 292         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 293                 return 0;
 294
 295         case PIPE_CAP_MAX_VIEWPORTS:
 296                 return 1;
 297
 298         case PIPE_CAP_SHAREABLE_SHADERS:
 299         /* manage the variants for these ourself, to avoid breaking precompile: */
 300         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 301         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 302                 if (is_ir3(screen))
 303                         return 1;
 304                 return 0;
 305
 306         /* Stream output. */
 307         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 308                 if (is_ir3(screen))
 309                         return PIPE_MAX_SO_BUFFERS;
 310                 return 0;
 311         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 312         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 313                 if (is_ir3(screen))
 314                         return 1;
 315                 return 0;
 316         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 317         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 318                 if (is_ir3(screen))
 319                         return 16 * 4;   /* should only be shader out limit? */
 320                 return 0;
 321
 322         /* Geometry shader output, unsupported. */
 323         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 324         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 325         case PIPE_CAP_MAX_VERTEX_STREAMS:
 326                 return 0;
 327
 328         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 329                 return 2048;
 330
 331         /* Texturing. */
 332         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 333         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 334                 return MAX_MIP_LEVELS;
 335         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 336                 return 11;
 337
 338         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 339                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 340
 341         /* Render targets. */
 342         case PIPE_CAP_MAX_RENDER_TARGETS:
 343                 return screen->max_rts;
 344         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 345                 return is_a3xx(screen) ? 1 : 0;
 346
 347         /* Queries. */
 348         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 349                 return 0;
 350         case PIPE_CAP_OCCLUSION_QUERY:
 351                 return is_a3xx(screen) || is_a4xx(screen);
 352         case PIPE_CAP_QUERY_TIMESTAMP:
 353         case PIPE_CAP_QUERY_TIME_ELAPSED:
 354                 /* only a4xx, requires new enough kernel so we know max_freq: */
 355                 return (screen->max_freq > 0) && is_a4xx(screen);
 356
 357         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 358         case PIPE_CAP_MIN_TEXEL_OFFSET:
 359                 return -8;
 360
 361         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 362         case PIPE_CAP_MAX_TEXEL_OFFSET:
 363                 return 7;
 364
 365         case PIPE_CAP_ENDIANNESS:
 366                 return PIPE_ENDIAN_LITTLE;
 367
 368         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 369                 return 64;
 370
 371         case PIPE_CAP_VENDOR_ID:
 372                 return 0x5143;
 373         case PIPE_CAP_DEVICE_ID:
 374                 return 0xFFFFFFFF;
 375         case PIPE_CAP_ACCELERATED:
 376                 return 1;
 377         case PIPE_CAP_VIDEO_MEMORY:
 378                 DBG("FINISHME: The value returned is incorrect\n");
 379                 return 10;
 380         case PIPE_CAP_UMA:
 381                 return 1;
 382         case PIPE_CAP_NATIVE_FENCE_FD:
 383                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 384         }
 385         debug_printf("unknown param %d\n", param);
 386         return 0;
 387 }
 388
 389 static float
 390 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 391 {
 392         switch (param) {
 393         case PIPE_CAPF_MAX_LINE_WIDTH:
 394         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 395                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 396                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 397                  * uses too small of a render target size, and gets confused when
 398                  * the lines start going offscreen.
 399                  *
 400                  * See: https://code.google.com/p/android/issues/detail?id=206513
 401                  */
 402                 if (fd_mesa_debug & FD_DBG_DEQP)
 403                         return 48.0f;
 404                 return 127.0f;
 405         case PIPE_CAPF_MAX_POINT_WIDTH:
 406         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 407                 return 4092.0f;
 408         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 409                 return 16.0f;
 410         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 411                 return 15.0f;
 412         case PIPE_CAPF_GUARD_BAND_LEFT:
 413         case PIPE_CAPF_GUARD_BAND_TOP:
 414         case PIPE_CAPF_GUARD_BAND_RIGHT:
 415         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 416                 return 0.0f;
 417         }
 418         debug_printf("unknown paramf %d\n", param);
 419         return 0;
 420 }
 421
 422 static int
 423 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 424                 enum pipe_shader_cap param)
 425 {
 426         struct fd_screen *screen = fd_screen(pscreen);
 427
 428         switch(shader)
 429         {
 430         case PIPE_SHADER_FRAGMENT:
 431         case PIPE_SHADER_VERTEX:
 432                 break;
 433         case PIPE_SHADER_COMPUTE:
 434         case PIPE_SHADER_GEOMETRY:
 435                 /* maye we could emulate.. */
 436                 return 0;
 437         default:
 438                 DBG("unknown shader type %d", shader);
 439                 return 0;
 440         }
 441
 442         /* this is probably not totally correct.. but it's a start: */
 443         switch (param) {
 444         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 445         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 446         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 447         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 448                 return 16384;
 449         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 450                 return 8; /* XXX */
 451         case PIPE_SHADER_CAP_MAX_INPUTS:
 452         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 453                 return 16;
 454         case PIPE_SHADER_CAP_MAX_TEMPS:
 455                 return 64; /* Max native temporaries. */
 456         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 457                 /* NOTE: seems to be limit for a3xx is actually 512 but
 458                  * split between VS and FS.  Use lower limit of 256 to
 459                  * avoid getting into impossible situations:
 460                  */
 461                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 462         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 463                 return is_ir3(screen) ? 16 : 1;
 464         case PIPE_SHADER_CAP_MAX_PREDS:
 465                 return 0; /* nothing uses this */
 466         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 467                 return 1;
 468         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 469         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 470                 /* Technically this should be the same as for TEMP/CONST, since
 471                  * everything is just normal registers.  This is just temporary
 472                  * hack until load_input/store_output handle arrays in a similar
 473                  * way as load_var/store_var..
 474                  */
 475                 return 0;
 476         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 477         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 478                 /* a2xx compiler doesn't handle indirect: */
 479                 return is_ir3(screen) ? 1 : 0;
 480         case PIPE_SHADER_CAP_SUBROUTINES:
 481         case PIPE_SHADER_CAP_DOUBLES:
 482         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 483         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 484         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 485         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 486                 return 0;
 487         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 488                 return 1;
 489         case PIPE_SHADER_CAP_INTEGERS:
 490                 if (glsl120)
 491                         return 0;
 492                 return is_ir3(screen) ? 1 : 0;
 493         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 494         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 495                 return 16;
 496         case PIPE_SHADER_CAP_PREFERRED_IR:
 497                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 498                         return PIPE_SHADER_IR_NIR;
 499                 return PIPE_SHADER_IR_TGSI;
 500         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 501                 return 0;
 502         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 503                 return 32;
 504         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 505         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 506         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 507                 return 0;
 508         }
 509         debug_printf("unknown shader param %d\n", param);
 510         return 0;
 511 }
 512
 513 static const void *
 514 fd_get_compiler_options(struct pipe_screen *pscreen,
 515                 enum pipe_shader_ir ir, unsigned shader)
 516 {
 517         struct fd_screen *screen = fd_screen(pscreen);
 518
 519         if (is_ir3(screen))
 520                 return ir3_get_compiler_options();
 521
 522         return NULL;
 523 }
 524
 525 boolean
 526 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 527                 struct fd_bo *bo,
 528                 unsigned stride,
 529                 struct winsys_handle *whandle)
 530 {
 531         whandle->stride = stride;
 532
 533         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 534                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 535         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 536                 whandle->handle = fd_bo_handle(bo);
 537                 return TRUE;
 538         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 539                 whandle->handle = fd_bo_dmabuf(bo);
 540                 return TRUE;
 541         } else {
 542                 return FALSE;
 543         }
 544 }
 545
 546 struct fd_bo *
 547 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 548                 struct winsys_handle *whandle)
 549 {
 550         struct fd_screen *screen = fd_screen(pscreen);
 551         struct fd_bo *bo;
 552
 553         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 554                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 555         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 556                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 557         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 558                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 559         } else {
 560                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 561                 return NULL;
 562         }
 563
 564         if (!bo) {
 565                 DBG("ref name 0x%08x failed", whandle->handle);
 566                 return NULL;
 567         }
 568
 569         return bo;
 570 }
 571
 572 struct pipe_screen *
 573 fd_screen_create(struct fd_device *dev)
 574 {
 575         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 576         struct pipe_screen *pscreen;
 577         uint64_t val;
 578
 579         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 580
 581         if (fd_mesa_debug & FD_DBG_NOBIN)
 582                 fd_binning_enabled = false;
 583
 584         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 585
 586         if (!screen)
 587                 return NULL;
 588
 589         pscreen = &screen->base;
 590
 591         screen->dev = dev;
 592         screen->refcnt = 1;
 593
 594         // maybe this should be in context?
 595         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 596         if (!screen->pipe) {
 597                 DBG("could not create 3d pipe");
 598                 goto fail;
 599         }
 600
 601         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 602                 DBG("could not get GMEM size");
 603                 goto fail;
 604         }
 605         screen->gmemsize_bytes = val;
 606
 607         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 608                 DBG("could not get device-id");
 609                 goto fail;
 610         }
 611         screen->device_id = val;
 612
 613         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 614                 DBG("could not get gpu freq");
 615                 /* this limits what performance related queries are
 616                  * supported but is not fatal
 617                  */
 618                 screen->max_freq = 0;
 619         } else {
 620                 screen->max_freq = val;
 621                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 622                         screen->has_timestamp = true;
 623         }
 624
 625         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 626                 DBG("could not get gpu-id");
 627                 goto fail;
 628         }
 629         screen->gpu_id = val;
 630
 631         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 632                 DBG("could not get chip-id");
 633                 /* older kernels may not have this property: */
 634                 unsigned core  = screen->gpu_id / 100;
 635                 unsigned major = (screen->gpu_id % 100) / 10;
 636                 unsigned minor = screen->gpu_id % 10;
 637                 unsigned patch = 0;  /* assume the worst */
 638                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 639                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 640         }
 641         screen->chip_id = val;
 642
 643         DBG("Pipe Info:");
 644         DBG(" GPU-id:          %d", screen->gpu_id);
 645         DBG(" Chip-id:         0x%08x", screen->chip_id);
 646         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 647
 648         /* explicitly checking for GPU revisions that are known to work.  This
 649          * may be overly conservative for a3xx, where spoofing the gpu_id with
 650          * the blob driver seems to generate identical cmdstream dumps.  But
 651          * on a2xx, there seem to be small differences between the GPU revs
 652          * so it is probably better to actually test first on real hardware
 653          * before enabling:
 654          *
 655          * If you have a different adreno version, feel free to add it to one
 656          * of the cases below and see what happens.  And if it works, please
 657          * send a patch ;-)
 658          */
 659         switch (screen->gpu_id) {
 660         case 220:
 661                 fd2_screen_init(pscreen);
 662                 break;
 663         case 305:
 664         case 307:
 665         case 320:
 666         case 330:
 667                 fd3_screen_init(pscreen);
 668                 break;
 669         case 420:
 670         case 430:
 671                 fd4_screen_init(pscreen);
 672                 break;
 673         case 530:
 674                 fd5_screen_init(pscreen);
 675                 break;
 676         default:
 677                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 678                 goto fail;
 679         }
 680
 681         if (screen->gpu_id >= 500) {
 682                 screen->gmem_alignw = 64;
 683                 screen->gmem_alignh = 32;
 684         } else {
 685                 screen->gmem_alignw = 32;
 686                 screen->gmem_alignh = 32;
 687         }
 688
 689         /* NOTE: don't enable reordering on a2xx, since completely untested.
 690          * Also, don't enable if we have too old of a kernel to support
 691          * growable cmdstream buffers, since memory requirement for cmdstream
 692          * buffers would be too much otherwise.
 693          */
 694         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 695                 screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
 696
 697         fd_bc_init(&screen->batch_cache);
 698
 699         pipe_mutex_init(screen->lock);
 700
 701         pscreen->destroy = fd_screen_destroy;
 702         pscreen->get_param = fd_screen_get_param;
 703         pscreen->get_paramf = fd_screen_get_paramf;
 704         pscreen->get_shader_param = fd_screen_get_shader_param;
 705         pscreen->get_compiler_options = fd_get_compiler_options;
 706
 707         fd_resource_screen_init(pscreen);
 708         fd_query_screen_init(pscreen);
 709
 710         pscreen->get_name = fd_screen_get_name;
 711         pscreen->get_vendor = fd_screen_get_vendor;
 712         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 713
 714         pscreen->get_timestamp = fd_screen_get_timestamp;
 715
 716         pscreen->fence_reference = fd_fence_ref;
 717         pscreen->fence_finish = fd_fence_finish;
 718         pscreen->fence_get_fd = fd_fence_get_fd;
 719
 720         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 721
 722         util_format_s3tc_init();
 723
 724         return pscreen;
 725
 726 fail:
 727         fd_screen_destroy(pscreen);
 728         return NULL;
 729 }