src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 /* XXX this should go away */
  58 #include "state_tracker/drm_driver.h"
  59
  60 static const struct debug_named_value debug_options[] = {
  61                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  62                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  63                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  64                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  65                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  66                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  67                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  68                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  69                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  71                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  72                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  73                 DEBUG_NAMED_VALUE_END
  74 };
  75
  76 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  77
  78 int fd_mesa_debug = 0;
  79 bool fd_binning_enabled = true;
  80 static bool glsl120 = false;
  81
  82 static const char *
  83 fd_screen_get_name(struct pipe_screen *pscreen)
  84 {
  85         static char buffer[128];
  86         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  87                         fd_screen(pscreen)->device_id);
  88         return buffer;
  89 }
  90
  91 static const char *
  92 fd_screen_get_vendor(struct pipe_screen *pscreen)
  93 {
  94         return "freedreno";
  95 }
  96
  97 static const char *
  98 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
  99 {
 100         return "Qualcomm";
 101 }
 102
 103
 104 static uint64_t
 105 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 106 {
 107         int64_t cpu_time = os_time_get() * 1000;
 108         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 109 }
 110
 111 static void
 112 fd_screen_destroy(struct pipe_screen *pscreen)
 113 {
 114         struct fd_screen *screen = fd_screen(pscreen);
 115
 116         if (screen->pipe)
 117                 fd_pipe_del(screen->pipe);
 118
 119         if (screen->dev)
 120                 fd_device_del(screen->dev);
 121
 122         free(screen);
 123 }
 124
 125 /*
 126 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 127 tables for things that differ if the delta is not too much..
 128  */
 129 static int
 130 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 131 {
 132         struct fd_screen *screen = fd_screen(pscreen);
 133
 134         /* this is probably not totally correct.. but it's a start: */
 135         switch (param) {
 136         /* Supported features (boolean caps). */
 137         case PIPE_CAP_NPOT_TEXTURES:
 138         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 139         case PIPE_CAP_TWO_SIDED_STENCIL:
 140         case PIPE_CAP_ANISOTROPIC_FILTER:
 141         case PIPE_CAP_POINT_SPRITE:
 142         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 143         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 144         case PIPE_CAP_TEXTURE_SWIZZLE:
 145         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 146         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 147         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 148         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 149         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 150         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 151         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 152         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 153         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 154         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 155         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156         case PIPE_CAP_VERTEXID_NOBASE:
 157                 return 1;
 158
 159         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 160         case PIPE_CAP_TGSI_TEXCOORD:
 161         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 162         case PIPE_CAP_CONDITIONAL_RENDER:
 163         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 164         case PIPE_CAP_TEXTURE_BARRIER:
 165         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 166         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 167         case PIPE_CAP_START_INSTANCE:
 168         case PIPE_CAP_COMPUTE:
 169                 return 0;
 170
 171         case PIPE_CAP_SM3:
 172         case PIPE_CAP_PRIMITIVE_RESTART:
 173         case PIPE_CAP_TGSI_INSTANCEID:
 174         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 175         case PIPE_CAP_INDEP_BLEND_ENABLE:
 176         case PIPE_CAP_INDEP_BLEND_FUNC:
 177         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 178         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 179                 return is_a3xx(screen) || is_a4xx(screen);
 180
 181         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 182                 /* ignoring first/last_element.. but I guess that should be
 183                  * easy to add..
 184                  */
 185                 return 0;
 186         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 187                 /* I think 32k on a4xx.. and we could possibly emulate more
 188                  * by pretending 2d/rect textures and splitting high bits
 189                  * of index into 2nd dimension..
 190                  */
 191                 return 16383;
 192
 193         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 194         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 195                 return is_a3xx(screen);
 196
 197         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 198         case PIPE_CAP_CUBE_MAP_ARRAY:
 199                 return is_a4xx(screen);
 200
 201         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 202                 return 256;
 203
 204         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 205                 if (glsl120)
 206                         return 120;
 207                 return is_ir3(screen) ? 130 : 120;
 208
 209         /* Unsupported features. */
 210         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 211         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 212         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 213         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 214         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 215         case PIPE_CAP_USER_VERTEX_BUFFERS:
 216         case PIPE_CAP_USER_INDEX_BUFFERS:
 217         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 218         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 219         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 220         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 221         case PIPE_CAP_TEXTURE_GATHER_SM5:
 222         case PIPE_CAP_FAKE_SW_MSAA:
 223         case PIPE_CAP_TEXTURE_QUERY_LOD:
 224         case PIPE_CAP_SAMPLE_SHADING:
 225         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 226         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 227         case PIPE_CAP_DRAW_INDIRECT:
 228         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 229         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 230         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 231         case PIPE_CAP_CLIP_HALFZ:
 232         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 233         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 234         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 235         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 236         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 237         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 238                 return 0;
 239
 240         case PIPE_CAP_MAX_VIEWPORTS:
 241                 return 1;
 242
 243         /* Stream output. */
 244         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 245                 if (is_ir3(screen))
 246                         return PIPE_MAX_SO_BUFFERS;
 247                 return 0;
 248         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 249                 if (is_ir3(screen))
 250                         return 1;
 251                 return 0;
 252         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 253         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 254                 if (is_ir3(screen))
 255                         return 16 * 4;   /* should only be shader out limit? */
 256                 return 0;
 257
 258         /* Geometry shader output, unsupported. */
 259         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 260         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 261         case PIPE_CAP_MAX_VERTEX_STREAMS:
 262                 return 0;
 263
 264         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 265                 return 2048;
 266
 267         /* Texturing. */
 268         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 269         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 270                 return MAX_MIP_LEVELS;
 271         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 272                 return 11;
 273
 274         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 275                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 276
 277         /* Render targets. */
 278         case PIPE_CAP_MAX_RENDER_TARGETS:
 279                 return screen->max_rts;
 280
 281         /* Queries. */
 282         case PIPE_CAP_QUERY_TIME_ELAPSED:
 283         case PIPE_CAP_QUERY_TIMESTAMP:
 284                 return 0;
 285         case PIPE_CAP_OCCLUSION_QUERY:
 286                 return is_a3xx(screen) || is_a4xx(screen);
 287
 288         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 289         case PIPE_CAP_MIN_TEXEL_OFFSET:
 290                 return -8;
 291
 292         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 293         case PIPE_CAP_MAX_TEXEL_OFFSET:
 294                 return 7;
 295
 296         case PIPE_CAP_ENDIANNESS:
 297                 return PIPE_ENDIAN_LITTLE;
 298
 299         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 300                 return 64;
 301
 302         case PIPE_CAP_VENDOR_ID:
 303                 return 0x5143;
 304         case PIPE_CAP_DEVICE_ID:
 305                 return 0xFFFFFFFF;
 306         case PIPE_CAP_ACCELERATED:
 307                 return 1;
 308         case PIPE_CAP_VIDEO_MEMORY:
 309                 DBG("FINISHME: The value returned is incorrect\n");
 310                 return 10;
 311         case PIPE_CAP_UMA:
 312                 return 1;
 313         }
 314         debug_printf("unknown param %d\n", param);
 315         return 0;
 316 }
 317
 318 static float
 319 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 320 {
 321         switch (param) {
 322         case PIPE_CAPF_MAX_LINE_WIDTH:
 323         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 324         case PIPE_CAPF_MAX_POINT_WIDTH:
 325         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 326                 return 4092.0f;
 327         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 328                 return 16.0f;
 329         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 330                 return 15.0f;
 331         case PIPE_CAPF_GUARD_BAND_LEFT:
 332         case PIPE_CAPF_GUARD_BAND_TOP:
 333         case PIPE_CAPF_GUARD_BAND_RIGHT:
 334         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 335                 return 0.0f;
 336         }
 337         debug_printf("unknown paramf %d\n", param);
 338         return 0;
 339 }
 340
 341 static int
 342 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 343                 enum pipe_shader_cap param)
 344 {
 345         struct fd_screen *screen = fd_screen(pscreen);
 346
 347         switch(shader)
 348         {
 349         case PIPE_SHADER_FRAGMENT:
 350         case PIPE_SHADER_VERTEX:
 351                 break;
 352         case PIPE_SHADER_COMPUTE:
 353         case PIPE_SHADER_GEOMETRY:
 354                 /* maye we could emulate.. */
 355                 return 0;
 356         default:
 357                 DBG("unknown shader type %d", shader);
 358                 return 0;
 359         }
 360
 361         /* this is probably not totally correct.. but it's a start: */
 362         switch (param) {
 363         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 364         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 365         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 366         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 367                 return 16384;
 368         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 369                 return 8; /* XXX */
 370         case PIPE_SHADER_CAP_MAX_INPUTS:
 371         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 372                 return 16;
 373         case PIPE_SHADER_CAP_MAX_TEMPS:
 374                 return 64; /* Max native temporaries. */
 375         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 376                 /* NOTE: seems to be limit for a3xx is actually 512 but
 377                  * split between VS and FS.  Use lower limit of 256 to
 378                  * avoid getting into impossible situations:
 379                  */
 380                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 381         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 382                 return is_ir3(screen) ? 16 : 1;
 383         case PIPE_SHADER_CAP_MAX_PREDS:
 384                 return 0; /* nothing uses this */
 385         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 386                 return 1;
 387         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 388         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 389         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 390         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 391                 return 1;
 392         case PIPE_SHADER_CAP_SUBROUTINES:
 393         case PIPE_SHADER_CAP_DOUBLES:
 394         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 395         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 396         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 397         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 398                 return 0;
 399         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 400                 return 1;
 401         case PIPE_SHADER_CAP_INTEGERS:
 402                 if (glsl120)
 403                         return 0;
 404                 return is_ir3(screen) ? 1 : 0;
 405         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 406         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 407                 return 16;
 408         case PIPE_SHADER_CAP_PREFERRED_IR:
 409                 return PIPE_SHADER_IR_TGSI;
 410         }
 411         debug_printf("unknown shader param %d\n", param);
 412         return 0;
 413 }
 414
 415 boolean
 416 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 417                 struct fd_bo *bo,
 418                 unsigned stride,
 419                 struct winsys_handle *whandle)
 420 {
 421         whandle->stride = stride;
 422
 423         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 424                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 425         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 426                 whandle->handle = fd_bo_handle(bo);
 427                 return TRUE;
 428         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 429                 whandle->handle = fd_bo_dmabuf(bo);
 430                 return TRUE;
 431         } else {
 432                 return FALSE;
 433         }
 434 }
 435
 436 struct fd_bo *
 437 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 438                 struct winsys_handle *whandle,
 439                 unsigned *out_stride)
 440 {
 441         struct fd_screen *screen = fd_screen(pscreen);
 442         struct fd_bo *bo;
 443
 444         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 445                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 446         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 447                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 448         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 449                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 450         } else {
 451                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 452                 return NULL;
 453         }
 454
 455         if (!bo) {
 456                 DBG("ref name 0x%08x failed", whandle->handle);
 457                 return NULL;
 458         }
 459
 460         *out_stride = whandle->stride;
 461
 462         return bo;
 463 }
 464
 465 struct pipe_screen *
 466 fd_screen_create(struct fd_device *dev)
 467 {
 468         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 469         struct pipe_screen *pscreen;
 470         uint64_t val;
 471
 472         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 473
 474         if (fd_mesa_debug & FD_DBG_NOBIN)
 475                 fd_binning_enabled = false;
 476
 477         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 478
 479         if (!screen)
 480                 return NULL;
 481
 482         pscreen = &screen->base;
 483
 484         screen->dev = dev;
 485
 486         // maybe this should be in context?
 487         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 488         if (!screen->pipe) {
 489                 DBG("could not create 3d pipe");
 490                 goto fail;
 491         }
 492
 493         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 494                 DBG("could not get GMEM size");
 495                 goto fail;
 496         }
 497         screen->gmemsize_bytes = val;
 498
 499         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 500                 DBG("could not get device-id");
 501                 goto fail;
 502         }
 503         screen->device_id = val;
 504
 505         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 506                 DBG("could not get gpu-id");
 507                 goto fail;
 508         }
 509         screen->gpu_id = val;
 510
 511         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 512                 DBG("could not get chip-id");
 513                 /* older kernels may not have this property: */
 514                 unsigned core  = screen->gpu_id / 100;
 515                 unsigned major = (screen->gpu_id % 100) / 10;
 516                 unsigned minor = screen->gpu_id % 10;
 517                 unsigned patch = 0;  /* assume the worst */
 518                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 519                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 520         }
 521         screen->chip_id = val;
 522
 523         DBG("Pipe Info:");
 524         DBG(" GPU-id:          %d", screen->gpu_id);
 525         DBG(" Chip-id:         0x%08x", screen->chip_id);
 526         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 527
 528         /* explicitly checking for GPU revisions that are known to work.  This
 529          * may be overly conservative for a3xx, where spoofing the gpu_id with
 530          * the blob driver seems to generate identical cmdstream dumps.  But
 531          * on a2xx, there seem to be small differences between the GPU revs
 532          * so it is probably better to actually test first on real hardware
 533          * before enabling:
 534          *
 535          * If you have a different adreno version, feel free to add it to one
 536          * of the cases below and see what happens.  And if it works, please
 537          * send a patch ;-)
 538          */
 539         switch (screen->gpu_id) {
 540         case 220:
 541                 fd2_screen_init(pscreen);
 542                 break;
 543         case 307:
 544         case 320:
 545         case 330:
 546                 fd3_screen_init(pscreen);
 547                 break;
 548         case 420:
 549                 fd4_screen_init(pscreen);
 550                 break;
 551         default:
 552                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 553                 goto fail;
 554         }
 555
 556         pscreen->destroy = fd_screen_destroy;
 557         pscreen->get_param = fd_screen_get_param;
 558         pscreen->get_paramf = fd_screen_get_paramf;
 559         pscreen->get_shader_param = fd_screen_get_shader_param;
 560
 561         fd_resource_screen_init(pscreen);
 562         fd_query_screen_init(pscreen);
 563
 564         pscreen->get_name = fd_screen_get_name;
 565         pscreen->get_vendor = fd_screen_get_vendor;
 566         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 567
 568         pscreen->get_timestamp = fd_screen_get_timestamp;
 569
 570         pscreen->fence_reference = fd_screen_fence_ref;
 571         pscreen->fence_finish = fd_screen_fence_finish;
 572
 573         util_format_s3tc_init();
 574
 575         return pscreen;
 576
 577 fail:
 578         fd_screen_destroy(pscreen);
 579         return NULL;
 580 }