1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
41 #include "os/os_time.h"
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_util.h"
52 #include "fd2_screen.h"
53 #include "fd3_screen.h"
55 /* XXX this should go away */
56 #include "state_tracker/drm_driver.h"
58 static const struct debug_named_value debug_options
[] = {
59 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
60 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
61 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
62 {"dgmem", FD_DBG_DGMEM
, "Mark all state dirty after GMEM tile pass"},
63 {"dscis", FD_DBG_DSCIS
, "Disable scissor optimization"},
67 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
69 int fd_mesa_debug
= 0;
72 fd_screen_get_name(struct pipe_screen
*pscreen
)
74 static char buffer
[128];
75 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
76 fd_screen(pscreen
)->device_id
);
81 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
87 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
89 int64_t cpu_time
= os_time_get() * 1000;
90 return cpu_time
+ fd_screen(pscreen
)->cpu_gpu_time_delta
;
94 fd_screen_fence_ref(struct pipe_screen
*pscreen
,
95 struct pipe_fence_handle
**ptr
,
96 struct pipe_fence_handle
*pfence
)
98 fd_fence_ref(fd_fence(pfence
), (struct fd_fence
**)ptr
);
102 fd_screen_fence_signalled(struct pipe_screen
*screen
,
103 struct pipe_fence_handle
*pfence
)
105 return fd_fence_signalled(fd_fence(pfence
));
109 fd_screen_fence_finish(struct pipe_screen
*screen
,
110 struct pipe_fence_handle
*pfence
,
113 return fd_fence_wait(fd_fence(pfence
));
117 fd_screen_destroy(struct pipe_screen
*pscreen
)
119 struct fd_screen
*screen
= fd_screen(pscreen
);
122 fd_pipe_del(screen
->pipe
);
125 fd_device_del(screen
->dev
);
131 TODO either move caps to a2xx/a3xx specific code, or maybe have some
132 tables for things that differ if the delta is not too much..
135 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
137 /* this is probably not totally correct.. but it's a start: */
139 /* Supported features (boolean caps). */
140 case PIPE_CAP_NPOT_TEXTURES
:
141 case PIPE_CAP_TWO_SIDED_STENCIL
:
142 case PIPE_CAP_ANISOTROPIC_FILTER
:
143 case PIPE_CAP_POINT_SPRITE
:
144 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
145 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
146 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
147 case PIPE_CAP_TEXTURE_SWIZZLE
:
148 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
149 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
150 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
151 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
152 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
154 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
155 case PIPE_CAP_PRIMITIVE_RESTART
:
156 case PIPE_CAP_CONDITIONAL_RENDER
:
157 case PIPE_CAP_TEXTURE_BARRIER
:
158 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
159 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
160 case PIPE_CAP_TGSI_INSTANCEID
:
161 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
162 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
163 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
164 case PIPE_CAP_COMPUTE
:
165 case PIPE_CAP_START_INSTANCE
:
166 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
167 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
171 case PIPE_CAP_TGSI_TEXCOORD
:
172 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
175 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
178 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
181 /* Unsupported features. */
182 case PIPE_CAP_INDEP_BLEND_ENABLE
:
183 case PIPE_CAP_INDEP_BLEND_FUNC
:
184 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
185 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
186 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
187 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
188 case PIPE_CAP_SCALED_RESOLVE
:
189 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
190 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
191 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
192 case PIPE_CAP_USER_VERTEX_BUFFERS
:
193 case PIPE_CAP_USER_INDEX_BUFFERS
:
194 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
195 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
199 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
200 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
201 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
202 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
206 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
207 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
208 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
209 return MAX_MIP_LEVELS
;
210 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
212 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
215 /* Render targets. */
216 case PIPE_CAP_MAX_RENDER_TARGETS
:
220 case PIPE_CAP_QUERY_TIME_ELAPSED
:
221 case PIPE_CAP_OCCLUSION_QUERY
:
222 case PIPE_CAP_QUERY_TIMESTAMP
:
225 case PIPE_CAP_MIN_TEXEL_OFFSET
:
228 case PIPE_CAP_MAX_TEXEL_OFFSET
:
231 case PIPE_CAP_ENDIANNESS
:
232 return PIPE_ENDIAN_LITTLE
;
235 DBG("unknown param %d", param
);
241 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
244 case PIPE_CAPF_MAX_LINE_WIDTH
:
245 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
246 case PIPE_CAPF_MAX_POINT_WIDTH
:
247 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
249 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
251 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
253 case PIPE_CAPF_GUARD_BAND_LEFT
:
254 case PIPE_CAPF_GUARD_BAND_TOP
:
255 case PIPE_CAPF_GUARD_BAND_RIGHT
:
256 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
259 DBG("unknown paramf %d", param
);
265 fd_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
266 enum pipe_shader_cap param
)
270 case PIPE_SHADER_FRAGMENT
:
271 case PIPE_SHADER_VERTEX
:
273 case PIPE_SHADER_COMPUTE
:
274 case PIPE_SHADER_GEOMETRY
:
275 /* maye we could emulate.. */
278 DBG("unknown shader type %d", shader
);
282 /* this is probably not totally correct.. but it's a start: */
284 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
285 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
286 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
287 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
289 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
291 case PIPE_SHADER_CAP_MAX_INPUTS
:
293 case PIPE_SHADER_CAP_MAX_TEMPS
:
294 return 256; /* Max native temporaries. */
295 case PIPE_SHADER_CAP_MAX_ADDRS
:
296 /* XXX Isn't this equal to TEMPS? */
297 return 1; /* Max native address registers */
298 case PIPE_SHADER_CAP_MAX_CONSTS
:
299 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
301 case PIPE_SHADER_CAP_MAX_PREDS
:
302 return 0; /* nothing uses this */
303 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
305 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
306 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
307 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
308 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
310 case PIPE_SHADER_CAP_SUBROUTINES
:
312 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
313 case PIPE_SHADER_CAP_INTEGERS
:
315 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
317 case PIPE_SHADER_CAP_PREFERRED_IR
:
318 return PIPE_SHADER_IR_TGSI
;
320 DBG("unknown shader param %d", param
);
327 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
330 struct winsys_handle
*whandle
)
332 whandle
->stride
= stride
;
334 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
335 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
336 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
337 whandle
->handle
= fd_bo_handle(bo
);
345 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
346 struct winsys_handle
*whandle
,
347 unsigned *out_stride
)
349 struct fd_screen
*screen
= fd_screen(pscreen
);
352 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
354 DBG("ref name 0x%08x failed", whandle
->handle
);
358 *out_stride
= whandle
->stride
;
364 fd_screen_create(struct fd_device
*dev
)
366 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
367 struct pipe_screen
*pscreen
;
370 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
375 pscreen
= &screen
->base
;
379 // maybe this should be in context?
380 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
382 DBG("could not create 3d pipe");
386 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
387 DBG("could not get GMEM size");
390 screen
->gmemsize_bytes
= val
;
392 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
393 DBG("could not get device-id");
396 screen
->device_id
= val
;
398 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
399 DBG("could not get gpu-id");
402 screen
->gpu_id
= val
;
404 /* explicitly checking for GPU revisions that are known to work. This
405 * may be overly conservative for a3xx, where spoofing the gpu_id with
406 * the blob driver seems to generate identical cmdstream dumps. But
407 * on a2xx, there seem to be small differences between the GPU revs
408 * so it is probably better to actually test first on real hardware
411 * If you have a different adreno version, feel free to add it to one
412 * of the two cases below and see what happens. And if it works, please
415 switch (screen
->gpu_id
) {
417 fd2_screen_init(pscreen
);
420 fd3_screen_init(pscreen
);
423 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
427 pscreen
->destroy
= fd_screen_destroy
;
428 pscreen
->get_param
= fd_screen_get_param
;
429 pscreen
->get_paramf
= fd_screen_get_paramf
;
430 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
432 fd_resource_screen_init(pscreen
);
434 pscreen
->get_name
= fd_screen_get_name
;
435 pscreen
->get_vendor
= fd_screen_get_vendor
;
437 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
439 pscreen
->fence_reference
= fd_screen_fence_ref
;
440 pscreen
->fence_signalled
= fd_screen_fence_signalled
;
441 pscreen
->fence_finish
= fd_screen_fence_finish
;
443 util_format_s3tc_init();
448 fd_screen_destroy(pscreen
);