src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 #include "ir3/ir3_nir.h"
  58
  59 /* XXX this should go away */
  60 #include "state_tracker/drm_driver.h"
  61
  62 static const struct debug_named_value debug_options[] = {
  63                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  64                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  65                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  66                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  67                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  68                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  69                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  70                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  71                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  72                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  73                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  74                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  75                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  76                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  77                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  78                 DEBUG_NAMED_VALUE_END
  79 };
  80
  81 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  82
  83 int fd_mesa_debug = 0;
  84 bool fd_binning_enabled = true;
  85 static bool glsl120 = false;
  86
  87 static const char *
  88 fd_screen_get_name(struct pipe_screen *pscreen)
  89 {
  90         static char buffer[128];
  91         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  92                         fd_screen(pscreen)->device_id);
  93         return buffer;
  94 }
  95
  96 static const char *
  97 fd_screen_get_vendor(struct pipe_screen *pscreen)
  98 {
  99         return "freedreno";
 100 }
 101
 102 static const char *
 103 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 104 {
 105         return "Qualcomm";
 106 }
 107
 108
 109 static uint64_t
 110 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 111 {
 112         int64_t cpu_time = os_time_get() * 1000;
 113         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 114 }
 115
 116 static void
 117 fd_screen_destroy(struct pipe_screen *pscreen)
 118 {
 119         struct fd_screen *screen = fd_screen(pscreen);
 120
 121         if (screen->pipe)
 122                 fd_pipe_del(screen->pipe);
 123
 124         if (screen->dev)
 125                 fd_device_del(screen->dev);
 126
 127         free(screen);
 128 }
 129
 130 /*
 131 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 132 tables for things that differ if the delta is not too much..
 133  */
 134 static int
 135 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 136 {
 137         struct fd_screen *screen = fd_screen(pscreen);
 138
 139         /* this is probably not totally correct.. but it's a start: */
 140         switch (param) {
 141         /* Supported features (boolean caps). */
 142         case PIPE_CAP_NPOT_TEXTURES:
 143         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 144         case PIPE_CAP_TWO_SIDED_STENCIL:
 145         case PIPE_CAP_ANISOTROPIC_FILTER:
 146         case PIPE_CAP_POINT_SPRITE:
 147         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 148         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149         case PIPE_CAP_TEXTURE_SWIZZLE:
 150         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 152         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 153         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 154         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 155         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 156         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 157         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 158         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 159         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 160         case PIPE_CAP_VERTEXID_NOBASE:
 161         case PIPE_CAP_STRING_MARKER:
 162                 return 1;
 163
 164         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 165                 return is_ir3(screen) ? 0 : 1;
 166
 167         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 168         case PIPE_CAP_TGSI_TEXCOORD:
 169         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 170         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 171         case PIPE_CAP_TEXTURE_BARRIER:
 172         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 173         case PIPE_CAP_COMPUTE:
 174         case PIPE_CAP_QUERY_MEMORY_INFO:
 175         case PIPE_CAP_PCI_GROUP:
 176         case PIPE_CAP_PCI_BUS:
 177         case PIPE_CAP_PCI_DEVICE:
 178         case PIPE_CAP_PCI_FUNCTION:
 179                 return 0;
 180
 181         case PIPE_CAP_SM3:
 182         case PIPE_CAP_PRIMITIVE_RESTART:
 183         case PIPE_CAP_TGSI_INSTANCEID:
 184         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 185         case PIPE_CAP_INDEP_BLEND_ENABLE:
 186         case PIPE_CAP_INDEP_BLEND_FUNC:
 187         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 188         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189         case PIPE_CAP_CONDITIONAL_RENDER:
 190         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 191         case PIPE_CAP_FAKE_SW_MSAA:
 192         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 193         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 194         case PIPE_CAP_CLIP_HALFZ:
 195                 return is_a3xx(screen) || is_a4xx(screen);
 196
 197         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 198                 return 0;
 199         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 200                 if (is_a3xx(screen)) return 16;
 201                 if (is_a4xx(screen)) return 32;
 202                 return 0;
 203         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 204                 /* We could possibly emulate more by pretending 2d/rect textures and
 205                  * splitting high bits of index into 2nd dimension..
 206                  */
 207                 if (is_a3xx(screen)) return 8192;
 208                 if (is_a4xx(screen)) return 16384;
 209                 return 0;
 210
 211         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 212         case PIPE_CAP_CUBE_MAP_ARRAY:
 213         case PIPE_CAP_START_INSTANCE:
 214         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 215         case PIPE_CAP_TEXTURE_QUERY_LOD:
 216                 return is_a4xx(screen);
 217
 218         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 219                 return 64;
 220
 221         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 222                 if (glsl120)
 223                         return 120;
 224                 return is_ir3(screen) ? 140 : 120;
 225
 226         /* Unsupported features. */
 227         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 228         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 229         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 230         case PIPE_CAP_USER_VERTEX_BUFFERS:
 231         case PIPE_CAP_USER_INDEX_BUFFERS:
 232         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 233         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 234         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 235         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 236         case PIPE_CAP_TEXTURE_GATHER_SM5:
 237         case PIPE_CAP_SAMPLE_SHADING:
 238         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 239         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 240         case PIPE_CAP_DRAW_INDIRECT:
 241         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 242         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 243         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 244         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 245         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 246         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 247         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 248         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 249         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 250         case PIPE_CAP_TGSI_TXQS:
 251         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 252         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 253         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 254         case PIPE_CAP_CLEAR_TEXTURE:
 255         case PIPE_CAP_DRAW_PARAMETERS:
 256         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 257         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 258         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 259         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 260         case PIPE_CAP_INVALIDATE_BUFFER:
 261         case PIPE_CAP_GENERATE_MIPMAP:
 262         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 263         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 264         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 265         case PIPE_CAP_CULL_DISTANCE:
 266         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 267         case PIPE_CAP_TGSI_VOTE:
 268         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 269         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 270                 return 0;
 271
 272         case PIPE_CAP_MAX_VIEWPORTS:
 273                 return 1;
 274
 275         case PIPE_CAP_SHAREABLE_SHADERS:
 276         /* manage the variants for these ourself, to avoid breaking precompile: */
 277         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 278         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 279                 if (is_ir3(screen))
 280                         return 1;
 281                 return 0;
 282
 283         /* Stream output. */
 284         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 285                 if (is_ir3(screen))
 286                         return PIPE_MAX_SO_BUFFERS;
 287                 return 0;
 288         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 289                 if (is_ir3(screen))
 290                         return 1;
 291                 return 0;
 292         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 293         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 294                 if (is_ir3(screen))
 295                         return 16 * 4;   /* should only be shader out limit? */
 296                 return 0;
 297
 298         /* Geometry shader output, unsupported. */
 299         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 300         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 301         case PIPE_CAP_MAX_VERTEX_STREAMS:
 302                 return 0;
 303
 304         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 305                 return 2048;
 306
 307         /* Texturing. */
 308         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 309         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 310                 return MAX_MIP_LEVELS;
 311         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 312                 return 11;
 313
 314         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 315                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 316
 317         /* Render targets. */
 318         case PIPE_CAP_MAX_RENDER_TARGETS:
 319                 return screen->max_rts;
 320         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 321                 return is_a3xx(screen) ? 1 : 0;
 322
 323         /* Queries. */
 324         case PIPE_CAP_QUERY_TIMESTAMP:
 325         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 326                 return 0;
 327         case PIPE_CAP_OCCLUSION_QUERY:
 328                 return is_a3xx(screen) || is_a4xx(screen);
 329         case PIPE_CAP_QUERY_TIME_ELAPSED:
 330                 /* only a4xx, requires new enough kernel so we know max_freq: */
 331                 return (screen->max_freq > 0) && is_a4xx(screen);
 332
 333         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 334         case PIPE_CAP_MIN_TEXEL_OFFSET:
 335                 return -8;
 336
 337         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 338         case PIPE_CAP_MAX_TEXEL_OFFSET:
 339                 return 7;
 340
 341         case PIPE_CAP_ENDIANNESS:
 342                 return PIPE_ENDIAN_LITTLE;
 343
 344         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 345                 return 64;
 346
 347         case PIPE_CAP_VENDOR_ID:
 348                 return 0x5143;
 349         case PIPE_CAP_DEVICE_ID:
 350                 return 0xFFFFFFFF;
 351         case PIPE_CAP_ACCELERATED:
 352                 return 1;
 353         case PIPE_CAP_VIDEO_MEMORY:
 354                 DBG("FINISHME: The value returned is incorrect\n");
 355                 return 10;
 356         case PIPE_CAP_UMA:
 357                 return 1;
 358         }
 359         debug_printf("unknown param %d\n", param);
 360         return 0;
 361 }
 362
 363 static float
 364 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 365 {
 366         switch (param) {
 367         case PIPE_CAPF_MAX_LINE_WIDTH:
 368         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 369                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 370                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 371                  * uses too small of a render target size, and gets confused when
 372                  * the lines start going offscreen.
 373                  *
 374                  * See: https://code.google.com/p/android/issues/detail?id=206513
 375                  */
 376                 if (fd_mesa_debug & FD_DBG_DEQP)
 377                         return 48.0f;
 378                 return 127.0f;
 379         case PIPE_CAPF_MAX_POINT_WIDTH:
 380         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 381                 return 4092.0f;
 382         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 383                 return 16.0f;
 384         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 385                 return 15.0f;
 386         case PIPE_CAPF_GUARD_BAND_LEFT:
 387         case PIPE_CAPF_GUARD_BAND_TOP:
 388         case PIPE_CAPF_GUARD_BAND_RIGHT:
 389         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 390                 return 0.0f;
 391         }
 392         debug_printf("unknown paramf %d\n", param);
 393         return 0;
 394 }
 395
 396 static int
 397 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 398                 enum pipe_shader_cap param)
 399 {
 400         struct fd_screen *screen = fd_screen(pscreen);
 401
 402         switch(shader)
 403         {
 404         case PIPE_SHADER_FRAGMENT:
 405         case PIPE_SHADER_VERTEX:
 406                 break;
 407         case PIPE_SHADER_COMPUTE:
 408         case PIPE_SHADER_GEOMETRY:
 409                 /* maye we could emulate.. */
 410                 return 0;
 411         default:
 412                 DBG("unknown shader type %d", shader);
 413                 return 0;
 414         }
 415
 416         /* this is probably not totally correct.. but it's a start: */
 417         switch (param) {
 418         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 419         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 420         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 421         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 422                 return 16384;
 423         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 424                 return 8; /* XXX */
 425         case PIPE_SHADER_CAP_MAX_INPUTS:
 426         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 427                 return 16;
 428         case PIPE_SHADER_CAP_MAX_TEMPS:
 429                 return 64; /* Max native temporaries. */
 430         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 431                 /* NOTE: seems to be limit for a3xx is actually 512 but
 432                  * split between VS and FS.  Use lower limit of 256 to
 433                  * avoid getting into impossible situations:
 434                  */
 435                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 436         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 437                 return is_ir3(screen) ? 16 : 1;
 438         case PIPE_SHADER_CAP_MAX_PREDS:
 439                 return 0; /* nothing uses this */
 440         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 441                 return 1;
 442         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 443         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 444                 /* Technically this should be the same as for TEMP/CONST, since
 445                  * everything is just normal registers.  This is just temporary
 446                  * hack until load_input/store_output handle arrays in a similar
 447                  * way as load_var/store_var..
 448                  */
 449                 return 0;
 450         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 451         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 452                 /* a2xx compiler doesn't handle indirect: */
 453                 return is_ir3(screen) ? 1 : 0;
 454         case PIPE_SHADER_CAP_SUBROUTINES:
 455         case PIPE_SHADER_CAP_DOUBLES:
 456         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 457         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 458         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 459         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 460                 return 0;
 461         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 462                 return 1;
 463         case PIPE_SHADER_CAP_INTEGERS:
 464                 if (glsl120)
 465                         return 0;
 466                 return is_ir3(screen) ? 1 : 0;
 467         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 468         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 469                 return 16;
 470         case PIPE_SHADER_CAP_PREFERRED_IR:
 471                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 472                         return PIPE_SHADER_IR_NIR;
 473                 return PIPE_SHADER_IR_TGSI;
 474         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 475                 return 0;
 476         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 477                 return 32;
 478         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 479         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 480                 return 0;
 481         }
 482         debug_printf("unknown shader param %d\n", param);
 483         return 0;
 484 }
 485
 486 static const void *
 487 fd_get_compiler_options(struct pipe_screen *pscreen,
 488                 enum pipe_shader_ir ir, unsigned shader)
 489 {
 490         struct fd_screen *screen = fd_screen(pscreen);
 491
 492         if (is_ir3(screen))
 493                 return ir3_get_compiler_options();
 494
 495         return NULL;
 496 }
 497
 498 boolean
 499 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 500                 struct fd_bo *bo,
 501                 unsigned stride,
 502                 struct winsys_handle *whandle)
 503 {
 504         whandle->stride = stride;
 505
 506         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 507                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 508         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 509                 whandle->handle = fd_bo_handle(bo);
 510                 return TRUE;
 511         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 512                 whandle->handle = fd_bo_dmabuf(bo);
 513                 return TRUE;
 514         } else {
 515                 return FALSE;
 516         }
 517 }
 518
 519 struct fd_bo *
 520 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 521                 struct winsys_handle *whandle,
 522                 unsigned *out_stride)
 523 {
 524         struct fd_screen *screen = fd_screen(pscreen);
 525         struct fd_bo *bo;
 526
 527         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 528                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 529         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 530                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 531         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 532                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 533         } else {
 534                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 535                 return NULL;
 536         }
 537
 538         if (!bo) {
 539                 DBG("ref name 0x%08x failed", whandle->handle);
 540                 return NULL;
 541         }
 542
 543         *out_stride = whandle->stride;
 544
 545         return bo;
 546 }
 547
 548 struct pipe_screen *
 549 fd_screen_create(struct fd_device *dev)
 550 {
 551         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 552         struct pipe_screen *pscreen;
 553         uint64_t val;
 554
 555         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 556
 557         if (fd_mesa_debug & FD_DBG_NOBIN)
 558                 fd_binning_enabled = false;
 559
 560         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 561
 562         if (!screen)
 563                 return NULL;
 564
 565         pscreen = &screen->base;
 566
 567         screen->dev = dev;
 568         screen->refcnt = 1;
 569
 570         // maybe this should be in context?
 571         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 572         if (!screen->pipe) {
 573                 DBG("could not create 3d pipe");
 574                 goto fail;
 575         }
 576
 577         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 578                 DBG("could not get GMEM size");
 579                 goto fail;
 580         }
 581         screen->gmemsize_bytes = val;
 582
 583         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 584                 DBG("could not get device-id");
 585                 goto fail;
 586         }
 587         screen->device_id = val;
 588
 589         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 590                 DBG("could not get gpu freq");
 591                 /* this limits what performance related queries are
 592                  * supported but is not fatal
 593                  */
 594                 screen->max_freq = 0;
 595         } else {
 596                 screen->max_freq = val;
 597         }
 598
 599         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 600                 DBG("could not get gpu-id");
 601                 goto fail;
 602         }
 603         screen->gpu_id = val;
 604
 605         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 606                 DBG("could not get chip-id");
 607                 /* older kernels may not have this property: */
 608                 unsigned core  = screen->gpu_id / 100;
 609                 unsigned major = (screen->gpu_id % 100) / 10;
 610                 unsigned minor = screen->gpu_id % 10;
 611                 unsigned patch = 0;  /* assume the worst */
 612                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 613                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 614         }
 615         screen->chip_id = val;
 616
 617         DBG("Pipe Info:");
 618         DBG(" GPU-id:          %d", screen->gpu_id);
 619         DBG(" Chip-id:         0x%08x", screen->chip_id);
 620         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 621
 622         /* explicitly checking for GPU revisions that are known to work.  This
 623          * may be overly conservative for a3xx, where spoofing the gpu_id with
 624          * the blob driver seems to generate identical cmdstream dumps.  But
 625          * on a2xx, there seem to be small differences between the GPU revs
 626          * so it is probably better to actually test first on real hardware
 627          * before enabling:
 628          *
 629          * If you have a different adreno version, feel free to add it to one
 630          * of the cases below and see what happens.  And if it works, please
 631          * send a patch ;-)
 632          */
 633         switch (screen->gpu_id) {
 634         case 220:
 635                 fd2_screen_init(pscreen);
 636                 break;
 637         case 305:
 638         case 307:
 639         case 320:
 640         case 330:
 641                 fd3_screen_init(pscreen);
 642                 break;
 643         case 420:
 644         case 430:
 645                 fd4_screen_init(pscreen);
 646                 break;
 647         default:
 648                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 649                 goto fail;
 650         }
 651
 652         pscreen->destroy = fd_screen_destroy;
 653         pscreen->get_param = fd_screen_get_param;
 654         pscreen->get_paramf = fd_screen_get_paramf;
 655         pscreen->get_shader_param = fd_screen_get_shader_param;
 656         pscreen->get_compiler_options = fd_get_compiler_options;
 657
 658         fd_resource_screen_init(pscreen);
 659         fd_query_screen_init(pscreen);
 660
 661         pscreen->get_name = fd_screen_get_name;
 662         pscreen->get_vendor = fd_screen_get_vendor;
 663         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 664
 665         pscreen->get_timestamp = fd_screen_get_timestamp;
 666
 667         pscreen->fence_reference = fd_screen_fence_ref;
 668         pscreen->fence_finish = fd_screen_fence_finish;
 669
 670         util_format_s3tc_init();
 671
 672         return pscreen;
 673
 674 fail:
 675         fd_screen_destroy(pscreen);
 676         return NULL;
 677 }