1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_state.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_debug.h"
41 #include "os/os_time.h"
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
58 #include "ir3/ir3_nir.h"
60 /* XXX this should go away */
61 #include "state_tracker/drm_driver.h"
63 static const struct debug_named_value debug_options
[] = {
64 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
65 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly"},
66 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
67 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
68 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
69 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
70 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
71 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
72 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
73 {"optmsgs", FD_DBG_OPTMSGS
,"Enable optimizer debug messages"},
74 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
75 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
76 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
77 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
78 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
79 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
80 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
81 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
87 int fd_mesa_debug
= 0;
88 bool fd_binning_enabled
= true;
89 static bool glsl120
= false;
92 fd_screen_get_name(struct pipe_screen
*pscreen
)
94 static char buffer
[128];
95 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
96 fd_screen(pscreen
)->device_id
);
101 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
107 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
114 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
116 struct fd_screen
*screen
= fd_screen(pscreen
);
118 if (screen
->has_timestamp
) {
120 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
121 debug_assert(screen
->max_freq
> 0);
122 return n
* 1000000000 / screen
->max_freq
;
124 int64_t cpu_time
= os_time_get() * 1000;
125 return cpu_time
+ screen
->cpu_gpu_time_delta
;
131 fd_screen_destroy(struct pipe_screen
*pscreen
)
133 struct fd_screen
*screen
= fd_screen(pscreen
);
136 fd_pipe_del(screen
->pipe
);
139 fd_device_del(screen
->dev
);
141 fd_bc_fini(&screen
->batch_cache
);
143 slab_destroy_parent(&screen
->transfer_pool
);
145 mtx_destroy(&screen
->lock
);
147 ralloc_free(screen
->compiler
);
153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
154 tables for things that differ if the delta is not too much..
157 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
159 struct fd_screen
*screen
= fd_screen(pscreen
);
161 /* this is probably not totally correct.. but it's a start: */
163 /* Supported features (boolean caps). */
164 case PIPE_CAP_NPOT_TEXTURES
:
165 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
166 case PIPE_CAP_TWO_SIDED_STENCIL
:
167 case PIPE_CAP_ANISOTROPIC_FILTER
:
168 case PIPE_CAP_POINT_SPRITE
:
169 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
170 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
171 case PIPE_CAP_TEXTURE_SWIZZLE
:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
173 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
176 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
177 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
178 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
179 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
180 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
181 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
182 case PIPE_CAP_STRING_MARKER
:
183 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
186 case PIPE_CAP_VERTEXID_NOBASE
:
187 return is_a3xx(screen
) || is_a4xx(screen
);
189 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
190 return is_a4xx(screen
) ? 0 : 1;
192 case PIPE_CAP_COMPUTE
:
193 return has_compute(screen
);
195 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
196 case PIPE_CAP_TGSI_TEXCOORD
:
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
198 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
199 case PIPE_CAP_TEXTURE_BARRIER
:
200 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
201 case PIPE_CAP_QUERY_MEMORY_INFO
:
202 case PIPE_CAP_PCI_GROUP
:
203 case PIPE_CAP_PCI_BUS
:
204 case PIPE_CAP_PCI_DEVICE
:
205 case PIPE_CAP_PCI_FUNCTION
:
209 case PIPE_CAP_PRIMITIVE_RESTART
:
210 case PIPE_CAP_TGSI_INSTANCEID
:
211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
212 case PIPE_CAP_INDEP_BLEND_ENABLE
:
213 case PIPE_CAP_INDEP_BLEND_FUNC
:
214 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
215 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
216 case PIPE_CAP_CONDITIONAL_RENDER
:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
218 case PIPE_CAP_FAKE_SW_MSAA
:
219 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
220 case PIPE_CAP_CLIP_HALFZ
:
221 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
);
223 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
224 return is_a3xx(screen
) || is_a4xx(screen
);
226 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
227 return is_a5xx(screen
);
229 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
231 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
232 if (is_a3xx(screen
)) return 16;
233 if (is_a4xx(screen
)) return 32;
234 if (is_a5xx(screen
)) return 32;
236 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
237 /* We could possibly emulate more by pretending 2d/rect textures and
238 * splitting high bits of index into 2nd dimension..
240 if (is_a3xx(screen
)) return 8192;
241 if (is_a4xx(screen
)) return 16384;
242 if (is_a5xx(screen
)) return 16384;
245 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
246 case PIPE_CAP_CUBE_MAP_ARRAY
:
247 case PIPE_CAP_START_INSTANCE
:
248 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
249 case PIPE_CAP_TEXTURE_QUERY_LOD
:
250 return is_a4xx(screen
) || is_a5xx(screen
);
252 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
255 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
258 return is_ir3(screen
) ? 140 : 120;
260 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
265 /* Unsupported features. */
266 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
267 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
268 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
269 case PIPE_CAP_USER_VERTEX_BUFFERS
:
270 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
271 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
272 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
273 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
274 case PIPE_CAP_TEXTURE_GATHER_SM5
:
275 case PIPE_CAP_SAMPLE_SHADING
:
276 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
277 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
278 case PIPE_CAP_DRAW_INDIRECT
:
279 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
280 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
281 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
282 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
283 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
284 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
285 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
286 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
287 case PIPE_CAP_TGSI_TXQS
:
288 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
289 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
290 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
291 case PIPE_CAP_CLEAR_TEXTURE
:
292 case PIPE_CAP_DRAW_PARAMETERS
:
293 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
294 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
295 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
296 case PIPE_CAP_INVALIDATE_BUFFER
:
297 case PIPE_CAP_GENERATE_MIPMAP
:
298 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
299 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
300 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
301 case PIPE_CAP_CULL_DISTANCE
:
302 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
303 case PIPE_CAP_TGSI_VOTE
:
304 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
305 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
306 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
307 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
308 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
309 case PIPE_CAP_TGSI_FS_FBFETCH
:
310 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
311 case PIPE_CAP_DOUBLES
:
313 case PIPE_CAP_INT64_DIVMOD
:
314 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
315 case PIPE_CAP_TGSI_CLOCK
:
316 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
317 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
318 case PIPE_CAP_TGSI_BALLOT
:
319 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
320 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
321 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
322 case PIPE_CAP_POST_DEPTH_COVERAGE
:
323 case PIPE_CAP_BINDLESS_TEXTURE
:
324 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
325 case PIPE_CAP_QUERY_SO_OVERFLOW
:
326 case PIPE_CAP_MEMOBJ
:
327 case PIPE_CAP_LOAD_CONSTBUF
:
330 case PIPE_CAP_MAX_VIEWPORTS
:
333 case PIPE_CAP_SHAREABLE_SHADERS
:
334 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
335 /* manage the variants for these ourself, to avoid breaking precompile: */
336 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
337 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
343 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
345 return PIPE_MAX_SO_BUFFERS
;
347 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
348 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
352 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
353 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
355 return 16 * 4; /* should only be shader out limit? */
358 /* Geometry shader output, unsupported. */
359 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
360 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
361 case PIPE_CAP_MAX_VERTEX_STREAMS
:
364 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
368 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
369 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
370 return MAX_MIP_LEVELS
;
371 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
374 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
375 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
)) ? 256 : 0;
377 /* Render targets. */
378 case PIPE_CAP_MAX_RENDER_TARGETS
:
379 return screen
->max_rts
;
380 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
381 return is_a3xx(screen
) ? 1 : 0;
384 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
386 case PIPE_CAP_OCCLUSION_QUERY
:
387 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
);
388 case PIPE_CAP_QUERY_TIMESTAMP
:
389 case PIPE_CAP_QUERY_TIME_ELAPSED
:
390 /* only a4xx, requires new enough kernel so we know max_freq: */
391 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
));
393 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
394 case PIPE_CAP_MIN_TEXEL_OFFSET
:
397 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
398 case PIPE_CAP_MAX_TEXEL_OFFSET
:
401 case PIPE_CAP_ENDIANNESS
:
402 return PIPE_ENDIAN_LITTLE
;
404 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
407 case PIPE_CAP_VENDOR_ID
:
409 case PIPE_CAP_DEVICE_ID
:
411 case PIPE_CAP_ACCELERATED
:
413 case PIPE_CAP_VIDEO_MEMORY
:
414 DBG("FINISHME: The value returned is incorrect\n");
418 case PIPE_CAP_NATIVE_FENCE_FD
:
419 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
421 debug_printf("unknown param %d\n", param
);
426 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
429 case PIPE_CAPF_MAX_LINE_WIDTH
:
430 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
431 /* NOTE: actual value is 127.0f, but this is working around a deqp
432 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
433 * uses too small of a render target size, and gets confused when
434 * the lines start going offscreen.
436 * See: https://code.google.com/p/android/issues/detail?id=206513
438 if (fd_mesa_debug
& FD_DBG_DEQP
)
441 case PIPE_CAPF_MAX_POINT_WIDTH
:
442 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
444 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
446 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
448 case PIPE_CAPF_GUARD_BAND_LEFT
:
449 case PIPE_CAPF_GUARD_BAND_TOP
:
450 case PIPE_CAPF_GUARD_BAND_RIGHT
:
451 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
454 debug_printf("unknown paramf %d\n", param
);
459 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
460 enum pipe_shader_type shader
,
461 enum pipe_shader_cap param
)
463 struct fd_screen
*screen
= fd_screen(pscreen
);
467 case PIPE_SHADER_FRAGMENT
:
468 case PIPE_SHADER_VERTEX
:
470 case PIPE_SHADER_COMPUTE
:
471 if (has_compute(screen
))
474 case PIPE_SHADER_GEOMETRY
:
475 /* maye we could emulate.. */
478 DBG("unknown shader type %d", shader
);
482 /* this is probably not totally correct.. but it's a start: */
484 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
485 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
486 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
487 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
489 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
491 case PIPE_SHADER_CAP_MAX_INPUTS
:
492 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
494 case PIPE_SHADER_CAP_MAX_TEMPS
:
495 return 64; /* Max native temporaries. */
496 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
497 /* NOTE: seems to be limit for a3xx is actually 512 but
498 * split between VS and FS. Use lower limit of 256 to
499 * avoid getting into impossible situations:
501 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
502 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
503 return is_ir3(screen
) ? 16 : 1;
504 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
506 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
507 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
508 /* Technically this should be the same as for TEMP/CONST, since
509 * everything is just normal registers. This is just temporary
510 * hack until load_input/store_output handle arrays in a similar
511 * way as load_var/store_var..
514 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
515 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
516 /* a2xx compiler doesn't handle indirect: */
517 return is_ir3(screen
) ? 1 : 0;
518 case PIPE_SHADER_CAP_SUBROUTINES
:
519 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
520 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
521 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
522 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
523 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
525 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
527 case PIPE_SHADER_CAP_INTEGERS
:
530 return is_ir3(screen
) ? 1 : 0;
531 case PIPE_SHADER_CAP_INT64_ATOMICS
:
533 case PIPE_SHADER_CAP_FP16
:
535 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
536 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
538 case PIPE_SHADER_CAP_PREFERRED_IR
:
540 return PIPE_SHADER_IR_NIR
;
541 return PIPE_SHADER_IR_TGSI
;
542 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
543 if (is_ir3(screen
)) {
544 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
546 return (1 << PIPE_SHADER_IR_TGSI
);
549 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
551 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
552 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
554 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
555 if (is_a5xx(screen
)) {
556 /* a5xx (and a4xx for that matter) has one state-block
557 * for compute-shader SSBO's and another that is shared
558 * by VS/HS/DS/GS/FS.. so to simplify things for now
559 * just advertise SSBOs for FS and CS. We could possibly
560 * do what blob does, and partition the space for
561 * VS/HS/DS/GS/FS. The blob advertises:
563 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
564 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
565 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
566 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
567 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
568 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
569 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
571 * I think that way we could avoid having to patch shaders
572 * for actual SSBO indexes by using a static partitioning.
576 case PIPE_SHADER_FRAGMENT
:
577 case PIPE_SHADER_COMPUTE
:
584 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
585 /* probably should be same as MAX_SHADRER_BUFFERS but not implemented yet */
588 debug_printf("unknown shader param %d\n", param
);
592 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
593 * into per-generation backend?
596 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
597 enum pipe_compute_cap param
, void *ret
)
599 struct fd_screen
*screen
= fd_screen(pscreen
);
600 const char * const ir
= "ir3";
602 if (!has_compute(screen
))
606 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
608 uint32_t *address_bits
= ret
;
609 address_bits
[0] = 32;
612 address_bits
[0] = 64;
614 return 1 * sizeof(uint32_t);
616 case PIPE_COMPUTE_CAP_IR_TARGET
:
619 return strlen(ir
) * sizeof(char);
621 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
623 uint64_t *grid_dimension
= ret
;
624 grid_dimension
[0] = 3;
626 return 1 * sizeof(uint64_t);
628 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
630 uint64_t *grid_size
= ret
;
631 grid_size
[0] = 65535;
632 grid_size
[1] = 65535;
633 grid_size
[2] = 65535;
635 return 3 * sizeof(uint64_t) ;
637 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
639 uint64_t *grid_size
= ret
;
644 return 3 * sizeof(uint64_t) ;
646 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
648 uint64_t *max_threads_per_block
= ret
;
649 *max_threads_per_block
= 1024;
651 return sizeof(uint64_t);
653 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
654 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
655 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
656 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
658 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
663 return sizeof(uint64_t);
664 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
665 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
666 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
667 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
668 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
676 fd_get_compiler_options(struct pipe_screen
*pscreen
,
677 enum pipe_shader_ir ir
, unsigned shader
)
679 struct fd_screen
*screen
= fd_screen(pscreen
);
682 return ir3_get_compiler_options(screen
->compiler
);
688 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
691 struct winsys_handle
*whandle
)
693 whandle
->stride
= stride
;
695 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
696 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
697 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
698 whandle
->handle
= fd_bo_handle(bo
);
700 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
701 whandle
->handle
= fd_bo_dmabuf(bo
);
709 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
710 struct winsys_handle
*whandle
)
712 struct fd_screen
*screen
= fd_screen(pscreen
);
715 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
716 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
717 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
718 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
719 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
720 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
722 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
727 DBG("ref name 0x%08x failed", whandle
->handle
);
735 fd_screen_create(struct fd_device
*dev
)
737 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
738 struct pipe_screen
*pscreen
;
741 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
743 if (fd_mesa_debug
& FD_DBG_NOBIN
)
744 fd_binning_enabled
= false;
746 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
751 pscreen
= &screen
->base
;
756 // maybe this should be in context?
757 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
759 DBG("could not create 3d pipe");
763 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
764 DBG("could not get GMEM size");
767 screen
->gmemsize_bytes
= val
;
769 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
770 DBG("could not get device-id");
773 screen
->device_id
= val
;
775 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
776 DBG("could not get gpu freq");
777 /* this limits what performance related queries are
778 * supported but is not fatal
780 screen
->max_freq
= 0;
782 screen
->max_freq
= val
;
783 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
784 screen
->has_timestamp
= true;
787 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
788 DBG("could not get gpu-id");
791 screen
->gpu_id
= val
;
793 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
794 DBG("could not get chip-id");
795 /* older kernels may not have this property: */
796 unsigned core
= screen
->gpu_id
/ 100;
797 unsigned major
= (screen
->gpu_id
% 100) / 10;
798 unsigned minor
= screen
->gpu_id
% 10;
799 unsigned patch
= 0; /* assume the worst */
800 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
801 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
803 screen
->chip_id
= val
;
806 DBG(" GPU-id: %d", screen
->gpu_id
);
807 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
808 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
810 /* explicitly checking for GPU revisions that are known to work. This
811 * may be overly conservative for a3xx, where spoofing the gpu_id with
812 * the blob driver seems to generate identical cmdstream dumps. But
813 * on a2xx, there seem to be small differences between the GPU revs
814 * so it is probably better to actually test first on real hardware
817 * If you have a different adreno version, feel free to add it to one
818 * of the cases below and see what happens. And if it works, please
821 switch (screen
->gpu_id
) {
823 fd2_screen_init(pscreen
);
829 fd3_screen_init(pscreen
);
833 fd4_screen_init(pscreen
);
836 fd5_screen_init(pscreen
);
839 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
843 if (screen
->gpu_id
>= 500) {
844 screen
->gmem_alignw
= 64;
845 screen
->gmem_alignh
= 32;
846 screen
->num_vsc_pipes
= 16;
848 screen
->gmem_alignw
= 32;
849 screen
->gmem_alignh
= 32;
850 screen
->num_vsc_pipes
= 8;
853 /* NOTE: don't enable reordering on a2xx, since completely untested.
854 * Also, don't enable if we have too old of a kernel to support
855 * growable cmdstream buffers, since memory requirement for cmdstream
856 * buffers would be too much otherwise.
858 if ((screen
->gpu_id
>= 300) && (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
))
859 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
861 fd_bc_init(&screen
->batch_cache
);
863 (void) mtx_init(&screen
->lock
, mtx_plain
);
865 pscreen
->destroy
= fd_screen_destroy
;
866 pscreen
->get_param
= fd_screen_get_param
;
867 pscreen
->get_paramf
= fd_screen_get_paramf
;
868 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
869 pscreen
->get_compute_param
= fd_get_compute_param
;
870 pscreen
->get_compiler_options
= fd_get_compiler_options
;
872 fd_resource_screen_init(pscreen
);
873 fd_query_screen_init(pscreen
);
875 pscreen
->get_name
= fd_screen_get_name
;
876 pscreen
->get_vendor
= fd_screen_get_vendor
;
877 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
879 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
881 pscreen
->fence_reference
= fd_fence_ref
;
882 pscreen
->fence_finish
= fd_fence_finish
;
883 pscreen
->fence_get_fd
= fd_fence_get_fd
;
885 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
890 fd_screen_destroy(pscreen
);