src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  81                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  82                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  83                 DEBUG_NAMED_VALUE_END
  84 };
  85
  86 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  87
  88 int fd_mesa_debug = 0;
  89 bool fd_binning_enabled = true;
  90 static bool glsl120 = false;
  91
  92 static const char *
  93 fd_screen_get_name(struct pipe_screen *pscreen)
  94 {
  95         static char buffer[128];
  96         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  97                         fd_screen(pscreen)->device_id);
  98         return buffer;
  99 }
 100
 101 static const char *
 102 fd_screen_get_vendor(struct pipe_screen *pscreen)
 103 {
 104         return "freedreno";
 105 }
 106
 107 static const char *
 108 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 109 {
 110         return "Qualcomm";
 111 }
 112
 113
 114 static uint64_t
 115 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 116 {
 117         struct fd_screen *screen = fd_screen(pscreen);
 118
 119         if (screen->has_timestamp) {
 120                 uint64_t n;
 121                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 122                 debug_assert(screen->max_freq > 0);
 123                 return n * 1000000000 / screen->max_freq;
 124         } else {
 125                 int64_t cpu_time = os_time_get() * 1000;
 126                 return cpu_time + screen->cpu_gpu_time_delta;
 127         }
 128
 129 }
 130
 131 static void
 132 fd_screen_destroy(struct pipe_screen *pscreen)
 133 {
 134         struct fd_screen *screen = fd_screen(pscreen);
 135
 136         if (screen->pipe)
 137                 fd_pipe_del(screen->pipe);
 138
 139         if (screen->dev)
 140                 fd_device_del(screen->dev);
 141
 142         fd_bc_fini(&screen->batch_cache);
 143
 144         slab_destroy_parent(&screen->transfer_pool);
 145
 146         mtx_destroy(&screen->lock);
 147
 148         ralloc_free(screen->compiler);
 149
 150         free(screen);
 151 }
 152
 153 /*
 154 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 155 tables for things that differ if the delta is not too much..
 156  */
 157 static int
 158 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 159 {
 160         struct fd_screen *screen = fd_screen(pscreen);
 161
 162         /* this is probably not totally correct.. but it's a start: */
 163         switch (param) {
 164         /* Supported features (boolean caps). */
 165         case PIPE_CAP_NPOT_TEXTURES:
 166         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 167         case PIPE_CAP_TWO_SIDED_STENCIL:
 168         case PIPE_CAP_ANISOTROPIC_FILTER:
 169         case PIPE_CAP_POINT_SPRITE:
 170         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 171         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 172         case PIPE_CAP_TEXTURE_SWIZZLE:
 173         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 174         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 175         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 176         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 177         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 178         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 179         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 180         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 182         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 183         case PIPE_CAP_STRING_MARKER:
 184         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 185         case PIPE_CAP_TEXTURE_BARRIER:
 186         case PIPE_CAP_INVALIDATE_BUFFER:
 187                 return 1;
 188
 189         case PIPE_CAP_VERTEXID_NOBASE:
 190                 return is_a3xx(screen) || is_a4xx(screen);
 191
 192         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 193                 return is_a4xx(screen) ? 0 : 1;
 194
 195         case PIPE_CAP_COMPUTE:
 196                 return has_compute(screen);
 197
 198         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 199         case PIPE_CAP_TGSI_TEXCOORD:
 200         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 201         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 202         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 203         case PIPE_CAP_QUERY_MEMORY_INFO:
 204         case PIPE_CAP_PCI_GROUP:
 205         case PIPE_CAP_PCI_BUS:
 206         case PIPE_CAP_PCI_DEVICE:
 207         case PIPE_CAP_PCI_FUNCTION:
 208                 return 0;
 209
 210         case PIPE_CAP_SM3:
 211         case PIPE_CAP_PRIMITIVE_RESTART:
 212         case PIPE_CAP_TGSI_INSTANCEID:
 213         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 214         case PIPE_CAP_INDEP_BLEND_ENABLE:
 215         case PIPE_CAP_INDEP_BLEND_FUNC:
 216         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 217         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 218         case PIPE_CAP_CONDITIONAL_RENDER:
 219         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 220         case PIPE_CAP_FAKE_SW_MSAA:
 221         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 222         case PIPE_CAP_CLIP_HALFZ:
 223                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 224
 225         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 226                 return is_a3xx(screen) || is_a4xx(screen);
 227
 228         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 229                 return is_a5xx(screen);
 230
 231         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 232                 return 0;
 233         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 234                 if (is_a3xx(screen)) return 16;
 235                 if (is_a4xx(screen)) return 32;
 236                 if (is_a5xx(screen)) return 32;
 237                 return 0;
 238         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 239                 /* We could possibly emulate more by pretending 2d/rect textures and
 240                  * splitting high bits of index into 2nd dimension..
 241                  */
 242                 if (is_a3xx(screen)) return 8192;
 243                 if (is_a4xx(screen)) return 16384;
 244                 if (is_a5xx(screen)) return 16384;
 245                 return 0;
 246
 247         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 248         case PIPE_CAP_CUBE_MAP_ARRAY:
 249         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 250         case PIPE_CAP_TEXTURE_QUERY_LOD:
 251                 return is_a4xx(screen) || is_a5xx(screen);
 252
 253         case PIPE_CAP_START_INSTANCE:
 254                 /* Note that a5xx can do this, it just can't (at least with
 255                  * current firmware) do draw_indirect with base_instance.
 256                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 257                  * gl42), hide base_instance on a5xx.  :-/
 258                  */
 259                 return is_a4xx(screen);
 260
 261         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 262                 return 64;
 263
 264         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 265                 if (glsl120)
 266                         return 120;
 267                 return is_ir3(screen) ? 140 : 120;
 268
 269         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 270                 if (is_a5xx(screen))
 271                         return 4;
 272                 return 0;
 273
 274         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 275                 if (is_a4xx(screen) || is_a5xx(screen))
 276                         return 4;
 277                 return 0;
 278
 279         /* Unsupported features. */
 280         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 281         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 282         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 283         case PIPE_CAP_USER_VERTEX_BUFFERS:
 284         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 285         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 286         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 287         case PIPE_CAP_TEXTURE_GATHER_SM5:
 288         case PIPE_CAP_SAMPLE_SHADING:
 289         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 290         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 291         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 292         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 293         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 294         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 295         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 296         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 297         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 298         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 299         case PIPE_CAP_TGSI_TXQS:
 300         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 301         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 302         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 303         case PIPE_CAP_CLEAR_TEXTURE:
 304         case PIPE_CAP_DRAW_PARAMETERS:
 305         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 306         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 307         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 308         case PIPE_CAP_GENERATE_MIPMAP:
 309         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 310         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 311         case PIPE_CAP_CULL_DISTANCE:
 312         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 313         case PIPE_CAP_TGSI_VOTE:
 314         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 315         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 316         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 317         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 318         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 319         case PIPE_CAP_TGSI_FS_FBFETCH:
 320         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 321         case PIPE_CAP_DOUBLES:
 322         case PIPE_CAP_INT64:
 323         case PIPE_CAP_INT64_DIVMOD:
 324         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 325         case PIPE_CAP_TGSI_CLOCK:
 326         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 327         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 328         case PIPE_CAP_TGSI_BALLOT:
 329         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 330         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 331         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 332         case PIPE_CAP_POST_DEPTH_COVERAGE:
 333         case PIPE_CAP_BINDLESS_TEXTURE:
 334         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 335         case PIPE_CAP_QUERY_SO_OVERFLOW:
 336         case PIPE_CAP_MEMOBJ:
 337         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 338         case PIPE_CAP_TILE_RASTER_ORDER:
 339         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 340         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 341                 return 0;
 342
 343         case PIPE_CAP_DRAW_INDIRECT:
 344                 if (is_a4xx(screen) || is_a5xx(screen))
 345                         return 1;
 346                 return 0;
 347
 348         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 349                 if (is_a4xx(screen) || is_a5xx(screen))
 350                         return 1;
 351                 return 0;
 352
 353         case PIPE_CAP_LOAD_CONSTBUF:
 354                 /* name is confusing, but this turns on std430 packing */
 355                 if (is_ir3(screen))
 356                         return 1;
 357                 return 0;
 358
 359         case PIPE_CAP_MAX_VIEWPORTS:
 360                 return 1;
 361
 362         case PIPE_CAP_SHAREABLE_SHADERS:
 363         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 364         /* manage the variants for these ourself, to avoid breaking precompile: */
 365         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 366         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 367                 if (is_ir3(screen))
 368                         return 1;
 369                 return 0;
 370
 371         /* Stream output. */
 372         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 373                 if (is_ir3(screen))
 374                         return PIPE_MAX_SO_BUFFERS;
 375                 return 0;
 376         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 377         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 378                 if (is_ir3(screen))
 379                         return 1;
 380                 return 0;
 381         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 382         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 383                 if (is_ir3(screen))
 384                         return 16 * 4;   /* should only be shader out limit? */
 385                 return 0;
 386
 387         /* Geometry shader output, unsupported. */
 388         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 389         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 390         case PIPE_CAP_MAX_VERTEX_STREAMS:
 391                 return 0;
 392
 393         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 394                 return 2048;
 395
 396         /* Texturing. */
 397         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 398         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 399                 return MAX_MIP_LEVELS;
 400         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 401                 return 11;
 402
 403         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 404                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 405
 406         /* Render targets. */
 407         case PIPE_CAP_MAX_RENDER_TARGETS:
 408                 return screen->max_rts;
 409         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 410                 return is_a3xx(screen) ? 1 : 0;
 411
 412         /* Queries. */
 413         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 414                 return 0;
 415         case PIPE_CAP_OCCLUSION_QUERY:
 416                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 417         case PIPE_CAP_QUERY_TIMESTAMP:
 418         case PIPE_CAP_QUERY_TIME_ELAPSED:
 419                 /* only a4xx, requires new enough kernel so we know max_freq: */
 420                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 421
 422         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 423         case PIPE_CAP_MIN_TEXEL_OFFSET:
 424                 return -8;
 425
 426         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 427         case PIPE_CAP_MAX_TEXEL_OFFSET:
 428                 return 7;
 429
 430         case PIPE_CAP_ENDIANNESS:
 431                 return PIPE_ENDIAN_LITTLE;
 432
 433         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 434                 return 64;
 435
 436         case PIPE_CAP_VENDOR_ID:
 437                 return 0x5143;
 438         case PIPE_CAP_DEVICE_ID:
 439                 return 0xFFFFFFFF;
 440         case PIPE_CAP_ACCELERATED:
 441                 return 1;
 442         case PIPE_CAP_VIDEO_MEMORY:
 443                 DBG("FINISHME: The value returned is incorrect\n");
 444                 return 10;
 445         case PIPE_CAP_UMA:
 446                 return 1;
 447         case PIPE_CAP_NATIVE_FENCE_FD:
 448                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 449         }
 450         debug_printf("unknown param %d\n", param);
 451         return 0;
 452 }
 453
 454 static float
 455 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 456 {
 457         switch (param) {
 458         case PIPE_CAPF_MAX_LINE_WIDTH:
 459         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 460                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 461                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 462                  * uses too small of a render target size, and gets confused when
 463                  * the lines start going offscreen.
 464                  *
 465                  * See: https://code.google.com/p/android/issues/detail?id=206513
 466                  */
 467                 if (fd_mesa_debug & FD_DBG_DEQP)
 468                         return 48.0f;
 469                 return 127.0f;
 470         case PIPE_CAPF_MAX_POINT_WIDTH:
 471         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 472                 return 4092.0f;
 473         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 474                 return 16.0f;
 475         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 476                 return 15.0f;
 477         case PIPE_CAPF_GUARD_BAND_LEFT:
 478         case PIPE_CAPF_GUARD_BAND_TOP:
 479         case PIPE_CAPF_GUARD_BAND_RIGHT:
 480         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 481                 return 0.0f;
 482         }
 483         debug_printf("unknown paramf %d\n", param);
 484         return 0;
 485 }
 486
 487 static int
 488 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 489                 enum pipe_shader_type shader,
 490                 enum pipe_shader_cap param)
 491 {
 492         struct fd_screen *screen = fd_screen(pscreen);
 493
 494         switch(shader)
 495         {
 496         case PIPE_SHADER_FRAGMENT:
 497         case PIPE_SHADER_VERTEX:
 498                 break;
 499         case PIPE_SHADER_COMPUTE:
 500                 if (has_compute(screen))
 501                         break;
 502                 return 0;
 503         case PIPE_SHADER_GEOMETRY:
 504                 /* maye we could emulate.. */
 505                 return 0;
 506         default:
 507                 DBG("unknown shader type %d", shader);
 508                 return 0;
 509         }
 510
 511         /* this is probably not totally correct.. but it's a start: */
 512         switch (param) {
 513         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 514         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 515         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 516         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 517                 return 16384;
 518         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 519                 return 8; /* XXX */
 520         case PIPE_SHADER_CAP_MAX_INPUTS:
 521         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 522                 return 16;
 523         case PIPE_SHADER_CAP_MAX_TEMPS:
 524                 return 64; /* Max native temporaries. */
 525         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 526                 /* NOTE: seems to be limit for a3xx is actually 512 but
 527                  * split between VS and FS.  Use lower limit of 256 to
 528                  * avoid getting into impossible situations:
 529                  */
 530                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 531         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 532                 return is_ir3(screen) ? 16 : 1;
 533         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 534                 return 1;
 535         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 536         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 537                 /* Technically this should be the same as for TEMP/CONST, since
 538                  * everything is just normal registers.  This is just temporary
 539                  * hack until load_input/store_output handle arrays in a similar
 540                  * way as load_var/store_var..
 541                  */
 542                 return 0;
 543         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 544         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 545                 /* a2xx compiler doesn't handle indirect: */
 546                 return is_ir3(screen) ? 1 : 0;
 547         case PIPE_SHADER_CAP_SUBROUTINES:
 548         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 549         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 550         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 551         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 552         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 553                 return 0;
 554         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 555                 return 1;
 556         case PIPE_SHADER_CAP_INTEGERS:
 557                 if (glsl120)
 558                         return 0;
 559                 return is_ir3(screen) ? 1 : 0;
 560         case PIPE_SHADER_CAP_INT64_ATOMICS:
 561                 return 0;
 562         case PIPE_SHADER_CAP_FP16:
 563                 return 0;
 564         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 565         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 566                 return 16;
 567         case PIPE_SHADER_CAP_PREFERRED_IR:
 568                 if (is_ir3(screen))
 569                         return PIPE_SHADER_IR_NIR;
 570                 return PIPE_SHADER_IR_TGSI;
 571         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 572                 if (is_ir3(screen)) {
 573                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 574                 } else {
 575                         return (1 << PIPE_SHADER_IR_TGSI);
 576                 }
 577                 return 0;
 578         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 579                 return 32;
 580         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 581         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 582         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 583         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 584                 return 0;
 585         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 586         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 587                 if (is_a5xx(screen)) {
 588                         /* a5xx (and a4xx for that matter) has one state-block
 589                          * for compute-shader SSBO's and another that is shared
 590                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 591                          * just advertise SSBOs for FS and CS.  We could possibly
 592                          * do what blob does, and partition the space for
 593                          * VS/HS/DS/GS/FS.  The blob advertises:
 594                          *
 595                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 596                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 597                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 598                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 599                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 600                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 601                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 602                          *
 603                          * I think that way we could avoid having to patch shaders
 604                          * for actual SSBO indexes by using a static partitioning.
 605                          *
 606                          * Note same state block is used for images and buffers,
 607                          * but images also need texture state for read access
 608                          * (isam/isam.3d)
 609                          */
 610                         switch(shader)
 611                         {
 612                         case PIPE_SHADER_FRAGMENT:
 613                         case PIPE_SHADER_COMPUTE:
 614                                 return 24;
 615                         default:
 616                                 return 0;
 617                         }
 618                 }
 619                 return 0;
 620         }
 621         debug_printf("unknown shader param %d\n", param);
 622         return 0;
 623 }
 624
 625 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 626  * into per-generation backend?
 627  */
 628 static int
 629 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 630                 enum pipe_compute_cap param, void *ret)
 631 {
 632         struct fd_screen *screen = fd_screen(pscreen);
 633         const char * const ir = "ir3";
 634
 635         if (!has_compute(screen))
 636                 return 0;
 637
 638         switch (param) {
 639         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 640                 if (ret) {
 641                         uint32_t *address_bits = ret;
 642                         address_bits[0] = 32;
 643
 644                         if (is_a5xx(screen))
 645                                 address_bits[0] = 64;
 646                 }
 647                 return 1 * sizeof(uint32_t);
 648
 649         case PIPE_COMPUTE_CAP_IR_TARGET:
 650                 if (ret)
 651                         sprintf(ret, ir);
 652                 return strlen(ir) * sizeof(char);
 653
 654         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 655                 if (ret) {
 656                         uint64_t *grid_dimension = ret;
 657                         grid_dimension[0] = 3;
 658                 }
 659                 return 1 * sizeof(uint64_t);
 660
 661         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 662                 if (ret) {
 663                         uint64_t *grid_size = ret;
 664                         grid_size[0] = 65535;
 665                         grid_size[1] = 65535;
 666                         grid_size[2] = 65535;
 667                 }
 668                 return 3 * sizeof(uint64_t) ;
 669
 670         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 671                 if (ret) {
 672                         uint64_t *block_size = ret;
 673                         block_size[0] = 1024;
 674                         block_size[1] = 1024;
 675                         block_size[2] = 64;
 676                 }
 677                 return 3 * sizeof(uint64_t) ;
 678
 679         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 680                 if (ret) {
 681                         uint64_t *max_threads_per_block = ret;
 682                         *max_threads_per_block = 1024;
 683                 }
 684                 return sizeof(uint64_t);
 685
 686         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 687         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 688                 if (ret) {
 689                         uint64_t *local_size = ret;
 690                         *local_size = 32768;
 691                 }
 692                 return sizeof(uint64_t);
 693         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 694         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 695                 break;
 696         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 697                 if (ret) {
 698                         uint64_t *max = ret;
 699                         *max = 32768;
 700                 }
 701                 return sizeof(uint64_t);
 702         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 703         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 704         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 705         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 706         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 707                 break;
 708         }
 709
 710         return 0;
 711 }
 712
 713 static const void *
 714 fd_get_compiler_options(struct pipe_screen *pscreen,
 715                 enum pipe_shader_ir ir, unsigned shader)
 716 {
 717         struct fd_screen *screen = fd_screen(pscreen);
 718
 719         if (is_ir3(screen))
 720                 return ir3_get_compiler_options(screen->compiler);
 721
 722         return NULL;
 723 }
 724
 725 boolean
 726 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 727                 struct fd_bo *bo,
 728                 unsigned stride,
 729                 struct winsys_handle *whandle)
 730 {
 731         whandle->stride = stride;
 732
 733         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 734                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 735         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 736                 whandle->handle = fd_bo_handle(bo);
 737                 return TRUE;
 738         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 739                 whandle->handle = fd_bo_dmabuf(bo);
 740                 return TRUE;
 741         } else {
 742                 return FALSE;
 743         }
 744 }
 745
 746 struct fd_bo *
 747 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 748                 struct winsys_handle *whandle)
 749 {
 750         struct fd_screen *screen = fd_screen(pscreen);
 751         struct fd_bo *bo;
 752
 753         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 754                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 755         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 756                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 757         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 758                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 759         } else {
 760                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 761                 return NULL;
 762         }
 763
 764         if (!bo) {
 765                 DBG("ref name 0x%08x failed", whandle->handle);
 766                 return NULL;
 767         }
 768
 769         return bo;
 770 }
 771
 772 struct pipe_screen *
 773 fd_screen_create(struct fd_device *dev)
 774 {
 775         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 776         struct pipe_screen *pscreen;
 777         uint64_t val;
 778
 779         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 780
 781         if (fd_mesa_debug & FD_DBG_NOBIN)
 782                 fd_binning_enabled = false;
 783
 784         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 785
 786         if (!screen)
 787                 return NULL;
 788
 789         pscreen = &screen->base;
 790
 791         screen->dev = dev;
 792         screen->refcnt = 1;
 793
 794         // maybe this should be in context?
 795         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 796         if (!screen->pipe) {
 797                 DBG("could not create 3d pipe");
 798                 goto fail;
 799         }
 800
 801         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 802                 DBG("could not get GMEM size");
 803                 goto fail;
 804         }
 805         screen->gmemsize_bytes = val;
 806
 807         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 808                 DBG("could not get device-id");
 809                 goto fail;
 810         }
 811         screen->device_id = val;
 812
 813         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 814                 DBG("could not get gpu freq");
 815                 /* this limits what performance related queries are
 816                  * supported but is not fatal
 817                  */
 818                 screen->max_freq = 0;
 819         } else {
 820                 screen->max_freq = val;
 821                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 822                         screen->has_timestamp = true;
 823         }
 824
 825         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 826                 DBG("could not get gpu-id");
 827                 goto fail;
 828         }
 829         screen->gpu_id = val;
 830
 831         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 832                 DBG("could not get chip-id");
 833                 /* older kernels may not have this property: */
 834                 unsigned core  = screen->gpu_id / 100;
 835                 unsigned major = (screen->gpu_id % 100) / 10;
 836                 unsigned minor = screen->gpu_id % 10;
 837                 unsigned patch = 0;  /* assume the worst */
 838                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 839                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 840         }
 841         screen->chip_id = val;
 842
 843         DBG("Pipe Info:");
 844         DBG(" GPU-id:          %d", screen->gpu_id);
 845         DBG(" Chip-id:         0x%08x", screen->chip_id);
 846         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 847
 848         /* explicitly checking for GPU revisions that are known to work.  This
 849          * may be overly conservative for a3xx, where spoofing the gpu_id with
 850          * the blob driver seems to generate identical cmdstream dumps.  But
 851          * on a2xx, there seem to be small differences between the GPU revs
 852          * so it is probably better to actually test first on real hardware
 853          * before enabling:
 854          *
 855          * If you have a different adreno version, feel free to add it to one
 856          * of the cases below and see what happens.  And if it works, please
 857          * send a patch ;-)
 858          */
 859         switch (screen->gpu_id) {
 860         case 220:
 861                 fd2_screen_init(pscreen);
 862                 break;
 863         case 305:
 864         case 307:
 865         case 320:
 866         case 330:
 867                 fd3_screen_init(pscreen);
 868                 break;
 869         case 420:
 870         case 430:
 871                 fd4_screen_init(pscreen);
 872                 break;
 873         case 530:
 874                 fd5_screen_init(pscreen);
 875                 break;
 876         default:
 877                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 878                 goto fail;
 879         }
 880
 881         if (screen->gpu_id >= 500) {
 882                 screen->gmem_alignw = 64;
 883                 screen->gmem_alignh = 32;
 884                 screen->num_vsc_pipes = 16;
 885         } else {
 886                 screen->gmem_alignw = 32;
 887                 screen->gmem_alignh = 32;
 888                 screen->num_vsc_pipes = 8;
 889         }
 890
 891         /* NOTE: don't enable reordering on a2xx, since completely untested.
 892          * Also, don't enable if we have too old of a kernel to support
 893          * growable cmdstream buffers, since memory requirement for cmdstream
 894          * buffers would be too much otherwise.
 895          */
 896         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 897                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 898
 899         fd_bc_init(&screen->batch_cache);
 900
 901         (void) mtx_init(&screen->lock, mtx_plain);
 902
 903         pscreen->destroy = fd_screen_destroy;
 904         pscreen->get_param = fd_screen_get_param;
 905         pscreen->get_paramf = fd_screen_get_paramf;
 906         pscreen->get_shader_param = fd_screen_get_shader_param;
 907         pscreen->get_compute_param = fd_get_compute_param;
 908         pscreen->get_compiler_options = fd_get_compiler_options;
 909
 910         fd_resource_screen_init(pscreen);
 911         fd_query_screen_init(pscreen);
 912
 913         pscreen->get_name = fd_screen_get_name;
 914         pscreen->get_vendor = fd_screen_get_vendor;
 915         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 916
 917         pscreen->get_timestamp = fd_screen_get_timestamp;
 918
 919         pscreen->fence_reference = fd_fence_ref;
 920         pscreen->fence_finish = fd_fence_finish;
 921         pscreen->fence_get_fd = fd_fence_get_fd;
 922
 923         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 924
 925         return pscreen;
 926
 927 fail:
 928         fd_screen_destroy(pscreen);
 929         return NULL;
 930 }