src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  79                 {"reorder",   FD_DBG_REORDER,"Enable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 DEBUG_NAMED_VALUE_END
  82 };
  83
  84 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  85
  86 int fd_mesa_debug = 0;
  87 bool fd_binning_enabled = true;
  88 static bool glsl120 = false;
  89
  90 static const char *
  91 fd_screen_get_name(struct pipe_screen *pscreen)
  92 {
  93         static char buffer[128];
  94         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  95                         fd_screen(pscreen)->device_id);
  96         return buffer;
  97 }
  98
  99 static const char *
 100 fd_screen_get_vendor(struct pipe_screen *pscreen)
 101 {
 102         return "freedreno";
 103 }
 104
 105 static const char *
 106 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 107 {
 108         return "Qualcomm";
 109 }
 110
 111
 112 static uint64_t
 113 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 114 {
 115         struct fd_screen *screen = fd_screen(pscreen);
 116
 117         if (screen->has_timestamp) {
 118                 uint64_t n;
 119                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 120                 debug_assert(screen->max_freq > 0);
 121                 return n * 1000000000 / screen->max_freq;
 122         } else {
 123                 int64_t cpu_time = os_time_get() * 1000;
 124                 return cpu_time + screen->cpu_gpu_time_delta;
 125         }
 126
 127 }
 128
 129 static void
 130 fd_screen_destroy(struct pipe_screen *pscreen)
 131 {
 132         struct fd_screen *screen = fd_screen(pscreen);
 133
 134         if (screen->pipe)
 135                 fd_pipe_del(screen->pipe);
 136
 137         if (screen->dev)
 138                 fd_device_del(screen->dev);
 139
 140         fd_bc_fini(&screen->batch_cache);
 141
 142         slab_destroy_parent(&screen->transfer_pool);
 143
 144         pipe_mutex_destroy(screen->lock);
 145
 146         free(screen);
 147 }
 148
 149 /*
 150 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 151 tables for things that differ if the delta is not too much..
 152  */
 153 static int
 154 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 155 {
 156         struct fd_screen *screen = fd_screen(pscreen);
 157
 158         /* this is probably not totally correct.. but it's a start: */
 159         switch (param) {
 160         /* Supported features (boolean caps). */
 161         case PIPE_CAP_NPOT_TEXTURES:
 162         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 163         case PIPE_CAP_TWO_SIDED_STENCIL:
 164         case PIPE_CAP_ANISOTROPIC_FILTER:
 165         case PIPE_CAP_POINT_SPRITE:
 166         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 167         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 168         case PIPE_CAP_TEXTURE_SWIZZLE:
 169         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 170         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 171         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 172         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 173         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 174         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 175         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 176         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 177         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 178         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 179         case PIPE_CAP_VERTEXID_NOBASE:
 180         case PIPE_CAP_STRING_MARKER:
 181         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 182                 return 1;
 183
 184         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 185                 return is_a4xx(screen) ? 0 : 1;
 186
 187         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 188         case PIPE_CAP_TGSI_TEXCOORD:
 189         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 190         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 191         case PIPE_CAP_TEXTURE_BARRIER:
 192         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 193         case PIPE_CAP_COMPUTE:
 194         case PIPE_CAP_QUERY_MEMORY_INFO:
 195         case PIPE_CAP_PCI_GROUP:
 196         case PIPE_CAP_PCI_BUS:
 197         case PIPE_CAP_PCI_DEVICE:
 198         case PIPE_CAP_PCI_FUNCTION:
 199                 return 0;
 200
 201         case PIPE_CAP_SM3:
 202         case PIPE_CAP_PRIMITIVE_RESTART:
 203         case PIPE_CAP_TGSI_INSTANCEID:
 204         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 205         case PIPE_CAP_INDEP_BLEND_ENABLE:
 206         case PIPE_CAP_INDEP_BLEND_FUNC:
 207         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 209         case PIPE_CAP_CONDITIONAL_RENDER:
 210         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 211         case PIPE_CAP_FAKE_SW_MSAA:
 212         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 213         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 214         case PIPE_CAP_CLIP_HALFZ:
 215                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 216
 217         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 218                 return 0;
 219         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 220                 if (is_a3xx(screen)) return 16;
 221                 if (is_a4xx(screen)) return 32;
 222                 if (is_a5xx(screen)) return 32;
 223                 return 0;
 224         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 225                 /* We could possibly emulate more by pretending 2d/rect textures and
 226                  * splitting high bits of index into 2nd dimension..
 227                  */
 228                 if (is_a3xx(screen)) return 8192;
 229                 if (is_a4xx(screen)) return 16384;
 230                 if (is_a5xx(screen)) return 16384;
 231                 return 0;
 232
 233         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 234         case PIPE_CAP_CUBE_MAP_ARRAY:
 235         case PIPE_CAP_START_INSTANCE:
 236         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 237         case PIPE_CAP_TEXTURE_QUERY_LOD:
 238                 return is_a4xx(screen) || is_a5xx(screen);
 239
 240         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 241                 return 64;
 242
 243         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 244                 if (glsl120)
 245                         return 120;
 246                 // XXX temporary, avoid issues with glamor:
 247                 if (is_a5xx(screen))
 248                         return 120;
 249                 return is_ir3(screen) ? 140 : 120;
 250
 251         /* Unsupported features. */
 252         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 253         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 254         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 255         case PIPE_CAP_USER_VERTEX_BUFFERS:
 256         case PIPE_CAP_USER_INDEX_BUFFERS:
 257         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 258         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 259         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 260         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 261         case PIPE_CAP_TEXTURE_GATHER_SM5:
 262         case PIPE_CAP_SAMPLE_SHADING:
 263         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 264         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 265         case PIPE_CAP_DRAW_INDIRECT:
 266         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 267         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 268         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 269         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 270         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 271         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 272         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 273         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 274         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 275         case PIPE_CAP_TGSI_TXQS:
 276         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 277         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 278         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 279         case PIPE_CAP_CLEAR_TEXTURE:
 280         case PIPE_CAP_DRAW_PARAMETERS:
 281         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 282         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 283         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 284         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 285         case PIPE_CAP_INVALIDATE_BUFFER:
 286         case PIPE_CAP_GENERATE_MIPMAP:
 287         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 288         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 289         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 290         case PIPE_CAP_CULL_DISTANCE:
 291         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 292         case PIPE_CAP_TGSI_VOTE:
 293         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 294         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 295         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 296         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 297         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 298         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 299                 return 0;
 300
 301         case PIPE_CAP_MAX_VIEWPORTS:
 302                 return 1;
 303
 304         case PIPE_CAP_SHAREABLE_SHADERS:
 305         /* manage the variants for these ourself, to avoid breaking precompile: */
 306         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 307         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 308                 if (is_ir3(screen))
 309                         return 1;
 310                 return 0;
 311
 312         /* Stream output. */
 313         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 314                 if (is_ir3(screen))
 315                         return PIPE_MAX_SO_BUFFERS;
 316                 return 0;
 317         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 318         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 319                 if (is_ir3(screen))
 320                         return 1;
 321                 return 0;
 322         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 323         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 324                 if (is_ir3(screen))
 325                         return 16 * 4;   /* should only be shader out limit? */
 326                 return 0;
 327
 328         /* Geometry shader output, unsupported. */
 329         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 330         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 331         case PIPE_CAP_MAX_VERTEX_STREAMS:
 332                 return 0;
 333
 334         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 335                 return 2048;
 336
 337         /* Texturing. */
 338         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 339         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 340                 return MAX_MIP_LEVELS;
 341         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 342                 return 11;
 343
 344         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 345                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 346
 347         /* Render targets. */
 348         case PIPE_CAP_MAX_RENDER_TARGETS:
 349                 return screen->max_rts;
 350         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 351                 return is_a3xx(screen) ? 1 : 0;
 352
 353         /* Queries. */
 354         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 355                 return 0;
 356         case PIPE_CAP_OCCLUSION_QUERY:
 357                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 358         case PIPE_CAP_QUERY_TIMESTAMP:
 359         case PIPE_CAP_QUERY_TIME_ELAPSED:
 360                 /* only a4xx, requires new enough kernel so we know max_freq: */
 361                 return (screen->max_freq > 0) && is_a4xx(screen);
 362
 363         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 364         case PIPE_CAP_MIN_TEXEL_OFFSET:
 365                 return -8;
 366
 367         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 368         case PIPE_CAP_MAX_TEXEL_OFFSET:
 369                 return 7;
 370
 371         case PIPE_CAP_ENDIANNESS:
 372                 return PIPE_ENDIAN_LITTLE;
 373
 374         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 375                 return 64;
 376
 377         case PIPE_CAP_VENDOR_ID:
 378                 return 0x5143;
 379         case PIPE_CAP_DEVICE_ID:
 380                 return 0xFFFFFFFF;
 381         case PIPE_CAP_ACCELERATED:
 382                 return 1;
 383         case PIPE_CAP_VIDEO_MEMORY:
 384                 DBG("FINISHME: The value returned is incorrect\n");
 385                 return 10;
 386         case PIPE_CAP_UMA:
 387                 return 1;
 388         case PIPE_CAP_NATIVE_FENCE_FD:
 389                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 390         }
 391         debug_printf("unknown param %d\n", param);
 392         return 0;
 393 }
 394
 395 static float
 396 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 397 {
 398         switch (param) {
 399         case PIPE_CAPF_MAX_LINE_WIDTH:
 400         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 401                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 402                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 403                  * uses too small of a render target size, and gets confused when
 404                  * the lines start going offscreen.
 405                  *
 406                  * See: https://code.google.com/p/android/issues/detail?id=206513
 407                  */
 408                 if (fd_mesa_debug & FD_DBG_DEQP)
 409                         return 48.0f;
 410                 return 127.0f;
 411         case PIPE_CAPF_MAX_POINT_WIDTH:
 412         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 413                 return 4092.0f;
 414         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 415                 return 16.0f;
 416         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 417                 return 15.0f;
 418         case PIPE_CAPF_GUARD_BAND_LEFT:
 419         case PIPE_CAPF_GUARD_BAND_TOP:
 420         case PIPE_CAPF_GUARD_BAND_RIGHT:
 421         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 422                 return 0.0f;
 423         }
 424         debug_printf("unknown paramf %d\n", param);
 425         return 0;
 426 }
 427
 428 static int
 429 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 430                 enum pipe_shader_cap param)
 431 {
 432         struct fd_screen *screen = fd_screen(pscreen);
 433
 434         switch(shader)
 435         {
 436         case PIPE_SHADER_FRAGMENT:
 437         case PIPE_SHADER_VERTEX:
 438                 break;
 439         case PIPE_SHADER_COMPUTE:
 440         case PIPE_SHADER_GEOMETRY:
 441                 /* maye we could emulate.. */
 442                 return 0;
 443         default:
 444                 DBG("unknown shader type %d", shader);
 445                 return 0;
 446         }
 447
 448         /* this is probably not totally correct.. but it's a start: */
 449         switch (param) {
 450         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 451         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 452         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 453         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 454                 return 16384;
 455         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 456                 return 8; /* XXX */
 457         case PIPE_SHADER_CAP_MAX_INPUTS:
 458         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 459                 return 16;
 460         case PIPE_SHADER_CAP_MAX_TEMPS:
 461                 return 64; /* Max native temporaries. */
 462         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 463                 /* NOTE: seems to be limit for a3xx is actually 512 but
 464                  * split between VS and FS.  Use lower limit of 256 to
 465                  * avoid getting into impossible situations:
 466                  */
 467                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 468         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 469                 return is_ir3(screen) ? 16 : 1;
 470         case PIPE_SHADER_CAP_MAX_PREDS:
 471                 return 0; /* nothing uses this */
 472         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 473                 return 1;
 474         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 475         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 476                 /* Technically this should be the same as for TEMP/CONST, since
 477                  * everything is just normal registers.  This is just temporary
 478                  * hack until load_input/store_output handle arrays in a similar
 479                  * way as load_var/store_var..
 480                  */
 481                 return 0;
 482         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 483         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 484                 /* a2xx compiler doesn't handle indirect: */
 485                 return is_ir3(screen) ? 1 : 0;
 486         case PIPE_SHADER_CAP_SUBROUTINES:
 487         case PIPE_SHADER_CAP_DOUBLES:
 488         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 489         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 490         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 491         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 492                 return 0;
 493         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 494                 return 1;
 495         case PIPE_SHADER_CAP_INTEGERS:
 496                 if (glsl120)
 497                         return 0;
 498                 return is_ir3(screen) ? 1 : 0;
 499         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 500         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 501                 return 16;
 502         case PIPE_SHADER_CAP_PREFERRED_IR:
 503                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 504                         return PIPE_SHADER_IR_NIR;
 505                 return PIPE_SHADER_IR_TGSI;
 506         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 507                 return 0;
 508         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 509                 return 32;
 510         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 511         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 512         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 513                 return 0;
 514         }
 515         debug_printf("unknown shader param %d\n", param);
 516         return 0;
 517 }
 518
 519 static const void *
 520 fd_get_compiler_options(struct pipe_screen *pscreen,
 521                 enum pipe_shader_ir ir, unsigned shader)
 522 {
 523         struct fd_screen *screen = fd_screen(pscreen);
 524
 525         if (is_ir3(screen))
 526                 return ir3_get_compiler_options();
 527
 528         return NULL;
 529 }
 530
 531 boolean
 532 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 533                 struct fd_bo *bo,
 534                 unsigned stride,
 535                 struct winsys_handle *whandle)
 536 {
 537         whandle->stride = stride;
 538
 539         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 540                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 541         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 542                 whandle->handle = fd_bo_handle(bo);
 543                 return TRUE;
 544         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 545                 whandle->handle = fd_bo_dmabuf(bo);
 546                 return TRUE;
 547         } else {
 548                 return FALSE;
 549         }
 550 }
 551
 552 struct fd_bo *
 553 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 554                 struct winsys_handle *whandle)
 555 {
 556         struct fd_screen *screen = fd_screen(pscreen);
 557         struct fd_bo *bo;
 558
 559         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 560                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 561         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 562                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 563         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 564                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 565         } else {
 566                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 567                 return NULL;
 568         }
 569
 570         if (!bo) {
 571                 DBG("ref name 0x%08x failed", whandle->handle);
 572                 return NULL;
 573         }
 574
 575         return bo;
 576 }
 577
 578 struct pipe_screen *
 579 fd_screen_create(struct fd_device *dev)
 580 {
 581         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 582         struct pipe_screen *pscreen;
 583         uint64_t val;
 584
 585         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 586
 587         if (fd_mesa_debug & FD_DBG_NOBIN)
 588                 fd_binning_enabled = false;
 589
 590         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 591
 592         if (!screen)
 593                 return NULL;
 594
 595         pscreen = &screen->base;
 596
 597         screen->dev = dev;
 598         screen->refcnt = 1;
 599
 600         // maybe this should be in context?
 601         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 602         if (!screen->pipe) {
 603                 DBG("could not create 3d pipe");
 604                 goto fail;
 605         }
 606
 607         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 608                 DBG("could not get GMEM size");
 609                 goto fail;
 610         }
 611         screen->gmemsize_bytes = val;
 612
 613         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 614                 DBG("could not get device-id");
 615                 goto fail;
 616         }
 617         screen->device_id = val;
 618
 619         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 620                 DBG("could not get gpu freq");
 621                 /* this limits what performance related queries are
 622                  * supported but is not fatal
 623                  */
 624                 screen->max_freq = 0;
 625         } else {
 626                 screen->max_freq = val;
 627                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 628                         screen->has_timestamp = true;
 629         }
 630
 631         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 632                 DBG("could not get gpu-id");
 633                 goto fail;
 634         }
 635         screen->gpu_id = val;
 636
 637         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 638                 DBG("could not get chip-id");
 639                 /* older kernels may not have this property: */
 640                 unsigned core  = screen->gpu_id / 100;
 641                 unsigned major = (screen->gpu_id % 100) / 10;
 642                 unsigned minor = screen->gpu_id % 10;
 643                 unsigned patch = 0;  /* assume the worst */
 644                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 645                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 646         }
 647         screen->chip_id = val;
 648
 649         DBG("Pipe Info:");
 650         DBG(" GPU-id:          %d", screen->gpu_id);
 651         DBG(" Chip-id:         0x%08x", screen->chip_id);
 652         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 653
 654         /* explicitly checking for GPU revisions that are known to work.  This
 655          * may be overly conservative for a3xx, where spoofing the gpu_id with
 656          * the blob driver seems to generate identical cmdstream dumps.  But
 657          * on a2xx, there seem to be small differences between the GPU revs
 658          * so it is probably better to actually test first on real hardware
 659          * before enabling:
 660          *
 661          * If you have a different adreno version, feel free to add it to one
 662          * of the cases below and see what happens.  And if it works, please
 663          * send a patch ;-)
 664          */
 665         switch (screen->gpu_id) {
 666         case 220:
 667                 fd2_screen_init(pscreen);
 668                 break;
 669         case 305:
 670         case 307:
 671         case 320:
 672         case 330:
 673                 fd3_screen_init(pscreen);
 674                 break;
 675         case 420:
 676         case 430:
 677                 fd4_screen_init(pscreen);
 678                 break;
 679         case 530:
 680                 fd5_screen_init(pscreen);
 681                 break;
 682         default:
 683                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 684                 goto fail;
 685         }
 686
 687         if (screen->gpu_id >= 500) {
 688                 screen->gmem_alignw = 64;
 689                 screen->gmem_alignh = 32;
 690         } else {
 691                 screen->gmem_alignw = 32;
 692                 screen->gmem_alignh = 32;
 693         }
 694
 695         /* NOTE: don't enable reordering on a2xx, since completely untested.
 696          * Also, don't enable if we have too old of a kernel to support
 697          * growable cmdstream buffers, since memory requirement for cmdstream
 698          * buffers would be too much otherwise.
 699          */
 700         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 701                 screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
 702
 703         fd_bc_init(&screen->batch_cache);
 704
 705         pipe_mutex_init(screen->lock);
 706
 707         pscreen->destroy = fd_screen_destroy;
 708         pscreen->get_param = fd_screen_get_param;
 709         pscreen->get_paramf = fd_screen_get_paramf;
 710         pscreen->get_shader_param = fd_screen_get_shader_param;
 711         pscreen->get_compiler_options = fd_get_compiler_options;
 712
 713         fd_resource_screen_init(pscreen);
 714         fd_query_screen_init(pscreen);
 715
 716         pscreen->get_name = fd_screen_get_name;
 717         pscreen->get_vendor = fd_screen_get_vendor;
 718         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 719
 720         pscreen->get_timestamp = fd_screen_get_timestamp;
 721
 722         pscreen->fence_reference = fd_fence_ref;
 723         pscreen->fence_finish = fd_fence_finish;
 724         pscreen->fence_get_fd = fd_fence_get_fd;
 725
 726         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 727
 728         util_format_s3tc_init();
 729
 730         return pscreen;
 731
 732 fail:
 733         fd_screen_destroy(pscreen);
 734         return NULL;
 735 }