src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 #include "ir3/ir3_nir.h"
  58
  59 /* XXX this should go away */
  60 #include "state_tracker/drm_driver.h"
  61
  62 static const struct debug_named_value debug_options[] = {
  63                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  64                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  65                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  66                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  67                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  68                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  69                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  70                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  71                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  72                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  73                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  74                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  75                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  76                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  77                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  78                 {"reorder",   FD_DBG_REORDER,"Enable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 DEBUG_NAMED_VALUE_END
  81 };
  82
  83 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  84
  85 int fd_mesa_debug = 0;
  86 bool fd_binning_enabled = true;
  87 static bool glsl120 = false;
  88
  89 static const char *
  90 fd_screen_get_name(struct pipe_screen *pscreen)
  91 {
  92         static char buffer[128];
  93         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  94                         fd_screen(pscreen)->device_id);
  95         return buffer;
  96 }
  97
  98 static const char *
  99 fd_screen_get_vendor(struct pipe_screen *pscreen)
 100 {
 101         return "freedreno";
 102 }
 103
 104 static const char *
 105 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 106 {
 107         return "Qualcomm";
 108 }
 109
 110
 111 static uint64_t
 112 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 113 {
 114         struct fd_screen *screen = fd_screen(pscreen);
 115
 116         if (screen->has_timestamp) {
 117                 uint64_t n;
 118                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 119                 debug_assert(screen->max_freq > 0);
 120                 return n * 1000000000 / screen->max_freq;
 121         } else {
 122                 int64_t cpu_time = os_time_get() * 1000;
 123                 return cpu_time + screen->cpu_gpu_time_delta;
 124         }
 125
 126 }
 127
 128 static void
 129 fd_screen_destroy(struct pipe_screen *pscreen)
 130 {
 131         struct fd_screen *screen = fd_screen(pscreen);
 132
 133         if (screen->pipe)
 134                 fd_pipe_del(screen->pipe);
 135
 136         if (screen->dev)
 137                 fd_device_del(screen->dev);
 138
 139         fd_bc_fini(&screen->batch_cache);
 140
 141         pipe_mutex_destroy(screen->lock);
 142
 143         free(screen);
 144 }
 145
 146 /*
 147 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 148 tables for things that differ if the delta is not too much..
 149  */
 150 static int
 151 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 152 {
 153         struct fd_screen *screen = fd_screen(pscreen);
 154
 155         /* this is probably not totally correct.. but it's a start: */
 156         switch (param) {
 157         /* Supported features (boolean caps). */
 158         case PIPE_CAP_NPOT_TEXTURES:
 159         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 160         case PIPE_CAP_TWO_SIDED_STENCIL:
 161         case PIPE_CAP_ANISOTROPIC_FILTER:
 162         case PIPE_CAP_POINT_SPRITE:
 163         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 164         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165         case PIPE_CAP_TEXTURE_SWIZZLE:
 166         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 167         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 169         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 170         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 171         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 172         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 173         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 174         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 175         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 176         case PIPE_CAP_VERTEXID_NOBASE:
 177         case PIPE_CAP_STRING_MARKER:
 178                 return 1;
 179
 180         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 181                 return is_a4xx(screen) ? 0 : 1;
 182
 183         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 184         case PIPE_CAP_TGSI_TEXCOORD:
 185         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 186         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 187         case PIPE_CAP_TEXTURE_BARRIER:
 188         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 189         case PIPE_CAP_COMPUTE:
 190         case PIPE_CAP_QUERY_MEMORY_INFO:
 191         case PIPE_CAP_PCI_GROUP:
 192         case PIPE_CAP_PCI_BUS:
 193         case PIPE_CAP_PCI_DEVICE:
 194         case PIPE_CAP_PCI_FUNCTION:
 195                 return 0;
 196
 197         case PIPE_CAP_SM3:
 198         case PIPE_CAP_PRIMITIVE_RESTART:
 199         case PIPE_CAP_TGSI_INSTANCEID:
 200         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 201         case PIPE_CAP_INDEP_BLEND_ENABLE:
 202         case PIPE_CAP_INDEP_BLEND_FUNC:
 203         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 204         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 205         case PIPE_CAP_CONDITIONAL_RENDER:
 206         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 207         case PIPE_CAP_FAKE_SW_MSAA:
 208         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 209         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 210         case PIPE_CAP_CLIP_HALFZ:
 211                 return is_a3xx(screen) || is_a4xx(screen);
 212
 213         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 214                 return 0;
 215         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 216                 if (is_a3xx(screen)) return 16;
 217                 if (is_a4xx(screen)) return 32;
 218                 return 0;
 219         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 220                 /* We could possibly emulate more by pretending 2d/rect textures and
 221                  * splitting high bits of index into 2nd dimension..
 222                  */
 223                 if (is_a3xx(screen)) return 8192;
 224                 if (is_a4xx(screen)) return 16384;
 225                 return 0;
 226
 227         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 228         case PIPE_CAP_CUBE_MAP_ARRAY:
 229         case PIPE_CAP_START_INSTANCE:
 230         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 231         case PIPE_CAP_TEXTURE_QUERY_LOD:
 232                 return is_a4xx(screen);
 233
 234         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 235                 return 64;
 236
 237         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 238                 if (glsl120)
 239                         return 120;
 240                 return is_ir3(screen) ? 140 : 120;
 241
 242         /* Unsupported features. */
 243         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 244         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 245         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 246         case PIPE_CAP_USER_VERTEX_BUFFERS:
 247         case PIPE_CAP_USER_INDEX_BUFFERS:
 248         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 249         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 250         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 251         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 252         case PIPE_CAP_TEXTURE_GATHER_SM5:
 253         case PIPE_CAP_SAMPLE_SHADING:
 254         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 255         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 256         case PIPE_CAP_DRAW_INDIRECT:
 257         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 258         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 259         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 260         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 261         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 262         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 263         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 264         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 265         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 266         case PIPE_CAP_TGSI_TXQS:
 267         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 268         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 269         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 270         case PIPE_CAP_CLEAR_TEXTURE:
 271         case PIPE_CAP_DRAW_PARAMETERS:
 272         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 273         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 274         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 275         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 276         case PIPE_CAP_INVALIDATE_BUFFER:
 277         case PIPE_CAP_GENERATE_MIPMAP:
 278         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 279         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 280         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 281         case PIPE_CAP_CULL_DISTANCE:
 282         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 283         case PIPE_CAP_TGSI_VOTE:
 284         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 285         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 286         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 287                 return 0;
 288
 289         case PIPE_CAP_MAX_VIEWPORTS:
 290                 return 1;
 291
 292         case PIPE_CAP_SHAREABLE_SHADERS:
 293         /* manage the variants for these ourself, to avoid breaking precompile: */
 294         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 295         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 296                 if (is_ir3(screen))
 297                         return 1;
 298                 return 0;
 299
 300         /* Stream output. */
 301         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 302                 if (is_ir3(screen))
 303                         return PIPE_MAX_SO_BUFFERS;
 304                 return 0;
 305         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 306                 if (is_ir3(screen))
 307                         return 1;
 308                 return 0;
 309         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 310         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 311                 if (is_ir3(screen))
 312                         return 16 * 4;   /* should only be shader out limit? */
 313                 return 0;
 314
 315         /* Geometry shader output, unsupported. */
 316         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 317         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 318         case PIPE_CAP_MAX_VERTEX_STREAMS:
 319                 return 0;
 320
 321         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 322                 return 2048;
 323
 324         /* Texturing. */
 325         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 326         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 327                 return MAX_MIP_LEVELS;
 328         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 329                 return 11;
 330
 331         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 332                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 333
 334         /* Render targets. */
 335         case PIPE_CAP_MAX_RENDER_TARGETS:
 336                 return screen->max_rts;
 337         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 338                 return is_a3xx(screen) ? 1 : 0;
 339
 340         /* Queries. */
 341         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 342                 return 0;
 343         case PIPE_CAP_OCCLUSION_QUERY:
 344                 return is_a3xx(screen) || is_a4xx(screen);
 345         case PIPE_CAP_QUERY_TIMESTAMP:
 346         case PIPE_CAP_QUERY_TIME_ELAPSED:
 347                 /* only a4xx, requires new enough kernel so we know max_freq: */
 348                 return (screen->max_freq > 0) && is_a4xx(screen);
 349
 350         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 351         case PIPE_CAP_MIN_TEXEL_OFFSET:
 352                 return -8;
 353
 354         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 355         case PIPE_CAP_MAX_TEXEL_OFFSET:
 356                 return 7;
 357
 358         case PIPE_CAP_ENDIANNESS:
 359                 return PIPE_ENDIAN_LITTLE;
 360
 361         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 362                 return 64;
 363
 364         case PIPE_CAP_VENDOR_ID:
 365                 return 0x5143;
 366         case PIPE_CAP_DEVICE_ID:
 367                 return 0xFFFFFFFF;
 368         case PIPE_CAP_ACCELERATED:
 369                 return 1;
 370         case PIPE_CAP_VIDEO_MEMORY:
 371                 DBG("FINISHME: The value returned is incorrect\n");
 372                 return 10;
 373         case PIPE_CAP_UMA:
 374                 return 1;
 375         }
 376         debug_printf("unknown param %d\n", param);
 377         return 0;
 378 }
 379
 380 static float
 381 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 382 {
 383         switch (param) {
 384         case PIPE_CAPF_MAX_LINE_WIDTH:
 385         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 386                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 387                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 388                  * uses too small of a render target size, and gets confused when
 389                  * the lines start going offscreen.
 390                  *
 391                  * See: https://code.google.com/p/android/issues/detail?id=206513
 392                  */
 393                 if (fd_mesa_debug & FD_DBG_DEQP)
 394                         return 48.0f;
 395                 return 127.0f;
 396         case PIPE_CAPF_MAX_POINT_WIDTH:
 397         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 398                 return 4092.0f;
 399         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 400                 return 16.0f;
 401         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 402                 return 15.0f;
 403         case PIPE_CAPF_GUARD_BAND_LEFT:
 404         case PIPE_CAPF_GUARD_BAND_TOP:
 405         case PIPE_CAPF_GUARD_BAND_RIGHT:
 406         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 407                 return 0.0f;
 408         }
 409         debug_printf("unknown paramf %d\n", param);
 410         return 0;
 411 }
 412
 413 static int
 414 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 415                 enum pipe_shader_cap param)
 416 {
 417         struct fd_screen *screen = fd_screen(pscreen);
 418
 419         switch(shader)
 420         {
 421         case PIPE_SHADER_FRAGMENT:
 422         case PIPE_SHADER_VERTEX:
 423                 break;
 424         case PIPE_SHADER_COMPUTE:
 425         case PIPE_SHADER_GEOMETRY:
 426                 /* maye we could emulate.. */
 427                 return 0;
 428         default:
 429                 DBG("unknown shader type %d", shader);
 430                 return 0;
 431         }
 432
 433         /* this is probably not totally correct.. but it's a start: */
 434         switch (param) {
 435         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 436         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 437         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 438         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 439                 return 16384;
 440         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 441                 return 8; /* XXX */
 442         case PIPE_SHADER_CAP_MAX_INPUTS:
 443         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 444                 return 16;
 445         case PIPE_SHADER_CAP_MAX_TEMPS:
 446                 return 64; /* Max native temporaries. */
 447         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 448                 /* NOTE: seems to be limit for a3xx is actually 512 but
 449                  * split between VS and FS.  Use lower limit of 256 to
 450                  * avoid getting into impossible situations:
 451                  */
 452                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 453         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 454                 return is_ir3(screen) ? 16 : 1;
 455         case PIPE_SHADER_CAP_MAX_PREDS:
 456                 return 0; /* nothing uses this */
 457         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 458                 return 1;
 459         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 460         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 461                 /* Technically this should be the same as for TEMP/CONST, since
 462                  * everything is just normal registers.  This is just temporary
 463                  * hack until load_input/store_output handle arrays in a similar
 464                  * way as load_var/store_var..
 465                  */
 466                 return 0;
 467         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 468         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 469                 /* a2xx compiler doesn't handle indirect: */
 470                 return is_ir3(screen) ? 1 : 0;
 471         case PIPE_SHADER_CAP_SUBROUTINES:
 472         case PIPE_SHADER_CAP_DOUBLES:
 473         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 474         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 475         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 476         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 477                 return 0;
 478         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 479                 return 1;
 480         case PIPE_SHADER_CAP_INTEGERS:
 481                 if (glsl120)
 482                         return 0;
 483                 return is_ir3(screen) ? 1 : 0;
 484         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 485         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 486                 return 16;
 487         case PIPE_SHADER_CAP_PREFERRED_IR:
 488                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 489                         return PIPE_SHADER_IR_NIR;
 490                 return PIPE_SHADER_IR_TGSI;
 491         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 492                 return 0;
 493         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 494                 return 32;
 495         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 496         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 497                 return 0;
 498         }
 499         debug_printf("unknown shader param %d\n", param);
 500         return 0;
 501 }
 502
 503 static const void *
 504 fd_get_compiler_options(struct pipe_screen *pscreen,
 505                 enum pipe_shader_ir ir, unsigned shader)
 506 {
 507         struct fd_screen *screen = fd_screen(pscreen);
 508
 509         if (is_ir3(screen))
 510                 return ir3_get_compiler_options();
 511
 512         return NULL;
 513 }
 514
 515 boolean
 516 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 517                 struct fd_bo *bo,
 518                 unsigned stride,
 519                 struct winsys_handle *whandle)
 520 {
 521         whandle->stride = stride;
 522
 523         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 524                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 525         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 526                 whandle->handle = fd_bo_handle(bo);
 527                 return TRUE;
 528         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 529                 whandle->handle = fd_bo_dmabuf(bo);
 530                 return TRUE;
 531         } else {
 532                 return FALSE;
 533         }
 534 }
 535
 536 struct fd_bo *
 537 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 538                 struct winsys_handle *whandle,
 539                 unsigned *out_stride)
 540 {
 541         struct fd_screen *screen = fd_screen(pscreen);
 542         struct fd_bo *bo;
 543
 544         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 545                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 546         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 547                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 548         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 549                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 550         } else {
 551                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 552                 return NULL;
 553         }
 554
 555         if (!bo) {
 556                 DBG("ref name 0x%08x failed", whandle->handle);
 557                 return NULL;
 558         }
 559
 560         *out_stride = whandle->stride;
 561
 562         return bo;
 563 }
 564
 565 struct pipe_screen *
 566 fd_screen_create(struct fd_device *dev)
 567 {
 568         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 569         struct pipe_screen *pscreen;
 570         uint64_t val;
 571
 572         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 573
 574         if (fd_mesa_debug & FD_DBG_NOBIN)
 575                 fd_binning_enabled = false;
 576
 577         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 578
 579         if (!screen)
 580                 return NULL;
 581
 582         pscreen = &screen->base;
 583
 584         screen->dev = dev;
 585         screen->refcnt = 1;
 586
 587         // maybe this should be in context?
 588         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 589         if (!screen->pipe) {
 590                 DBG("could not create 3d pipe");
 591                 goto fail;
 592         }
 593
 594         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 595                 DBG("could not get GMEM size");
 596                 goto fail;
 597         }
 598         screen->gmemsize_bytes = val;
 599
 600         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 601                 DBG("could not get device-id");
 602                 goto fail;
 603         }
 604         screen->device_id = val;
 605
 606         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 607                 DBG("could not get gpu freq");
 608                 /* this limits what performance related queries are
 609                  * supported but is not fatal
 610                  */
 611                 screen->max_freq = 0;
 612         } else {
 613                 screen->max_freq = val;
 614                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 615                         screen->has_timestamp = true;
 616         }
 617
 618         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 619                 DBG("could not get gpu-id");
 620                 goto fail;
 621         }
 622         screen->gpu_id = val;
 623
 624         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 625                 DBG("could not get chip-id");
 626                 /* older kernels may not have this property: */
 627                 unsigned core  = screen->gpu_id / 100;
 628                 unsigned major = (screen->gpu_id % 100) / 10;
 629                 unsigned minor = screen->gpu_id % 10;
 630                 unsigned patch = 0;  /* assume the worst */
 631                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 632                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 633         }
 634         screen->chip_id = val;
 635
 636         DBG("Pipe Info:");
 637         DBG(" GPU-id:          %d", screen->gpu_id);
 638         DBG(" Chip-id:         0x%08x", screen->chip_id);
 639         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 640
 641         /* explicitly checking for GPU revisions that are known to work.  This
 642          * may be overly conservative for a3xx, where spoofing the gpu_id with
 643          * the blob driver seems to generate identical cmdstream dumps.  But
 644          * on a2xx, there seem to be small differences between the GPU revs
 645          * so it is probably better to actually test first on real hardware
 646          * before enabling:
 647          *
 648          * If you have a different adreno version, feel free to add it to one
 649          * of the cases below and see what happens.  And if it works, please
 650          * send a patch ;-)
 651          */
 652         switch (screen->gpu_id) {
 653         case 220:
 654                 fd2_screen_init(pscreen);
 655                 break;
 656         case 305:
 657         case 307:
 658         case 320:
 659         case 330:
 660                 fd3_screen_init(pscreen);
 661                 break;
 662         case 420:
 663         case 430:
 664                 fd4_screen_init(pscreen);
 665                 break;
 666         default:
 667                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 668                 goto fail;
 669         }
 670
 671         /* NOTE: don't enable reordering on a2xx, since completely untested.
 672          * Also, don't enable if we have too old of a kernel to support
 673          * growable cmdstream buffers, since memory requirement for cmdstream
 674          * buffers would be too much otherwise.
 675          */
 676         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 677                 screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
 678
 679         fd_bc_init(&screen->batch_cache);
 680
 681         pipe_mutex_init(screen->lock);
 682
 683         pscreen->destroy = fd_screen_destroy;
 684         pscreen->get_param = fd_screen_get_param;
 685         pscreen->get_paramf = fd_screen_get_paramf;
 686         pscreen->get_shader_param = fd_screen_get_shader_param;
 687         pscreen->get_compiler_options = fd_get_compiler_options;
 688
 689         fd_resource_screen_init(pscreen);
 690         fd_query_screen_init(pscreen);
 691
 692         pscreen->get_name = fd_screen_get_name;
 693         pscreen->get_vendor = fd_screen_get_vendor;
 694         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 695
 696         pscreen->get_timestamp = fd_screen_get_timestamp;
 697
 698         pscreen->fence_reference = fd_screen_fence_ref;
 699         pscreen->fence_finish = fd_screen_fence_finish;
 700
 701         util_format_s3tc_init();
 702
 703         return pscreen;
 704
 705 fail:
 706         fd_screen_destroy(pscreen);
 707         return NULL;
 708 }