src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  81                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  82                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  83                 DEBUG_NAMED_VALUE_END
  84 };
  85
  86 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  87
  88 int fd_mesa_debug = 0;
  89 bool fd_binning_enabled = true;
  90 static bool glsl120 = false;
  91
  92 static const char *
  93 fd_screen_get_name(struct pipe_screen *pscreen)
  94 {
  95         static char buffer[128];
  96         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  97                         fd_screen(pscreen)->device_id);
  98         return buffer;
  99 }
 100
 101 static const char *
 102 fd_screen_get_vendor(struct pipe_screen *pscreen)
 103 {
 104         return "freedreno";
 105 }
 106
 107 static const char *
 108 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 109 {
 110         return "Qualcomm";
 111 }
 112
 113
 114 static uint64_t
 115 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 116 {
 117         struct fd_screen *screen = fd_screen(pscreen);
 118
 119         if (screen->has_timestamp) {
 120                 uint64_t n;
 121                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 122                 debug_assert(screen->max_freq > 0);
 123                 return n * 1000000000 / screen->max_freq;
 124         } else {
 125                 int64_t cpu_time = os_time_get() * 1000;
 126                 return cpu_time + screen->cpu_gpu_time_delta;
 127         }
 128
 129 }
 130
 131 static void
 132 fd_screen_destroy(struct pipe_screen *pscreen)
 133 {
 134         struct fd_screen *screen = fd_screen(pscreen);
 135
 136         if (screen->pipe)
 137                 fd_pipe_del(screen->pipe);
 138
 139         if (screen->dev)
 140                 fd_device_del(screen->dev);
 141
 142         fd_bc_fini(&screen->batch_cache);
 143
 144         slab_destroy_parent(&screen->transfer_pool);
 145
 146         mtx_destroy(&screen->lock);
 147
 148         ralloc_free(screen->compiler);
 149
 150         free(screen);
 151 }
 152
 153 /*
 154 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 155 tables for things that differ if the delta is not too much..
 156  */
 157 static int
 158 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 159 {
 160         struct fd_screen *screen = fd_screen(pscreen);
 161
 162         /* this is probably not totally correct.. but it's a start: */
 163         switch (param) {
 164         /* Supported features (boolean caps). */
 165         case PIPE_CAP_NPOT_TEXTURES:
 166         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 167         case PIPE_CAP_TWO_SIDED_STENCIL:
 168         case PIPE_CAP_ANISOTROPIC_FILTER:
 169         case PIPE_CAP_POINT_SPRITE:
 170         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 171         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 172         case PIPE_CAP_TEXTURE_SWIZZLE:
 173         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 174         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 175         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 176         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 177         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 178         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 179         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 180         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 182         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 183         case PIPE_CAP_STRING_MARKER:
 184         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 185         case PIPE_CAP_TEXTURE_BARRIER:
 186         case PIPE_CAP_INVALIDATE_BUFFER:
 187                 return 1;
 188
 189         case PIPE_CAP_VERTEXID_NOBASE:
 190                 return is_a3xx(screen) || is_a4xx(screen);
 191
 192         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 193                 return is_a4xx(screen) ? 0 : 1;
 194
 195         case PIPE_CAP_COMPUTE:
 196                 return has_compute(screen);
 197
 198         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 199         case PIPE_CAP_TGSI_TEXCOORD:
 200         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 201         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 202         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 203         case PIPE_CAP_QUERY_MEMORY_INFO:
 204         case PIPE_CAP_PCI_GROUP:
 205         case PIPE_CAP_PCI_BUS:
 206         case PIPE_CAP_PCI_DEVICE:
 207         case PIPE_CAP_PCI_FUNCTION:
 208                 return 0;
 209
 210         case PIPE_CAP_SM3:
 211         case PIPE_CAP_PRIMITIVE_RESTART:
 212         case PIPE_CAP_TGSI_INSTANCEID:
 213         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 214         case PIPE_CAP_INDEP_BLEND_ENABLE:
 215         case PIPE_CAP_INDEP_BLEND_FUNC:
 216         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 217         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 218         case PIPE_CAP_CONDITIONAL_RENDER:
 219         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 220         case PIPE_CAP_FAKE_SW_MSAA:
 221         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 222         case PIPE_CAP_CLIP_HALFZ:
 223                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 224
 225         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 226                 return is_a3xx(screen) || is_a4xx(screen);
 227
 228         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 229                 return is_a5xx(screen);
 230
 231         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 232                 return 0;
 233         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 234                 if (is_a3xx(screen)) return 16;
 235                 if (is_a4xx(screen)) return 32;
 236                 if (is_a5xx(screen)) return 32;
 237                 return 0;
 238         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 239                 /* We could possibly emulate more by pretending 2d/rect textures and
 240                  * splitting high bits of index into 2nd dimension..
 241                  */
 242                 if (is_a3xx(screen)) return 8192;
 243                 if (is_a4xx(screen)) return 16384;
 244                 if (is_a5xx(screen)) return 16384;
 245                 return 0;
 246
 247         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 248         case PIPE_CAP_CUBE_MAP_ARRAY:
 249         case PIPE_CAP_START_INSTANCE:
 250         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 251         case PIPE_CAP_TEXTURE_QUERY_LOD:
 252                 return is_a4xx(screen) || is_a5xx(screen);
 253
 254         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 255                 return 64;
 256
 257         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 258                 if (glsl120)
 259                         return 120;
 260                 return is_ir3(screen) ? 140 : 120;
 261
 262         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 263                 if (is_a5xx(screen))
 264                         return 4;
 265                 return 0;
 266
 267         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 268                 if (is_a4xx(screen) || is_a5xx(screen))
 269                         return 4;
 270                 return 0;
 271
 272         /* Unsupported features. */
 273         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 274         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 275         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 276         case PIPE_CAP_USER_VERTEX_BUFFERS:
 277         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 278         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 279         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 280         case PIPE_CAP_TEXTURE_GATHER_SM5:
 281         case PIPE_CAP_SAMPLE_SHADING:
 282         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 283         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 284         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 285         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 286         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 287         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 288         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 289         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 290         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 291         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 292         case PIPE_CAP_TGSI_TXQS:
 293         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 294         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 295         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 296         case PIPE_CAP_CLEAR_TEXTURE:
 297         case PIPE_CAP_DRAW_PARAMETERS:
 298         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 299         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 300         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 301         case PIPE_CAP_GENERATE_MIPMAP:
 302         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 303         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 304         case PIPE_CAP_CULL_DISTANCE:
 305         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 306         case PIPE_CAP_TGSI_VOTE:
 307         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 308         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 309         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 310         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 311         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 312         case PIPE_CAP_TGSI_FS_FBFETCH:
 313         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 314         case PIPE_CAP_DOUBLES:
 315         case PIPE_CAP_INT64:
 316         case PIPE_CAP_INT64_DIVMOD:
 317         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 318         case PIPE_CAP_TGSI_CLOCK:
 319         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 320         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 321         case PIPE_CAP_TGSI_BALLOT:
 322         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 323         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 324         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 325         case PIPE_CAP_POST_DEPTH_COVERAGE:
 326         case PIPE_CAP_BINDLESS_TEXTURE:
 327         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 328         case PIPE_CAP_QUERY_SO_OVERFLOW:
 329         case PIPE_CAP_MEMOBJ:
 330         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 331         case PIPE_CAP_TILE_RASTER_ORDER:
 332         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 333         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 334                 return 0;
 335
 336         case PIPE_CAP_DRAW_INDIRECT:
 337                 if (is_a4xx(screen) || is_a5xx(screen))
 338                         return 1;
 339                 return 0;
 340
 341         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 342                 if (is_a4xx(screen) || is_a5xx(screen))
 343                         return 1;
 344                 return 0;
 345
 346         case PIPE_CAP_LOAD_CONSTBUF:
 347                 /* name is confusing, but this turns on std430 packing */
 348                 if (is_ir3(screen))
 349                         return 1;
 350                 return 0;
 351
 352         case PIPE_CAP_MAX_VIEWPORTS:
 353                 return 1;
 354
 355         case PIPE_CAP_SHAREABLE_SHADERS:
 356         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 357         /* manage the variants for these ourself, to avoid breaking precompile: */
 358         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 359         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 360                 if (is_ir3(screen))
 361                         return 1;
 362                 return 0;
 363
 364         /* Stream output. */
 365         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 366                 if (is_ir3(screen))
 367                         return PIPE_MAX_SO_BUFFERS;
 368                 return 0;
 369         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 370         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 371                 if (is_ir3(screen))
 372                         return 1;
 373                 return 0;
 374         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 375         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 376                 if (is_ir3(screen))
 377                         return 16 * 4;   /* should only be shader out limit? */
 378                 return 0;
 379
 380         /* Geometry shader output, unsupported. */
 381         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 382         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 383         case PIPE_CAP_MAX_VERTEX_STREAMS:
 384                 return 0;
 385
 386         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 387                 return 2048;
 388
 389         /* Texturing. */
 390         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 391         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 392                 return MAX_MIP_LEVELS;
 393         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 394                 return 11;
 395
 396         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 397                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 398
 399         /* Render targets. */
 400         case PIPE_CAP_MAX_RENDER_TARGETS:
 401                 return screen->max_rts;
 402         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 403                 return is_a3xx(screen) ? 1 : 0;
 404
 405         /* Queries. */
 406         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 407                 return 0;
 408         case PIPE_CAP_OCCLUSION_QUERY:
 409                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 410         case PIPE_CAP_QUERY_TIMESTAMP:
 411         case PIPE_CAP_QUERY_TIME_ELAPSED:
 412                 /* only a4xx, requires new enough kernel so we know max_freq: */
 413                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 414
 415         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 416         case PIPE_CAP_MIN_TEXEL_OFFSET:
 417                 return -8;
 418
 419         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 420         case PIPE_CAP_MAX_TEXEL_OFFSET:
 421                 return 7;
 422
 423         case PIPE_CAP_ENDIANNESS:
 424                 return PIPE_ENDIAN_LITTLE;
 425
 426         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 427                 return 64;
 428
 429         case PIPE_CAP_VENDOR_ID:
 430                 return 0x5143;
 431         case PIPE_CAP_DEVICE_ID:
 432                 return 0xFFFFFFFF;
 433         case PIPE_CAP_ACCELERATED:
 434                 return 1;
 435         case PIPE_CAP_VIDEO_MEMORY:
 436                 DBG("FINISHME: The value returned is incorrect\n");
 437                 return 10;
 438         case PIPE_CAP_UMA:
 439                 return 1;
 440         case PIPE_CAP_NATIVE_FENCE_FD:
 441                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 442         }
 443         debug_printf("unknown param %d\n", param);
 444         return 0;
 445 }
 446
 447 static float
 448 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 449 {
 450         switch (param) {
 451         case PIPE_CAPF_MAX_LINE_WIDTH:
 452         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 453                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 454                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 455                  * uses too small of a render target size, and gets confused when
 456                  * the lines start going offscreen.
 457                  *
 458                  * See: https://code.google.com/p/android/issues/detail?id=206513
 459                  */
 460                 if (fd_mesa_debug & FD_DBG_DEQP)
 461                         return 48.0f;
 462                 return 127.0f;
 463         case PIPE_CAPF_MAX_POINT_WIDTH:
 464         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 465                 return 4092.0f;
 466         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 467                 return 16.0f;
 468         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 469                 return 15.0f;
 470         case PIPE_CAPF_GUARD_BAND_LEFT:
 471         case PIPE_CAPF_GUARD_BAND_TOP:
 472         case PIPE_CAPF_GUARD_BAND_RIGHT:
 473         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 474                 return 0.0f;
 475         }
 476         debug_printf("unknown paramf %d\n", param);
 477         return 0;
 478 }
 479
 480 static int
 481 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 482                 enum pipe_shader_type shader,
 483                 enum pipe_shader_cap param)
 484 {
 485         struct fd_screen *screen = fd_screen(pscreen);
 486
 487         switch(shader)
 488         {
 489         case PIPE_SHADER_FRAGMENT:
 490         case PIPE_SHADER_VERTEX:
 491                 break;
 492         case PIPE_SHADER_COMPUTE:
 493                 if (has_compute(screen))
 494                         break;
 495                 return 0;
 496         case PIPE_SHADER_GEOMETRY:
 497                 /* maye we could emulate.. */
 498                 return 0;
 499         default:
 500                 DBG("unknown shader type %d", shader);
 501                 return 0;
 502         }
 503
 504         /* this is probably not totally correct.. but it's a start: */
 505         switch (param) {
 506         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 507         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 508         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 509         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 510                 return 16384;
 511         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 512                 return 8; /* XXX */
 513         case PIPE_SHADER_CAP_MAX_INPUTS:
 514         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 515                 return 16;
 516         case PIPE_SHADER_CAP_MAX_TEMPS:
 517                 return 64; /* Max native temporaries. */
 518         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 519                 /* NOTE: seems to be limit for a3xx is actually 512 but
 520                  * split between VS and FS.  Use lower limit of 256 to
 521                  * avoid getting into impossible situations:
 522                  */
 523                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 524         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 525                 return is_ir3(screen) ? 16 : 1;
 526         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 527                 return 1;
 528         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 529         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 530                 /* Technically this should be the same as for TEMP/CONST, since
 531                  * everything is just normal registers.  This is just temporary
 532                  * hack until load_input/store_output handle arrays in a similar
 533                  * way as load_var/store_var..
 534                  */
 535                 return 0;
 536         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 537         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 538                 /* a2xx compiler doesn't handle indirect: */
 539                 return is_ir3(screen) ? 1 : 0;
 540         case PIPE_SHADER_CAP_SUBROUTINES:
 541         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 542         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 543         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 544         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 545         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 546                 return 0;
 547         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 548                 return 1;
 549         case PIPE_SHADER_CAP_INTEGERS:
 550                 if (glsl120)
 551                         return 0;
 552                 return is_ir3(screen) ? 1 : 0;
 553         case PIPE_SHADER_CAP_INT64_ATOMICS:
 554                 return 0;
 555         case PIPE_SHADER_CAP_FP16:
 556                 return 0;
 557         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 558         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 559                 return 16;
 560         case PIPE_SHADER_CAP_PREFERRED_IR:
 561                 if (is_ir3(screen))
 562                         return PIPE_SHADER_IR_NIR;
 563                 return PIPE_SHADER_IR_TGSI;
 564         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 565                 if (is_ir3(screen)) {
 566                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 567                 } else {
 568                         return (1 << PIPE_SHADER_IR_TGSI);
 569                 }
 570                 return 0;
 571         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 572                 return 32;
 573         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 574         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 575         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 576         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 577                 return 0;
 578         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 579         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 580                 if (is_a5xx(screen)) {
 581                         /* a5xx (and a4xx for that matter) has one state-block
 582                          * for compute-shader SSBO's and another that is shared
 583                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 584                          * just advertise SSBOs for FS and CS.  We could possibly
 585                          * do what blob does, and partition the space for
 586                          * VS/HS/DS/GS/FS.  The blob advertises:
 587                          *
 588                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 589                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 590                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 591                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 592                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 593                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 594                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 595                          *
 596                          * I think that way we could avoid having to patch shaders
 597                          * for actual SSBO indexes by using a static partitioning.
 598                          *
 599                          * Note same state block is used for images and buffers,
 600                          * but images also need texture state for read access
 601                          * (isam/isam.3d)
 602                          */
 603                         switch(shader)
 604                         {
 605                         case PIPE_SHADER_FRAGMENT:
 606                         case PIPE_SHADER_COMPUTE:
 607                                 return 24;
 608                         default:
 609                                 return 0;
 610                         }
 611                 }
 612                 return 0;
 613         }
 614         debug_printf("unknown shader param %d\n", param);
 615         return 0;
 616 }
 617
 618 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 619  * into per-generation backend?
 620  */
 621 static int
 622 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 623                 enum pipe_compute_cap param, void *ret)
 624 {
 625         struct fd_screen *screen = fd_screen(pscreen);
 626         const char * const ir = "ir3";
 627
 628         if (!has_compute(screen))
 629                 return 0;
 630
 631         switch (param) {
 632         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 633                 if (ret) {
 634                         uint32_t *address_bits = ret;
 635                         address_bits[0] = 32;
 636
 637                         if (is_a5xx(screen))
 638                                 address_bits[0] = 64;
 639                 }
 640                 return 1 * sizeof(uint32_t);
 641
 642         case PIPE_COMPUTE_CAP_IR_TARGET:
 643                 if (ret)
 644                         sprintf(ret, ir);
 645                 return strlen(ir) * sizeof(char);
 646
 647         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 648                 if (ret) {
 649                         uint64_t *grid_dimension = ret;
 650                         grid_dimension[0] = 3;
 651                 }
 652                 return 1 * sizeof(uint64_t);
 653
 654         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 655                 if (ret) {
 656                         uint64_t *grid_size = ret;
 657                         grid_size[0] = 65535;
 658                         grid_size[1] = 65535;
 659                         grid_size[2] = 65535;
 660                 }
 661                 return 3 * sizeof(uint64_t) ;
 662
 663         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 664                 if (ret) {
 665                         uint64_t *block_size = ret;
 666                         block_size[0] = 1024;
 667                         block_size[1] = 1024;
 668                         block_size[2] = 64;
 669                 }
 670                 return 3 * sizeof(uint64_t) ;
 671
 672         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 673                 if (ret) {
 674                         uint64_t *max_threads_per_block = ret;
 675                         *max_threads_per_block = 1024;
 676                 }
 677                 return sizeof(uint64_t);
 678
 679         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 680         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 681                 if (ret) {
 682                         uint64_t *local_size = ret;
 683                         *local_size = 32768;
 684                 }
 685                 return sizeof(uint64_t);
 686         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 687         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 688                 break;
 689         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 690                 if (ret) {
 691                         uint64_t *max = ret;
 692                         *max = 32768;
 693                 }
 694                 return sizeof(uint64_t);
 695         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 696         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 697         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 698         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 699         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 700                 break;
 701         }
 702
 703         return 0;
 704 }
 705
 706 static const void *
 707 fd_get_compiler_options(struct pipe_screen *pscreen,
 708                 enum pipe_shader_ir ir, unsigned shader)
 709 {
 710         struct fd_screen *screen = fd_screen(pscreen);
 711
 712         if (is_ir3(screen))
 713                 return ir3_get_compiler_options(screen->compiler);
 714
 715         return NULL;
 716 }
 717
 718 boolean
 719 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 720                 struct fd_bo *bo,
 721                 unsigned stride,
 722                 struct winsys_handle *whandle)
 723 {
 724         whandle->stride = stride;
 725
 726         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 727                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 728         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 729                 whandle->handle = fd_bo_handle(bo);
 730                 return TRUE;
 731         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 732                 whandle->handle = fd_bo_dmabuf(bo);
 733                 return TRUE;
 734         } else {
 735                 return FALSE;
 736         }
 737 }
 738
 739 struct fd_bo *
 740 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 741                 struct winsys_handle *whandle)
 742 {
 743         struct fd_screen *screen = fd_screen(pscreen);
 744         struct fd_bo *bo;
 745
 746         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 747                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 748         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 749                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 750         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 751                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 752         } else {
 753                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 754                 return NULL;
 755         }
 756
 757         if (!bo) {
 758                 DBG("ref name 0x%08x failed", whandle->handle);
 759                 return NULL;
 760         }
 761
 762         return bo;
 763 }
 764
 765 struct pipe_screen *
 766 fd_screen_create(struct fd_device *dev)
 767 {
 768         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 769         struct pipe_screen *pscreen;
 770         uint64_t val;
 771
 772         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 773
 774         if (fd_mesa_debug & FD_DBG_NOBIN)
 775                 fd_binning_enabled = false;
 776
 777         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 778
 779         if (!screen)
 780                 return NULL;
 781
 782         pscreen = &screen->base;
 783
 784         screen->dev = dev;
 785         screen->refcnt = 1;
 786
 787         // maybe this should be in context?
 788         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 789         if (!screen->pipe) {
 790                 DBG("could not create 3d pipe");
 791                 goto fail;
 792         }
 793
 794         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 795                 DBG("could not get GMEM size");
 796                 goto fail;
 797         }
 798         screen->gmemsize_bytes = val;
 799
 800         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 801                 DBG("could not get device-id");
 802                 goto fail;
 803         }
 804         screen->device_id = val;
 805
 806         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 807                 DBG("could not get gpu freq");
 808                 /* this limits what performance related queries are
 809                  * supported but is not fatal
 810                  */
 811                 screen->max_freq = 0;
 812         } else {
 813                 screen->max_freq = val;
 814                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 815                         screen->has_timestamp = true;
 816         }
 817
 818         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 819                 DBG("could not get gpu-id");
 820                 goto fail;
 821         }
 822         screen->gpu_id = val;
 823
 824         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 825                 DBG("could not get chip-id");
 826                 /* older kernels may not have this property: */
 827                 unsigned core  = screen->gpu_id / 100;
 828                 unsigned major = (screen->gpu_id % 100) / 10;
 829                 unsigned minor = screen->gpu_id % 10;
 830                 unsigned patch = 0;  /* assume the worst */
 831                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 832                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 833         }
 834         screen->chip_id = val;
 835
 836         DBG("Pipe Info:");
 837         DBG(" GPU-id:          %d", screen->gpu_id);
 838         DBG(" Chip-id:         0x%08x", screen->chip_id);
 839         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 840
 841         /* explicitly checking for GPU revisions that are known to work.  This
 842          * may be overly conservative for a3xx, where spoofing the gpu_id with
 843          * the blob driver seems to generate identical cmdstream dumps.  But
 844          * on a2xx, there seem to be small differences between the GPU revs
 845          * so it is probably better to actually test first on real hardware
 846          * before enabling:
 847          *
 848          * If you have a different adreno version, feel free to add it to one
 849          * of the cases below and see what happens.  And if it works, please
 850          * send a patch ;-)
 851          */
 852         switch (screen->gpu_id) {
 853         case 220:
 854                 fd2_screen_init(pscreen);
 855                 break;
 856         case 305:
 857         case 307:
 858         case 320:
 859         case 330:
 860                 fd3_screen_init(pscreen);
 861                 break;
 862         case 420:
 863         case 430:
 864                 fd4_screen_init(pscreen);
 865                 break;
 866         case 530:
 867                 fd5_screen_init(pscreen);
 868                 break;
 869         default:
 870                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 871                 goto fail;
 872         }
 873
 874         if (screen->gpu_id >= 500) {
 875                 screen->gmem_alignw = 64;
 876                 screen->gmem_alignh = 32;
 877                 screen->num_vsc_pipes = 16;
 878         } else {
 879                 screen->gmem_alignw = 32;
 880                 screen->gmem_alignh = 32;
 881                 screen->num_vsc_pipes = 8;
 882         }
 883
 884         /* NOTE: don't enable reordering on a2xx, since completely untested.
 885          * Also, don't enable if we have too old of a kernel to support
 886          * growable cmdstream buffers, since memory requirement for cmdstream
 887          * buffers would be too much otherwise.
 888          */
 889         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 890                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 891
 892         fd_bc_init(&screen->batch_cache);
 893
 894         (void) mtx_init(&screen->lock, mtx_plain);
 895
 896         pscreen->destroy = fd_screen_destroy;
 897         pscreen->get_param = fd_screen_get_param;
 898         pscreen->get_paramf = fd_screen_get_paramf;
 899         pscreen->get_shader_param = fd_screen_get_shader_param;
 900         pscreen->get_compute_param = fd_get_compute_param;
 901         pscreen->get_compiler_options = fd_get_compiler_options;
 902
 903         fd_resource_screen_init(pscreen);
 904         fd_query_screen_init(pscreen);
 905
 906         pscreen->get_name = fd_screen_get_name;
 907         pscreen->get_vendor = fd_screen_get_vendor;
 908         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 909
 910         pscreen->get_timestamp = fd_screen_get_timestamp;
 911
 912         pscreen->fence_reference = fd_fence_ref;
 913         pscreen->fence_finish = fd_fence_finish;
 914         pscreen->fence_get_fd = fd_fence_get_fd;
 915
 916         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 917
 918         return pscreen;
 919
 920 fail:
 921         fd_screen_destroy(pscreen);
 922         return NULL;
 923 }