src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  79                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  80                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  81                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  82                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  83                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  84                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  85                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  86                 DEBUG_NAMED_VALUE_END
  87 };
  88
  89 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  90
  91 int fd_mesa_debug = 0;
  92 bool fd_binning_enabled = true;
  93 static bool glsl120 = false;
  94
  95 static const char *
  96 fd_screen_get_name(struct pipe_screen *pscreen)
  97 {
  98         static char buffer[128];
  99         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 100                         fd_screen(pscreen)->device_id);
 101         return buffer;
 102 }
 103
 104 static const char *
 105 fd_screen_get_vendor(struct pipe_screen *pscreen)
 106 {
 107         return "freedreno";
 108 }
 109
 110 static const char *
 111 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 112 {
 113         return "Qualcomm";
 114 }
 115
 116
 117 static uint64_t
 118 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 119 {
 120         struct fd_screen *screen = fd_screen(pscreen);
 121
 122         if (screen->has_timestamp) {
 123                 uint64_t n;
 124                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 125                 debug_assert(screen->max_freq > 0);
 126                 return n * 1000000000 / screen->max_freq;
 127         } else {
 128                 int64_t cpu_time = os_time_get() * 1000;
 129                 return cpu_time + screen->cpu_gpu_time_delta;
 130         }
 131
 132 }
 133
 134 static void
 135 fd_screen_destroy(struct pipe_screen *pscreen)
 136 {
 137         struct fd_screen *screen = fd_screen(pscreen);
 138
 139         if (screen->pipe)
 140                 fd_pipe_del(screen->pipe);
 141
 142         if (screen->dev)
 143                 fd_device_del(screen->dev);
 144
 145         fd_bc_fini(&screen->batch_cache);
 146
 147         slab_destroy_parent(&screen->transfer_pool);
 148
 149         mtx_destroy(&screen->lock);
 150
 151         ralloc_free(screen->compiler);
 152
 153         free(screen);
 154 }
 155
 156 /*
 157 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 158 tables for things that differ if the delta is not too much..
 159  */
 160 static int
 161 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 162 {
 163         struct fd_screen *screen = fd_screen(pscreen);
 164
 165         /* this is probably not totally correct.. but it's a start: */
 166         switch (param) {
 167         /* Supported features (boolean caps). */
 168         case PIPE_CAP_NPOT_TEXTURES:
 169         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 170         case PIPE_CAP_ANISOTROPIC_FILTER:
 171         case PIPE_CAP_POINT_SPRITE:
 172         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 173         case PIPE_CAP_TEXTURE_SWIZZLE:
 174         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 175         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 176         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 177         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 178         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 179         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 180         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 182         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 183         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 184         case PIPE_CAP_STRING_MARKER:
 185         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 186         case PIPE_CAP_TEXTURE_BARRIER:
 187         case PIPE_CAP_INVALIDATE_BUFFER:
 188                 return 1;
 189
 190         case PIPE_CAP_VERTEXID_NOBASE:
 191                 return is_a3xx(screen) || is_a4xx(screen);
 192
 193         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 194                 return is_a4xx(screen) ? 0 : 1;
 195
 196         case PIPE_CAP_COMPUTE:
 197                 return has_compute(screen);
 198
 199         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 200         case PIPE_CAP_TGSI_TEXCOORD:
 201         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 202         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 203         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 204         case PIPE_CAP_QUERY_MEMORY_INFO:
 205         case PIPE_CAP_PCI_GROUP:
 206         case PIPE_CAP_PCI_BUS:
 207         case PIPE_CAP_PCI_DEVICE:
 208         case PIPE_CAP_PCI_FUNCTION:
 209                 return 0;
 210
 211         case PIPE_CAP_SM3:
 212         case PIPE_CAP_PRIMITIVE_RESTART:
 213         case PIPE_CAP_TGSI_INSTANCEID:
 214         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 215         case PIPE_CAP_INDEP_BLEND_ENABLE:
 216         case PIPE_CAP_INDEP_BLEND_FUNC:
 217         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 218         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 219         case PIPE_CAP_CONDITIONAL_RENDER:
 220         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 221         case PIPE_CAP_FAKE_SW_MSAA:
 222         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 223         case PIPE_CAP_CLIP_HALFZ:
 224                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 225
 226         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 227                 return is_a3xx(screen) || is_a4xx(screen);
 228
 229         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 230                 return is_a5xx(screen);
 231
 232         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 233                 return 0;
 234         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 235                 if (is_a3xx(screen)) return 16;
 236                 if (is_a4xx(screen)) return 32;
 237                 if (is_a5xx(screen)) return 32;
 238                 return 0;
 239         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 240                 /* We could possibly emulate more by pretending 2d/rect textures and
 241                  * splitting high bits of index into 2nd dimension..
 242                  */
 243                 if (is_a3xx(screen)) return 8192;
 244                 if (is_a4xx(screen)) return 16384;
 245                 if (is_a5xx(screen)) return 16384;
 246                 return 0;
 247
 248         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 249         case PIPE_CAP_CUBE_MAP_ARRAY:
 250         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 251         case PIPE_CAP_TEXTURE_QUERY_LOD:
 252                 return is_a4xx(screen) || is_a5xx(screen);
 253
 254         case PIPE_CAP_START_INSTANCE:
 255                 /* Note that a5xx can do this, it just can't (at least with
 256                  * current firmware) do draw_indirect with base_instance.
 257                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 258                  * gl42), hide base_instance on a5xx.  :-/
 259                  */
 260                 return is_a4xx(screen);
 261
 262         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 263                 return 64;
 264
 265         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 266                 if (glsl120)
 267                         return 120;
 268                 return is_ir3(screen) ? 140 : 120;
 269
 270         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 271                 if (is_a5xx(screen))
 272                         return 4;
 273                 return 0;
 274
 275         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 276                 if (is_a4xx(screen) || is_a5xx(screen))
 277                         return 4;
 278                 return 0;
 279
 280         /* Unsupported features. */
 281         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 282         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 283         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 284         case PIPE_CAP_USER_VERTEX_BUFFERS:
 285         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 286         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 287         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 288         case PIPE_CAP_TEXTURE_GATHER_SM5:
 289         case PIPE_CAP_SAMPLE_SHADING:
 290         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 291         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 292         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 293         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 294         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 295         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 296         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 297         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 298         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 299         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 300         case PIPE_CAP_TGSI_TXQS:
 301         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 302         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 303         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 304         case PIPE_CAP_CLEAR_TEXTURE:
 305         case PIPE_CAP_DRAW_PARAMETERS:
 306         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 307         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 308         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 309         case PIPE_CAP_GENERATE_MIPMAP:
 310         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 311         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 312         case PIPE_CAP_CULL_DISTANCE:
 313         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 314         case PIPE_CAP_TGSI_VOTE:
 315         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 316         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 317         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 318         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 319         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 320         case PIPE_CAP_TGSI_FS_FBFETCH:
 321         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 322         case PIPE_CAP_DOUBLES:
 323         case PIPE_CAP_INT64:
 324         case PIPE_CAP_INT64_DIVMOD:
 325         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 326         case PIPE_CAP_TGSI_CLOCK:
 327         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 328         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 329         case PIPE_CAP_TGSI_BALLOT:
 330         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 331         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 332         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 333         case PIPE_CAP_POST_DEPTH_COVERAGE:
 334         case PIPE_CAP_BINDLESS_TEXTURE:
 335         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 336         case PIPE_CAP_QUERY_SO_OVERFLOW:
 337         case PIPE_CAP_MEMOBJ:
 338         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 339         case PIPE_CAP_TILE_RASTER_ORDER:
 340         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 341         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 342                 return 0;
 343
 344         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 345                 return screen->priority_mask;
 346
 347         case PIPE_CAP_DRAW_INDIRECT:
 348                 if (is_a4xx(screen) || is_a5xx(screen))
 349                         return 1;
 350                 return 0;
 351
 352         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 353                 if (is_a4xx(screen) || is_a5xx(screen))
 354                         return 1;
 355                 return 0;
 356
 357         case PIPE_CAP_LOAD_CONSTBUF:
 358                 /* name is confusing, but this turns on std430 packing */
 359                 if (is_ir3(screen))
 360                         return 1;
 361                 return 0;
 362
 363         case PIPE_CAP_MAX_VIEWPORTS:
 364                 return 1;
 365
 366         case PIPE_CAP_SHAREABLE_SHADERS:
 367         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 368         /* manage the variants for these ourself, to avoid breaking precompile: */
 369         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 370         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 371                 if (is_ir3(screen))
 372                         return 1;
 373                 return 0;
 374
 375         /* Stream output. */
 376         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 377                 if (is_ir3(screen))
 378                         return PIPE_MAX_SO_BUFFERS;
 379                 return 0;
 380         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 381         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 382                 if (is_ir3(screen))
 383                         return 1;
 384                 return 0;
 385         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 386         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 387                 if (is_ir3(screen))
 388                         return 16 * 4;   /* should only be shader out limit? */
 389                 return 0;
 390
 391         /* Geometry shader output, unsupported. */
 392         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 393         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 394         case PIPE_CAP_MAX_VERTEX_STREAMS:
 395                 return 0;
 396
 397         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 398                 return 2048;
 399
 400         /* Texturing. */
 401         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 402         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 403                 return MAX_MIP_LEVELS;
 404         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 405                 return 11;
 406
 407         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 408                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 409
 410         /* Render targets. */
 411         case PIPE_CAP_MAX_RENDER_TARGETS:
 412                 return screen->max_rts;
 413         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 414                 return is_a3xx(screen) ? 1 : 0;
 415
 416         /* Queries. */
 417         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 418                 return 0;
 419         case PIPE_CAP_OCCLUSION_QUERY:
 420                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 421         case PIPE_CAP_QUERY_TIMESTAMP:
 422         case PIPE_CAP_QUERY_TIME_ELAPSED:
 423                 /* only a4xx, requires new enough kernel so we know max_freq: */
 424                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 425
 426         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 427         case PIPE_CAP_MIN_TEXEL_OFFSET:
 428                 return -8;
 429
 430         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 431         case PIPE_CAP_MAX_TEXEL_OFFSET:
 432                 return 7;
 433
 434         case PIPE_CAP_ENDIANNESS:
 435                 return PIPE_ENDIAN_LITTLE;
 436
 437         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 438                 return 64;
 439
 440         case PIPE_CAP_VENDOR_ID:
 441                 return 0x5143;
 442         case PIPE_CAP_DEVICE_ID:
 443                 return 0xFFFFFFFF;
 444         case PIPE_CAP_ACCELERATED:
 445                 return 1;
 446         case PIPE_CAP_VIDEO_MEMORY:
 447                 DBG("FINISHME: The value returned is incorrect\n");
 448                 return 10;
 449         case PIPE_CAP_UMA:
 450                 return 1;
 451         case PIPE_CAP_NATIVE_FENCE_FD:
 452                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 453         }
 454         debug_printf("unknown param %d\n", param);
 455         return 0;
 456 }
 457
 458 static float
 459 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 460 {
 461         switch (param) {
 462         case PIPE_CAPF_MAX_LINE_WIDTH:
 463         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 464                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 465                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 466                  * uses too small of a render target size, and gets confused when
 467                  * the lines start going offscreen.
 468                  *
 469                  * See: https://code.google.com/p/android/issues/detail?id=206513
 470                  */
 471                 if (fd_mesa_debug & FD_DBG_DEQP)
 472                         return 48.0f;
 473                 return 127.0f;
 474         case PIPE_CAPF_MAX_POINT_WIDTH:
 475         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 476                 return 4092.0f;
 477         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 478                 return 16.0f;
 479         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 480                 return 15.0f;
 481         case PIPE_CAPF_GUARD_BAND_LEFT:
 482         case PIPE_CAPF_GUARD_BAND_TOP:
 483         case PIPE_CAPF_GUARD_BAND_RIGHT:
 484         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 485                 return 0.0f;
 486         }
 487         debug_printf("unknown paramf %d\n", param);
 488         return 0;
 489 }
 490
 491 static int
 492 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 493                 enum pipe_shader_type shader,
 494                 enum pipe_shader_cap param)
 495 {
 496         struct fd_screen *screen = fd_screen(pscreen);
 497
 498         switch(shader)
 499         {
 500         case PIPE_SHADER_FRAGMENT:
 501         case PIPE_SHADER_VERTEX:
 502                 break;
 503         case PIPE_SHADER_COMPUTE:
 504                 if (has_compute(screen))
 505                         break;
 506                 return 0;
 507         case PIPE_SHADER_GEOMETRY:
 508                 /* maye we could emulate.. */
 509                 return 0;
 510         default:
 511                 DBG("unknown shader type %d", shader);
 512                 return 0;
 513         }
 514
 515         /* this is probably not totally correct.. but it's a start: */
 516         switch (param) {
 517         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 518         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 519         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 520         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 521                 return 16384;
 522         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 523                 return 8; /* XXX */
 524         case PIPE_SHADER_CAP_MAX_INPUTS:
 525         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 526                 return 16;
 527         case PIPE_SHADER_CAP_MAX_TEMPS:
 528                 return 64; /* Max native temporaries. */
 529         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 530                 /* NOTE: seems to be limit for a3xx is actually 512 but
 531                  * split between VS and FS.  Use lower limit of 256 to
 532                  * avoid getting into impossible situations:
 533                  */
 534                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 535         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 536                 return is_ir3(screen) ? 16 : 1;
 537         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 538                 return 1;
 539         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 540         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 541                 /* Technically this should be the same as for TEMP/CONST, since
 542                  * everything is just normal registers.  This is just temporary
 543                  * hack until load_input/store_output handle arrays in a similar
 544                  * way as load_var/store_var..
 545                  */
 546                 return 0;
 547         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 548         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 549                 /* a2xx compiler doesn't handle indirect: */
 550                 return is_ir3(screen) ? 1 : 0;
 551         case PIPE_SHADER_CAP_SUBROUTINES:
 552         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 553         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 554         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 555         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 556         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 557                 return 0;
 558         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 559                 return 1;
 560         case PIPE_SHADER_CAP_INTEGERS:
 561                 if (glsl120)
 562                         return 0;
 563                 return is_ir3(screen) ? 1 : 0;
 564         case PIPE_SHADER_CAP_INT64_ATOMICS:
 565                 return 0;
 566         case PIPE_SHADER_CAP_FP16:
 567                 return 0;
 568         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 569         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 570                 return 16;
 571         case PIPE_SHADER_CAP_PREFERRED_IR:
 572                 if (is_ir3(screen))
 573                         return PIPE_SHADER_IR_NIR;
 574                 return PIPE_SHADER_IR_TGSI;
 575         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 576                 if (is_ir3(screen)) {
 577                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 578                 } else {
 579                         return (1 << PIPE_SHADER_IR_TGSI);
 580                 }
 581                 return 0;
 582         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 583                 return 32;
 584         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 585         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 586         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 587         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 588                 return 0;
 589         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 590         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 591                 if (is_a5xx(screen)) {
 592                         /* a5xx (and a4xx for that matter) has one state-block
 593                          * for compute-shader SSBO's and another that is shared
 594                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 595                          * just advertise SSBOs for FS and CS.  We could possibly
 596                          * do what blob does, and partition the space for
 597                          * VS/HS/DS/GS/FS.  The blob advertises:
 598                          *
 599                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 600                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 601                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 602                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 603                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 604                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 605                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 606                          *
 607                          * I think that way we could avoid having to patch shaders
 608                          * for actual SSBO indexes by using a static partitioning.
 609                          *
 610                          * Note same state block is used for images and buffers,
 611                          * but images also need texture state for read access
 612                          * (isam/isam.3d)
 613                          */
 614                         switch(shader)
 615                         {
 616                         case PIPE_SHADER_FRAGMENT:
 617                         case PIPE_SHADER_COMPUTE:
 618                                 return 24;
 619                         default:
 620                                 return 0;
 621                         }
 622                 }
 623                 return 0;
 624         }
 625         debug_printf("unknown shader param %d\n", param);
 626         return 0;
 627 }
 628
 629 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 630  * into per-generation backend?
 631  */
 632 static int
 633 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 634                 enum pipe_compute_cap param, void *ret)
 635 {
 636         struct fd_screen *screen = fd_screen(pscreen);
 637         const char * const ir = "ir3";
 638
 639         if (!has_compute(screen))
 640                 return 0;
 641
 642         switch (param) {
 643         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 644                 if (ret) {
 645                         uint32_t *address_bits = ret;
 646                         address_bits[0] = 32;
 647
 648                         if (is_a5xx(screen))
 649                                 address_bits[0] = 64;
 650                 }
 651                 return 1 * sizeof(uint32_t);
 652
 653         case PIPE_COMPUTE_CAP_IR_TARGET:
 654                 if (ret)
 655                         sprintf(ret, ir);
 656                 return strlen(ir) * sizeof(char);
 657
 658         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 659                 if (ret) {
 660                         uint64_t *grid_dimension = ret;
 661                         grid_dimension[0] = 3;
 662                 }
 663                 return 1 * sizeof(uint64_t);
 664
 665         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 666                 if (ret) {
 667                         uint64_t *grid_size = ret;
 668                         grid_size[0] = 65535;
 669                         grid_size[1] = 65535;
 670                         grid_size[2] = 65535;
 671                 }
 672                 return 3 * sizeof(uint64_t) ;
 673
 674         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 675                 if (ret) {
 676                         uint64_t *block_size = ret;
 677                         block_size[0] = 1024;
 678                         block_size[1] = 1024;
 679                         block_size[2] = 64;
 680                 }
 681                 return 3 * sizeof(uint64_t) ;
 682
 683         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 684                 if (ret) {
 685                         uint64_t *max_threads_per_block = ret;
 686                         *max_threads_per_block = 1024;
 687                 }
 688                 return sizeof(uint64_t);
 689
 690         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 691         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 692                 if (ret) {
 693                         uint64_t *local_size = ret;
 694                         *local_size = 32768;
 695                 }
 696                 return sizeof(uint64_t);
 697         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 698         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 699                 break;
 700         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 701                 if (ret) {
 702                         uint64_t *max = ret;
 703                         *max = 32768;
 704                 }
 705                 return sizeof(uint64_t);
 706         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 707         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 708         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 709         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 710         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 711                 break;
 712         }
 713
 714         return 0;
 715 }
 716
 717 static const void *
 718 fd_get_compiler_options(struct pipe_screen *pscreen,
 719                 enum pipe_shader_ir ir, unsigned shader)
 720 {
 721         struct fd_screen *screen = fd_screen(pscreen);
 722
 723         if (is_ir3(screen))
 724                 return ir3_get_compiler_options(screen->compiler);
 725
 726         return NULL;
 727 }
 728
 729 boolean
 730 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 731                 struct fd_bo *bo,
 732                 unsigned stride,
 733                 struct winsys_handle *whandle)
 734 {
 735         whandle->stride = stride;
 736
 737         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 738                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 739         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 740                 whandle->handle = fd_bo_handle(bo);
 741                 return TRUE;
 742         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 743                 whandle->handle = fd_bo_dmabuf(bo);
 744                 return TRUE;
 745         } else {
 746                 return FALSE;
 747         }
 748 }
 749
 750 struct fd_bo *
 751 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 752                 struct winsys_handle *whandle)
 753 {
 754         struct fd_screen *screen = fd_screen(pscreen);
 755         struct fd_bo *bo;
 756
 757         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 758                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 759         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 760                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 761         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 762                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 763         } else {
 764                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 765                 return NULL;
 766         }
 767
 768         if (!bo) {
 769                 DBG("ref name 0x%08x failed", whandle->handle);
 770                 return NULL;
 771         }
 772
 773         return bo;
 774 }
 775
 776 struct pipe_screen *
 777 fd_screen_create(struct fd_device *dev)
 778 {
 779         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 780         struct pipe_screen *pscreen;
 781         uint64_t val;
 782
 783         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 784
 785         if (fd_mesa_debug & FD_DBG_NOBIN)
 786                 fd_binning_enabled = false;
 787
 788         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 789
 790         if (!screen)
 791                 return NULL;
 792
 793         pscreen = &screen->base;
 794
 795         screen->dev = dev;
 796         screen->refcnt = 1;
 797
 798         // maybe this should be in context?
 799         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 800         if (!screen->pipe) {
 801                 DBG("could not create 3d pipe");
 802                 goto fail;
 803         }
 804
 805         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 806                 DBG("could not get GMEM size");
 807                 goto fail;
 808         }
 809         screen->gmemsize_bytes = val;
 810
 811         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 812                 DBG("could not get device-id");
 813                 goto fail;
 814         }
 815         screen->device_id = val;
 816
 817         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 818                 DBG("could not get gpu freq");
 819                 /* this limits what performance related queries are
 820                  * supported but is not fatal
 821                  */
 822                 screen->max_freq = 0;
 823         } else {
 824                 screen->max_freq = val;
 825                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 826                         screen->has_timestamp = true;
 827         }
 828
 829         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 830                 DBG("could not get gpu-id");
 831                 goto fail;
 832         }
 833         screen->gpu_id = val;
 834
 835         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 836                 DBG("could not get chip-id");
 837                 /* older kernels may not have this property: */
 838                 unsigned core  = screen->gpu_id / 100;
 839                 unsigned major = (screen->gpu_id % 100) / 10;
 840                 unsigned minor = screen->gpu_id % 10;
 841                 unsigned patch = 0;  /* assume the worst */
 842                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 843                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 844         }
 845         screen->chip_id = val;
 846
 847         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 848                 DBG("could not get # of rings");
 849                 screen->priority_mask = 0;
 850         } else {
 851                 /* # of rings equates to number of unique priority values: */
 852                 screen->priority_mask = (1 << val) - 1;
 853         }
 854
 855         DBG("Pipe Info:");
 856         DBG(" GPU-id:          %d", screen->gpu_id);
 857         DBG(" Chip-id:         0x%08x", screen->chip_id);
 858         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 859
 860         /* explicitly checking for GPU revisions that are known to work.  This
 861          * may be overly conservative for a3xx, where spoofing the gpu_id with
 862          * the blob driver seems to generate identical cmdstream dumps.  But
 863          * on a2xx, there seem to be small differences between the GPU revs
 864          * so it is probably better to actually test first on real hardware
 865          * before enabling:
 866          *
 867          * If you have a different adreno version, feel free to add it to one
 868          * of the cases below and see what happens.  And if it works, please
 869          * send a patch ;-)
 870          */
 871         switch (screen->gpu_id) {
 872         case 220:
 873                 fd2_screen_init(pscreen);
 874                 break;
 875         case 305:
 876         case 307:
 877         case 320:
 878         case 330:
 879                 fd3_screen_init(pscreen);
 880                 break;
 881         case 420:
 882         case 430:
 883                 fd4_screen_init(pscreen);
 884                 break;
 885         case 530:
 886                 fd5_screen_init(pscreen);
 887                 break;
 888         default:
 889                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 890                 goto fail;
 891         }
 892
 893         if (screen->gpu_id >= 500) {
 894                 screen->gmem_alignw = 64;
 895                 screen->gmem_alignh = 32;
 896                 screen->num_vsc_pipes = 16;
 897         } else {
 898                 screen->gmem_alignw = 32;
 899                 screen->gmem_alignh = 32;
 900                 screen->num_vsc_pipes = 8;
 901         }
 902
 903         /* NOTE: don't enable reordering on a2xx, since completely untested.
 904          * Also, don't enable if we have too old of a kernel to support
 905          * growable cmdstream buffers, since memory requirement for cmdstream
 906          * buffers would be too much otherwise.
 907          */
 908         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 909                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 910
 911         fd_bc_init(&screen->batch_cache);
 912
 913         (void) mtx_init(&screen->lock, mtx_plain);
 914
 915         pscreen->destroy = fd_screen_destroy;
 916         pscreen->get_param = fd_screen_get_param;
 917         pscreen->get_paramf = fd_screen_get_paramf;
 918         pscreen->get_shader_param = fd_screen_get_shader_param;
 919         pscreen->get_compute_param = fd_get_compute_param;
 920         pscreen->get_compiler_options = fd_get_compiler_options;
 921
 922         fd_resource_screen_init(pscreen);
 923         fd_query_screen_init(pscreen);
 924
 925         pscreen->get_name = fd_screen_get_name;
 926         pscreen->get_vendor = fd_screen_get_vendor;
 927         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 928
 929         pscreen->get_timestamp = fd_screen_get_timestamp;
 930
 931         pscreen->fence_reference = fd_fence_ref;
 932         pscreen->fence_finish = fd_fence_finish;
 933         pscreen->fence_get_fd = fd_fence_get_fd;
 934
 935         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 936
 937         return pscreen;
 938
 939 fail:
 940         fd_screen_destroy(pscreen);
 941         return NULL;
 942 }