src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56
  57 /* XXX this should go away */
  58 #include "state_tracker/drm_driver.h"
  59
  60 static const struct debug_named_value debug_options[] = {
  61                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  62                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  63                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  64                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  65                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  66                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  67                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  68                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  69                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  70                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  71                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  72                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  73                 DEBUG_NAMED_VALUE_END
  74 };
  75
  76 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  77
  78 int fd_mesa_debug = 0;
  79 bool fd_binning_enabled = true;
  80 static bool glsl120 = false;
  81
  82 static const char *
  83 fd_screen_get_name(struct pipe_screen *pscreen)
  84 {
  85         static char buffer[128];
  86         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  87                         fd_screen(pscreen)->device_id);
  88         return buffer;
  89 }
  90
  91 static const char *
  92 fd_screen_get_vendor(struct pipe_screen *pscreen)
  93 {
  94         return "freedreno";
  95 }
  96
  97 static const char *
  98 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
  99 {
 100         return "Qualcomm";
 101 }
 102
 103
 104 static uint64_t
 105 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 106 {
 107         int64_t cpu_time = os_time_get() * 1000;
 108         return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
 109 }
 110
 111 static void
 112 fd_screen_destroy(struct pipe_screen *pscreen)
 113 {
 114         struct fd_screen *screen = fd_screen(pscreen);
 115
 116         if (screen->pipe)
 117                 fd_pipe_del(screen->pipe);
 118
 119         if (screen->dev)
 120                 fd_device_del(screen->dev);
 121
 122         free(screen);
 123 }
 124
 125 /*
 126 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 127 tables for things that differ if the delta is not too much..
 128  */
 129 static int
 130 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 131 {
 132         struct fd_screen *screen = fd_screen(pscreen);
 133
 134         /* this is probably not totally correct.. but it's a start: */
 135         switch (param) {
 136         /* Supported features (boolean caps). */
 137         case PIPE_CAP_NPOT_TEXTURES:
 138         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 139         case PIPE_CAP_TWO_SIDED_STENCIL:
 140         case PIPE_CAP_ANISOTROPIC_FILTER:
 141         case PIPE_CAP_POINT_SPRITE:
 142         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 143         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 144         case PIPE_CAP_TEXTURE_SWIZZLE:
 145         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 146         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 147         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 148         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 149         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 150         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 151         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 152         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 153         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 154         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 155         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156         case PIPE_CAP_VERTEXID_NOBASE:
 157                 return 1;
 158
 159         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 160         case PIPE_CAP_TGSI_TEXCOORD:
 161         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 162         case PIPE_CAP_CONDITIONAL_RENDER:
 163         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 164         case PIPE_CAP_TEXTURE_BARRIER:
 165         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 166         case PIPE_CAP_START_INSTANCE:
 167         case PIPE_CAP_COMPUTE:
 168                 return 0;
 169
 170         case PIPE_CAP_SM3:
 171         case PIPE_CAP_PRIMITIVE_RESTART:
 172         case PIPE_CAP_TGSI_INSTANCEID:
 173         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 174         case PIPE_CAP_INDEP_BLEND_ENABLE:
 175         case PIPE_CAP_INDEP_BLEND_FUNC:
 176         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 177         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 178                 return is_a3xx(screen) || is_a4xx(screen);
 179
 180         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 181                 /* ignoring first/last_element.. but I guess that should be
 182                  * easy to add..
 183                  */
 184                 return 0;
 185         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 186                 /* I think 32k on a4xx.. and we could possibly emulate more
 187                  * by pretending 2d/rect textures and splitting high bits
 188                  * of index into 2nd dimension..
 189                  */
 190                 return 16383;
 191
 192         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 193         case PIPE_CAP_CLIP_HALFZ:
 194         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 195                 return is_a3xx(screen);
 196
 197         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 198         case PIPE_CAP_CUBE_MAP_ARRAY:
 199                 return is_a4xx(screen);
 200
 201         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 202                 return 256;
 203
 204         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 205                 if (glsl120)
 206                         return 120;
 207                 return is_ir3(screen) ? 130 : 120;
 208
 209         /* Unsupported features. */
 210         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 211         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 212         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 213         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 214         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 215         case PIPE_CAP_USER_VERTEX_BUFFERS:
 216         case PIPE_CAP_USER_INDEX_BUFFERS:
 217         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 218         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 219         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 220         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 221         case PIPE_CAP_TEXTURE_GATHER_SM5:
 222         case PIPE_CAP_FAKE_SW_MSAA:
 223         case PIPE_CAP_TEXTURE_QUERY_LOD:
 224         case PIPE_CAP_SAMPLE_SHADING:
 225         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 226         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 227         case PIPE_CAP_DRAW_INDIRECT:
 228         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 229         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 230         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 231         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 232         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 233         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 234         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 235         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 236         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 237         case PIPE_CAP_TGSI_TXQS:
 238                 return 0;
 239
 240         case PIPE_CAP_MAX_VIEWPORTS:
 241                 return 1;
 242
 243         /* Stream output. */
 244         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 245                 if (is_ir3(screen))
 246                         return PIPE_MAX_SO_BUFFERS;
 247                 return 0;
 248         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 249                 if (is_ir3(screen))
 250                         return 1;
 251                 return 0;
 252         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 253         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 254                 if (is_ir3(screen))
 255                         return 16 * 4;   /* should only be shader out limit? */
 256                 return 0;
 257
 258         /* Geometry shader output, unsupported. */
 259         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 260         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 261         case PIPE_CAP_MAX_VERTEX_STREAMS:
 262                 return 0;
 263
 264         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 265                 return 2048;
 266
 267         /* Texturing. */
 268         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 269         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 270                 return MAX_MIP_LEVELS;
 271         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 272                 return 11;
 273
 274         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 275                 return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
 276
 277         /* Render targets. */
 278         case PIPE_CAP_MAX_RENDER_TARGETS:
 279                 return screen->max_rts;
 280         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 281                 return is_a3xx(screen) ? 1 : 0;
 282
 283         /* Queries. */
 284         case PIPE_CAP_QUERY_TIME_ELAPSED:
 285         case PIPE_CAP_QUERY_TIMESTAMP:
 286                 return 0;
 287         case PIPE_CAP_OCCLUSION_QUERY:
 288                 return is_a3xx(screen) || is_a4xx(screen);
 289
 290         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 291         case PIPE_CAP_MIN_TEXEL_OFFSET:
 292                 return -8;
 293
 294         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 295         case PIPE_CAP_MAX_TEXEL_OFFSET:
 296                 return 7;
 297
 298         case PIPE_CAP_ENDIANNESS:
 299                 return PIPE_ENDIAN_LITTLE;
 300
 301         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 302                 return 64;
 303
 304         case PIPE_CAP_VENDOR_ID:
 305                 return 0x5143;
 306         case PIPE_CAP_DEVICE_ID:
 307                 return 0xFFFFFFFF;
 308         case PIPE_CAP_ACCELERATED:
 309                 return 1;
 310         case PIPE_CAP_VIDEO_MEMORY:
 311                 DBG("FINISHME: The value returned is incorrect\n");
 312                 return 10;
 313         case PIPE_CAP_UMA:
 314                 return 1;
 315         }
 316         debug_printf("unknown param %d\n", param);
 317         return 0;
 318 }
 319
 320 static float
 321 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 322 {
 323         switch (param) {
 324         case PIPE_CAPF_MAX_LINE_WIDTH:
 325         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 326         case PIPE_CAPF_MAX_POINT_WIDTH:
 327         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 328                 return 4092.0f;
 329         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 330                 return 16.0f;
 331         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 332                 return 15.0f;
 333         case PIPE_CAPF_GUARD_BAND_LEFT:
 334         case PIPE_CAPF_GUARD_BAND_TOP:
 335         case PIPE_CAPF_GUARD_BAND_RIGHT:
 336         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 337                 return 0.0f;
 338         }
 339         debug_printf("unknown paramf %d\n", param);
 340         return 0;
 341 }
 342
 343 static int
 344 fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 345                 enum pipe_shader_cap param)
 346 {
 347         struct fd_screen *screen = fd_screen(pscreen);
 348
 349         switch(shader)
 350         {
 351         case PIPE_SHADER_FRAGMENT:
 352         case PIPE_SHADER_VERTEX:
 353                 break;
 354         case PIPE_SHADER_COMPUTE:
 355         case PIPE_SHADER_GEOMETRY:
 356                 /* maye we could emulate.. */
 357                 return 0;
 358         default:
 359                 DBG("unknown shader type %d", shader);
 360                 return 0;
 361         }
 362
 363         /* this is probably not totally correct.. but it's a start: */
 364         switch (param) {
 365         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 366         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 367         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 368         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 369                 return 16384;
 370         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 371                 return 8; /* XXX */
 372         case PIPE_SHADER_CAP_MAX_INPUTS:
 373         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 374                 return 16;
 375         case PIPE_SHADER_CAP_MAX_TEMPS:
 376                 return 64; /* Max native temporaries. */
 377         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 378                 /* NOTE: seems to be limit for a3xx is actually 512 but
 379                  * split between VS and FS.  Use lower limit of 256 to
 380                  * avoid getting into impossible situations:
 381                  */
 382                 return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 383         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 384                 return is_ir3(screen) ? 16 : 1;
 385         case PIPE_SHADER_CAP_MAX_PREDS:
 386                 return 0; /* nothing uses this */
 387         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 388                 return 1;
 389         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 390         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 391         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 392         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 393                 return 1;
 394         case PIPE_SHADER_CAP_SUBROUTINES:
 395         case PIPE_SHADER_CAP_DOUBLES:
 396         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 397         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 398         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 399         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 400                 return 0;
 401         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 402                 return 1;
 403         case PIPE_SHADER_CAP_INTEGERS:
 404                 if (glsl120)
 405                         return 0;
 406                 return is_ir3(screen) ? 1 : 0;
 407         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 408         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 409                 return 16;
 410         case PIPE_SHADER_CAP_PREFERRED_IR:
 411                 return PIPE_SHADER_IR_TGSI;
 412         }
 413         debug_printf("unknown shader param %d\n", param);
 414         return 0;
 415 }
 416
 417 boolean
 418 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 419                 struct fd_bo *bo,
 420                 unsigned stride,
 421                 struct winsys_handle *whandle)
 422 {
 423         whandle->stride = stride;
 424
 425         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 426                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 427         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 428                 whandle->handle = fd_bo_handle(bo);
 429                 return TRUE;
 430         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 431                 whandle->handle = fd_bo_dmabuf(bo);
 432                 return TRUE;
 433         } else {
 434                 return FALSE;
 435         }
 436 }
 437
 438 struct fd_bo *
 439 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 440                 struct winsys_handle *whandle,
 441                 unsigned *out_stride)
 442 {
 443         struct fd_screen *screen = fd_screen(pscreen);
 444         struct fd_bo *bo;
 445
 446         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 447                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 448         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 449                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 450         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 451                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 452         } else {
 453                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 454                 return NULL;
 455         }
 456
 457         if (!bo) {
 458                 DBG("ref name 0x%08x failed", whandle->handle);
 459                 return NULL;
 460         }
 461
 462         *out_stride = whandle->stride;
 463
 464         return bo;
 465 }
 466
 467 struct pipe_screen *
 468 fd_screen_create(struct fd_device *dev)
 469 {
 470         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 471         struct pipe_screen *pscreen;
 472         uint64_t val;
 473
 474         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 475
 476         if (fd_mesa_debug & FD_DBG_NOBIN)
 477                 fd_binning_enabled = false;
 478
 479         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 480
 481         if (!screen)
 482                 return NULL;
 483
 484         pscreen = &screen->base;
 485
 486         screen->dev = dev;
 487         screen->refcnt = 1;
 488
 489         // maybe this should be in context?
 490         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 491         if (!screen->pipe) {
 492                 DBG("could not create 3d pipe");
 493                 goto fail;
 494         }
 495
 496         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 497                 DBG("could not get GMEM size");
 498                 goto fail;
 499         }
 500         screen->gmemsize_bytes = val;
 501
 502         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 503                 DBG("could not get device-id");
 504                 goto fail;
 505         }
 506         screen->device_id = val;
 507
 508         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 509                 DBG("could not get gpu-id");
 510                 goto fail;
 511         }
 512         screen->gpu_id = val;
 513
 514         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 515                 DBG("could not get chip-id");
 516                 /* older kernels may not have this property: */
 517                 unsigned core  = screen->gpu_id / 100;
 518                 unsigned major = (screen->gpu_id % 100) / 10;
 519                 unsigned minor = screen->gpu_id % 10;
 520                 unsigned patch = 0;  /* assume the worst */
 521                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 522                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 523         }
 524         screen->chip_id = val;
 525
 526         DBG("Pipe Info:");
 527         DBG(" GPU-id:          %d", screen->gpu_id);
 528         DBG(" Chip-id:         0x%08x", screen->chip_id);
 529         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 530
 531         /* explicitly checking for GPU revisions that are known to work.  This
 532          * may be overly conservative for a3xx, where spoofing the gpu_id with
 533          * the blob driver seems to generate identical cmdstream dumps.  But
 534          * on a2xx, there seem to be small differences between the GPU revs
 535          * so it is probably better to actually test first on real hardware
 536          * before enabling:
 537          *
 538          * If you have a different adreno version, feel free to add it to one
 539          * of the cases below and see what happens.  And if it works, please
 540          * send a patch ;-)
 541          */
 542         switch (screen->gpu_id) {
 543         case 220:
 544                 fd2_screen_init(pscreen);
 545                 break;
 546         case 307:
 547         case 320:
 548         case 330:
 549                 fd3_screen_init(pscreen);
 550                 break;
 551         case 420:
 552                 fd4_screen_init(pscreen);
 553                 break;
 554         default:
 555                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 556                 goto fail;
 557         }
 558
 559         pscreen->destroy = fd_screen_destroy;
 560         pscreen->get_param = fd_screen_get_param;
 561         pscreen->get_paramf = fd_screen_get_paramf;
 562         pscreen->get_shader_param = fd_screen_get_shader_param;
 563
 564         fd_resource_screen_init(pscreen);
 565         fd_query_screen_init(pscreen);
 566
 567         pscreen->get_name = fd_screen_get_name;
 568         pscreen->get_vendor = fd_screen_get_vendor;
 569         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 570
 571         pscreen->get_timestamp = fd_screen_get_timestamp;
 572
 573         pscreen->fence_reference = fd_screen_fence_ref;
 574         pscreen->fence_finish = fd_screen_fence_finish;
 575
 576         util_format_s3tc_init();
 577
 578         return pscreen;
 579
 580 fail:
 581         fd_screen_destroy(pscreen);
 582         return NULL;
 583 }