src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "os/os_time.h"
  42
  43 #include <stdio.h>
  44 #include <errno.h>
  45 #include <stdlib.h>
  46
  47 #include "freedreno_screen.h"
  48 #include "freedreno_resource.h"
  49 #include "freedreno_fence.h"
  50 #include "freedreno_query.h"
  51 #include "freedreno_util.h"
  52
  53 #include "a2xx/fd2_screen.h"
  54 #include "a3xx/fd3_screen.h"
  55 #include "a4xx/fd4_screen.h"
  56 #include "a5xx/fd5_screen.h"
  57
  58 #include "ir3/ir3_nir.h"
  59
  60 /* XXX this should go away */
  61 #include "state_tracker/drm_driver.h"
  62
  63 static const struct debug_named_value debug_options[] = {
  64                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  65                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  66                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  67                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  68                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  69                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  70                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  71                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  72                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  73                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  74                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  75                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  76                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  77                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  78                 {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
  79                 {"reorder",   FD_DBG_REORDER,"Enable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  82                 DEBUG_NAMED_VALUE_END
  83 };
  84
  85 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  86
  87 int fd_mesa_debug = 0;
  88 bool fd_binning_enabled = true;
  89 static bool glsl120 = false;
  90
  91 static const char *
  92 fd_screen_get_name(struct pipe_screen *pscreen)
  93 {
  94         static char buffer[128];
  95         util_snprintf(buffer, sizeof(buffer), "FD%03d",
  96                         fd_screen(pscreen)->device_id);
  97         return buffer;
  98 }
  99
 100 static const char *
 101 fd_screen_get_vendor(struct pipe_screen *pscreen)
 102 {
 103         return "freedreno";
 104 }
 105
 106 static const char *
 107 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 108 {
 109         return "Qualcomm";
 110 }
 111
 112
 113 static uint64_t
 114 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 115 {
 116         struct fd_screen *screen = fd_screen(pscreen);
 117
 118         if (screen->has_timestamp) {
 119                 uint64_t n;
 120                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 121                 debug_assert(screen->max_freq > 0);
 122                 return n * 1000000000 / screen->max_freq;
 123         } else {
 124                 int64_t cpu_time = os_time_get() * 1000;
 125                 return cpu_time + screen->cpu_gpu_time_delta;
 126         }
 127
 128 }
 129
 130 static void
 131 fd_screen_destroy(struct pipe_screen *pscreen)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         if (screen->pipe)
 136                 fd_pipe_del(screen->pipe);
 137
 138         if (screen->dev)
 139                 fd_device_del(screen->dev);
 140
 141         fd_bc_fini(&screen->batch_cache);
 142
 143         slab_destroy_parent(&screen->transfer_pool);
 144
 145         mtx_destroy(&screen->lock);
 146
 147         ralloc_free(screen->compiler);
 148
 149         free(screen);
 150 }
 151
 152 /*
 153 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 154 tables for things that differ if the delta is not too much..
 155  */
 156 static int
 157 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 158 {
 159         struct fd_screen *screen = fd_screen(pscreen);
 160
 161         /* this is probably not totally correct.. but it's a start: */
 162         switch (param) {
 163         /* Supported features (boolean caps). */
 164         case PIPE_CAP_NPOT_TEXTURES:
 165         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 166         case PIPE_CAP_TWO_SIDED_STENCIL:
 167         case PIPE_CAP_ANISOTROPIC_FILTER:
 168         case PIPE_CAP_POINT_SPRITE:
 169         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 170         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 171         case PIPE_CAP_TEXTURE_SWIZZLE:
 172         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 174         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 175         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 176         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 177         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 178         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 179         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 180         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 181         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 182         case PIPE_CAP_STRING_MARKER:
 183         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 184                 return 1;
 185
 186         case PIPE_CAP_VERTEXID_NOBASE:
 187                 return is_a3xx(screen) || is_a4xx(screen);
 188
 189         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 190                 return is_a4xx(screen) ? 0 : 1;
 191
 192         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 193         case PIPE_CAP_TGSI_TEXCOORD:
 194         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 195         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 196         case PIPE_CAP_TEXTURE_BARRIER:
 197         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 198         case PIPE_CAP_COMPUTE:
 199         case PIPE_CAP_QUERY_MEMORY_INFO:
 200         case PIPE_CAP_PCI_GROUP:
 201         case PIPE_CAP_PCI_BUS:
 202         case PIPE_CAP_PCI_DEVICE:
 203         case PIPE_CAP_PCI_FUNCTION:
 204                 return 0;
 205
 206         case PIPE_CAP_SM3:
 207         case PIPE_CAP_PRIMITIVE_RESTART:
 208         case PIPE_CAP_TGSI_INSTANCEID:
 209         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 210         case PIPE_CAP_INDEP_BLEND_ENABLE:
 211         case PIPE_CAP_INDEP_BLEND_FUNC:
 212         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 213         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 214         case PIPE_CAP_CONDITIONAL_RENDER:
 215         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 216         case PIPE_CAP_FAKE_SW_MSAA:
 217         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 218         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 219         case PIPE_CAP_CLIP_HALFZ:
 220                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 221
 222         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 223                 return 0;
 224         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 225                 if (is_a3xx(screen)) return 16;
 226                 if (is_a4xx(screen)) return 32;
 227                 if (is_a5xx(screen)) return 32;
 228                 return 0;
 229         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 230                 /* We could possibly emulate more by pretending 2d/rect textures and
 231                  * splitting high bits of index into 2nd dimension..
 232                  */
 233                 if (is_a3xx(screen)) return 8192;
 234                 if (is_a4xx(screen)) return 16384;
 235                 if (is_a5xx(screen)) return 16384;
 236                 return 0;
 237
 238         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 239         case PIPE_CAP_CUBE_MAP_ARRAY:
 240         case PIPE_CAP_START_INSTANCE:
 241         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 242         case PIPE_CAP_TEXTURE_QUERY_LOD:
 243                 return is_a4xx(screen) || is_a5xx(screen);
 244
 245         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 246                 return 64;
 247
 248         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 249                 if (glsl120)
 250                         return 120;
 251                 return is_ir3(screen) ? 140 : 120;
 252
 253         /* Unsupported features. */
 254         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 255         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 256         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 257         case PIPE_CAP_USER_VERTEX_BUFFERS:
 258         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 259         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 260         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 261         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 262         case PIPE_CAP_TEXTURE_GATHER_SM5:
 263         case PIPE_CAP_SAMPLE_SHADING:
 264         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 265         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 266         case PIPE_CAP_DRAW_INDIRECT:
 267         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 268         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 269         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 270         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 271         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 272         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 273         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 274         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 275         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 276         case PIPE_CAP_TGSI_TXQS:
 277         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 278         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 279         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 280         case PIPE_CAP_CLEAR_TEXTURE:
 281         case PIPE_CAP_DRAW_PARAMETERS:
 282         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 283         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 284         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 285         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 286         case PIPE_CAP_INVALIDATE_BUFFER:
 287         case PIPE_CAP_GENERATE_MIPMAP:
 288         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 289         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 290         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 291         case PIPE_CAP_CULL_DISTANCE:
 292         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 293         case PIPE_CAP_TGSI_VOTE:
 294         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 295         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 296         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 297         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 298         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 299         case PIPE_CAP_TGSI_FS_FBFETCH:
 300         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 301         case PIPE_CAP_DOUBLES:
 302         case PIPE_CAP_INT64:
 303         case PIPE_CAP_INT64_DIVMOD:
 304         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 305         case PIPE_CAP_TGSI_CLOCK:
 306         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 307                 return 0;
 308
 309         case PIPE_CAP_MAX_VIEWPORTS:
 310                 return 1;
 311
 312         case PIPE_CAP_SHAREABLE_SHADERS:
 313         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 314         /* manage the variants for these ourself, to avoid breaking precompile: */
 315         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 316         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 317                 if (is_ir3(screen))
 318                         return 1;
 319                 return 0;
 320
 321         /* Stream output. */
 322         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 323                 if (is_ir3(screen))
 324                         return PIPE_MAX_SO_BUFFERS;
 325                 return 0;
 326         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 327         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 328                 if (is_ir3(screen))
 329                         return 1;
 330                 return 0;
 331         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 332         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 333                 if (is_ir3(screen))
 334                         return 16 * 4;   /* should only be shader out limit? */
 335                 return 0;
 336
 337         /* Geometry shader output, unsupported. */
 338         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 339         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 340         case PIPE_CAP_MAX_VERTEX_STREAMS:
 341                 return 0;
 342
 343         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 344                 return 2048;
 345
 346         /* Texturing. */
 347         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 348         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 349                 return MAX_MIP_LEVELS;
 350         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 351                 return 11;
 352
 353         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 354                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 355
 356         /* Render targets. */
 357         case PIPE_CAP_MAX_RENDER_TARGETS:
 358                 return screen->max_rts;
 359         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 360                 return is_a3xx(screen) ? 1 : 0;
 361
 362         /* Queries. */
 363         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 364                 return 0;
 365         case PIPE_CAP_OCCLUSION_QUERY:
 366                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 367         case PIPE_CAP_QUERY_TIMESTAMP:
 368         case PIPE_CAP_QUERY_TIME_ELAPSED:
 369                 /* only a4xx, requires new enough kernel so we know max_freq: */
 370                 return (screen->max_freq > 0) && is_a4xx(screen);
 371
 372         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 373         case PIPE_CAP_MIN_TEXEL_OFFSET:
 374                 return -8;
 375
 376         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 377         case PIPE_CAP_MAX_TEXEL_OFFSET:
 378                 return 7;
 379
 380         case PIPE_CAP_ENDIANNESS:
 381                 return PIPE_ENDIAN_LITTLE;
 382
 383         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 384                 return 64;
 385
 386         case PIPE_CAP_VENDOR_ID:
 387                 return 0x5143;
 388         case PIPE_CAP_DEVICE_ID:
 389                 return 0xFFFFFFFF;
 390         case PIPE_CAP_ACCELERATED:
 391                 return 1;
 392         case PIPE_CAP_VIDEO_MEMORY:
 393                 DBG("FINISHME: The value returned is incorrect\n");
 394                 return 10;
 395         case PIPE_CAP_UMA:
 396                 return 1;
 397         case PIPE_CAP_NATIVE_FENCE_FD:
 398                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 399         }
 400         debug_printf("unknown param %d\n", param);
 401         return 0;
 402 }
 403
 404 static float
 405 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 406 {
 407         switch (param) {
 408         case PIPE_CAPF_MAX_LINE_WIDTH:
 409         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 410                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 411                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 412                  * uses too small of a render target size, and gets confused when
 413                  * the lines start going offscreen.
 414                  *
 415                  * See: https://code.google.com/p/android/issues/detail?id=206513
 416                  */
 417                 if (fd_mesa_debug & FD_DBG_DEQP)
 418                         return 48.0f;
 419                 return 127.0f;
 420         case PIPE_CAPF_MAX_POINT_WIDTH:
 421         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 422                 return 4092.0f;
 423         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 424                 return 16.0f;
 425         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 426                 return 15.0f;
 427         case PIPE_CAPF_GUARD_BAND_LEFT:
 428         case PIPE_CAPF_GUARD_BAND_TOP:
 429         case PIPE_CAPF_GUARD_BAND_RIGHT:
 430         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 431                 return 0.0f;
 432         }
 433         debug_printf("unknown paramf %d\n", param);
 434         return 0;
 435 }
 436
 437 static int
 438 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 439                                                    enum pipe_shader_type shader,
 440                 enum pipe_shader_cap param)
 441 {
 442         struct fd_screen *screen = fd_screen(pscreen);
 443
 444         switch(shader)
 445         {
 446         case PIPE_SHADER_FRAGMENT:
 447         case PIPE_SHADER_VERTEX:
 448                 break;
 449         case PIPE_SHADER_COMPUTE:
 450         case PIPE_SHADER_GEOMETRY:
 451                 /* maye we could emulate.. */
 452                 return 0;
 453         default:
 454                 DBG("unknown shader type %d", shader);
 455                 return 0;
 456         }
 457
 458         /* this is probably not totally correct.. but it's a start: */
 459         switch (param) {
 460         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 461         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 462         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 463         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 464                 return 16384;
 465         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 466                 return 8; /* XXX */
 467         case PIPE_SHADER_CAP_MAX_INPUTS:
 468         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 469                 return 16;
 470         case PIPE_SHADER_CAP_MAX_TEMPS:
 471                 return 64; /* Max native temporaries. */
 472         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 473                 /* NOTE: seems to be limit for a3xx is actually 512 but
 474                  * split between VS and FS.  Use lower limit of 256 to
 475                  * avoid getting into impossible situations:
 476                  */
 477                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 478         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 479                 return is_ir3(screen) ? 16 : 1;
 480         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 481                 return 1;
 482         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 483         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 484                 /* Technically this should be the same as for TEMP/CONST, since
 485                  * everything is just normal registers.  This is just temporary
 486                  * hack until load_input/store_output handle arrays in a similar
 487                  * way as load_var/store_var..
 488                  */
 489                 return 0;
 490         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 491         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 492                 /* a2xx compiler doesn't handle indirect: */
 493                 return is_ir3(screen) ? 1 : 0;
 494         case PIPE_SHADER_CAP_SUBROUTINES:
 495         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 496         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 497         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 498         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 499                 return 0;
 500         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 501                 return 1;
 502         case PIPE_SHADER_CAP_INTEGERS:
 503                 if (glsl120)
 504                         return 0;
 505                 return is_ir3(screen) ? 1 : 0;
 506         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 507         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 508                 return 16;
 509         case PIPE_SHADER_CAP_PREFERRED_IR:
 510                 if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
 511                         return PIPE_SHADER_IR_NIR;
 512                 return PIPE_SHADER_IR_TGSI;
 513         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 514                 return 0;
 515         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 516                 return 32;
 517         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 518         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 519         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 520                 return 0;
 521         }
 522         debug_printf("unknown shader param %d\n", param);
 523         return 0;
 524 }
 525
 526 static const void *
 527 fd_get_compiler_options(struct pipe_screen *pscreen,
 528                 enum pipe_shader_ir ir, unsigned shader)
 529 {
 530         struct fd_screen *screen = fd_screen(pscreen);
 531
 532         if (is_ir3(screen))
 533                 return ir3_get_compiler_options();
 534
 535         return NULL;
 536 }
 537
 538 boolean
 539 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 540                 struct fd_bo *bo,
 541                 unsigned stride,
 542                 struct winsys_handle *whandle)
 543 {
 544         whandle->stride = stride;
 545
 546         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 547                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 548         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 549                 whandle->handle = fd_bo_handle(bo);
 550                 return TRUE;
 551         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 552                 whandle->handle = fd_bo_dmabuf(bo);
 553                 return TRUE;
 554         } else {
 555                 return FALSE;
 556         }
 557 }
 558
 559 struct fd_bo *
 560 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 561                 struct winsys_handle *whandle)
 562 {
 563         struct fd_screen *screen = fd_screen(pscreen);
 564         struct fd_bo *bo;
 565
 566         if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 567                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 568         } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 569                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 570         } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 571                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 572         } else {
 573                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 574                 return NULL;
 575         }
 576
 577         if (!bo) {
 578                 DBG("ref name 0x%08x failed", whandle->handle);
 579                 return NULL;
 580         }
 581
 582         return bo;
 583 }
 584
 585 struct pipe_screen *
 586 fd_screen_create(struct fd_device *dev)
 587 {
 588         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 589         struct pipe_screen *pscreen;
 590         uint64_t val;
 591
 592         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 593
 594         if (fd_mesa_debug & FD_DBG_NOBIN)
 595                 fd_binning_enabled = false;
 596
 597         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 598
 599         if (!screen)
 600                 return NULL;
 601
 602         pscreen = &screen->base;
 603
 604         screen->dev = dev;
 605         screen->refcnt = 1;
 606
 607         // maybe this should be in context?
 608         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 609         if (!screen->pipe) {
 610                 DBG("could not create 3d pipe");
 611                 goto fail;
 612         }
 613
 614         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 615                 DBG("could not get GMEM size");
 616                 goto fail;
 617         }
 618         screen->gmemsize_bytes = val;
 619
 620         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 621                 DBG("could not get device-id");
 622                 goto fail;
 623         }
 624         screen->device_id = val;
 625
 626         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 627                 DBG("could not get gpu freq");
 628                 /* this limits what performance related queries are
 629                  * supported but is not fatal
 630                  */
 631                 screen->max_freq = 0;
 632         } else {
 633                 screen->max_freq = val;
 634                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 635                         screen->has_timestamp = true;
 636         }
 637
 638         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 639                 DBG("could not get gpu-id");
 640                 goto fail;
 641         }
 642         screen->gpu_id = val;
 643
 644         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 645                 DBG("could not get chip-id");
 646                 /* older kernels may not have this property: */
 647                 unsigned core  = screen->gpu_id / 100;
 648                 unsigned major = (screen->gpu_id % 100) / 10;
 649                 unsigned minor = screen->gpu_id % 10;
 650                 unsigned patch = 0;  /* assume the worst */
 651                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 652                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 653         }
 654         screen->chip_id = val;
 655
 656         DBG("Pipe Info:");
 657         DBG(" GPU-id:          %d", screen->gpu_id);
 658         DBG(" Chip-id:         0x%08x", screen->chip_id);
 659         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 660
 661         /* explicitly checking for GPU revisions that are known to work.  This
 662          * may be overly conservative for a3xx, where spoofing the gpu_id with
 663          * the blob driver seems to generate identical cmdstream dumps.  But
 664          * on a2xx, there seem to be small differences between the GPU revs
 665          * so it is probably better to actually test first on real hardware
 666          * before enabling:
 667          *
 668          * If you have a different adreno version, feel free to add it to one
 669          * of the cases below and see what happens.  And if it works, please
 670          * send a patch ;-)
 671          */
 672         switch (screen->gpu_id) {
 673         case 220:
 674                 fd2_screen_init(pscreen);
 675                 break;
 676         case 305:
 677         case 307:
 678         case 320:
 679         case 330:
 680                 fd3_screen_init(pscreen);
 681                 break;
 682         case 420:
 683         case 430:
 684                 fd4_screen_init(pscreen);
 685                 break;
 686         case 530:
 687                 fd5_screen_init(pscreen);
 688                 break;
 689         default:
 690                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 691                 goto fail;
 692         }
 693
 694         if (screen->gpu_id >= 500) {
 695                 screen->gmem_alignw = 64;
 696                 screen->gmem_alignh = 32;
 697         } else {
 698                 screen->gmem_alignw = 32;
 699                 screen->gmem_alignh = 32;
 700         }
 701
 702         /* NOTE: don't enable reordering on a2xx, since completely untested.
 703          * Also, don't enable if we have too old of a kernel to support
 704          * growable cmdstream buffers, since memory requirement for cmdstream
 705          * buffers would be too much otherwise.
 706          */
 707         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 708                 screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
 709
 710         fd_bc_init(&screen->batch_cache);
 711
 712         (void) mtx_init(&screen->lock, mtx_plain);
 713
 714         pscreen->destroy = fd_screen_destroy;
 715         pscreen->get_param = fd_screen_get_param;
 716         pscreen->get_paramf = fd_screen_get_paramf;
 717         pscreen->get_shader_param = fd_screen_get_shader_param;
 718         pscreen->get_compiler_options = fd_get_compiler_options;
 719
 720         fd_resource_screen_init(pscreen);
 721         fd_query_screen_init(pscreen);
 722
 723         pscreen->get_name = fd_screen_get_name;
 724         pscreen->get_vendor = fd_screen_get_vendor;
 725         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 726
 727         pscreen->get_timestamp = fd_screen_get_timestamp;
 728
 729         pscreen->fence_reference = fd_fence_ref;
 730         pscreen->fence_finish = fd_fence_finish;
 731         pscreen->fence_get_fd = fd_fence_get_fd;
 732
 733         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 734
 735         util_format_s3tc_init();
 736
 737         return pscreen;
 738
 739 fail:
 740         fd_screen_destroy(pscreen);
 741         return NULL;
 742 }