1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
34 #include "freedreno_state.h"
35 #include "freedreno_context.h"
36 #include "freedreno_zsa.h"
37 #include "freedreno_rasterizer.h"
38 #include "freedreno_blend.h"
39 #include "freedreno_program.h"
40 #include "freedreno_resource.h"
41 #include "freedreno_texture.h"
42 #include "freedreno_gmem.h"
43 #include "freedreno_util.h"
46 fd_set_blend_color(struct pipe_context
*pctx
,
47 const struct pipe_blend_color
*blend_color
)
49 struct fd_context
*ctx
= fd_context(pctx
);
50 ctx
->blend_color
= *blend_color
;
51 ctx
->dirty
|= FD_DIRTY_BLEND_COLOR
;
55 fd_set_stencil_ref(struct pipe_context
*pctx
,
56 const struct pipe_stencil_ref
*stencil_ref
)
58 struct fd_context
*ctx
= fd_context(pctx
);
59 ctx
->stencil_ref
=* stencil_ref
;
60 ctx
->dirty
|= FD_DIRTY_STENCIL_REF
;
64 fd_set_clip_state(struct pipe_context
*pctx
,
65 const struct pipe_clip_state
*clip
)
71 fd_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
73 struct fd_context
*ctx
= fd_context(pctx
);
74 ctx
->sample_mask
= (uint16_t)sample_mask
;
75 ctx
->dirty
|= FD_DIRTY_SAMPLE_MASK
;
78 /* notes from calim on #dri-devel:
79 * index==0 will be non-UBO (ie. glUniformXYZ()) all packed together padded
81 * I should be able to consider that I own the user_ptr until the next
82 * set_constant_buffer() call, at which point I don't really care about the
84 * index>0 will be UBO's.. well, I'll worry about that later
87 fd_set_constant_buffer(struct pipe_context
*pctx
, uint shader
, uint index
,
88 struct pipe_constant_buffer
*cb
)
90 struct fd_context
*ctx
= fd_context(pctx
);
91 struct fd_constbuf_stateobj
*so
= &ctx
->constbuf
[shader
];
93 /* Note that the state tracker can unbind constant buffers by
97 so
->enabled_mask
&= ~(1 << index
);
98 so
->dirty_mask
&= ~(1 << index
);
99 pipe_resource_reference(&so
->cb
[index
].buffer
, NULL
);
103 pipe_resource_reference(&so
->cb
[index
].buffer
, cb
->buffer
);
104 so
->cb
[index
].buffer_offset
= cb
->buffer_offset
;
105 so
->cb
[index
].buffer_size
= cb
->buffer_size
;
106 so
->cb
[index
].user_buffer
= cb
->user_buffer
;
108 so
->enabled_mask
|= 1 << index
;
109 so
->dirty_mask
|= 1 << index
;
110 ctx
->dirty
|= FD_DIRTY_CONSTBUF
;
114 fd_set_framebuffer_state(struct pipe_context
*pctx
,
115 const struct pipe_framebuffer_state
*framebuffer
)
117 struct fd_context
*ctx
= fd_context(pctx
);
118 struct pipe_framebuffer_state
*cso
= &ctx
->framebuffer
;
121 DBG("%d: cbufs[0]=%p, zsbuf=%p", ctx
->needs_flush
,
122 cso
->cbufs
[0], cso
->zsbuf
);
124 fd_context_render(pctx
);
126 for (i
= 0; i
< framebuffer
->nr_cbufs
; i
++)
127 pipe_surface_reference(&cso
->cbufs
[i
], framebuffer
->cbufs
[i
]);
128 for (; i
< ctx
->framebuffer
.nr_cbufs
; i
++)
129 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
131 cso
->nr_cbufs
= framebuffer
->nr_cbufs
;
132 cso
->width
= framebuffer
->width
;
133 cso
->height
= framebuffer
->height
;
135 pipe_surface_reference(&cso
->zsbuf
, framebuffer
->zsbuf
);
137 ctx
->dirty
|= FD_DIRTY_FRAMEBUFFER
;
141 fd_set_polygon_stipple(struct pipe_context
*pctx
,
142 const struct pipe_poly_stipple
*stipple
)
144 struct fd_context
*ctx
= fd_context(pctx
);
145 ctx
->stipple
= *stipple
;
146 ctx
->dirty
|= FD_DIRTY_STIPPLE
;
150 fd_set_scissor_state(struct pipe_context
*pctx
,
151 const struct pipe_scissor_state
*scissor
)
153 struct fd_context
*ctx
= fd_context(pctx
);
155 ctx
->scissor
= *scissor
;
156 ctx
->dirty
|= FD_DIRTY_SCISSOR
;
160 fd_set_viewport_state(struct pipe_context
*pctx
,
161 const struct pipe_viewport_state
*viewport
)
163 struct fd_context
*ctx
= fd_context(pctx
);
164 ctx
->viewport
= *viewport
;
165 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
169 fd_set_vertex_buffers(struct pipe_context
*pctx
,
170 unsigned start_slot
, unsigned count
,
171 const struct pipe_vertex_buffer
*vb
)
173 struct fd_context
*ctx
= fd_context(pctx
);
174 struct fd_vertexbuf_stateobj
*so
= &ctx
->vertexbuf
;
176 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
, start_slot
, count
);
177 so
->count
= util_last_bit(so
->enabled_mask
);
179 ctx
->dirty
|= FD_DIRTY_VERTEXBUF
;
183 fd_set_index_buffer(struct pipe_context
*pctx
,
184 const struct pipe_index_buffer
*ib
)
186 struct fd_context
*ctx
= fd_context(pctx
);
189 pipe_resource_reference(&ctx
->indexbuf
.buffer
, ib
->buffer
);
190 ctx
->indexbuf
.index_size
= ib
->index_size
;
191 ctx
->indexbuf
.offset
= ib
->offset
;
192 ctx
->indexbuf
.user_buffer
= ib
->user_buffer
;
194 pipe_resource_reference(&ctx
->indexbuf
.buffer
, NULL
);
197 ctx
->dirty
|= FD_DIRTY_INDEXBUF
;
201 fd_state_init(struct pipe_context
*pctx
)
203 pctx
->set_blend_color
= fd_set_blend_color
;
204 pctx
->set_stencil_ref
= fd_set_stencil_ref
;
205 pctx
->set_clip_state
= fd_set_clip_state
;
206 pctx
->set_sample_mask
= fd_set_sample_mask
;
207 pctx
->set_constant_buffer
= fd_set_constant_buffer
;
208 pctx
->set_framebuffer_state
= fd_set_framebuffer_state
;
209 pctx
->set_polygon_stipple
= fd_set_polygon_stipple
;
210 pctx
->set_scissor_state
= fd_set_scissor_state
;
211 pctx
->set_viewport_state
= fd_set_viewport_state
;
213 pctx
->set_vertex_buffers
= fd_set_vertex_buffers
;
214 pctx
->set_index_buffer
= fd_set_index_buffer
;
217 /* NOTE: just define the position for const regs statically.. the blob
218 * driver doesn't seem to change these dynamically, and I can't really
219 * think of a good reason to so..
221 #define VS_CONST_BASE 0x20
222 #define PS_CONST_BASE 0x120
225 emit_constants(struct fd_ringbuffer
*ring
, uint32_t base
,
226 struct fd_constbuf_stateobj
*constbuf
,
227 struct fd_shader_stateobj
*shader
)
229 uint32_t enabled_mask
= constbuf
->enabled_mask
;
230 uint32_t start_base
= base
;
233 // XXX TODO only emit dirty consts.. but we need to keep track if
234 // they are clobbered by a clear, gmem2mem, or mem2gmem..
235 constbuf
->dirty_mask
= enabled_mask
;
237 /* emit user constants: */
238 while (enabled_mask
) {
239 unsigned index
= ffs(enabled_mask
) - 1;
240 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
241 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
243 // I expect that size should be a multiple of vec4's:
244 assert(size
== align(size
, 4));
246 /* hmm, sometimes we still seem to end up with consts bound,
247 * even if shader isn't using them, which ends up overwriting
248 * const reg's used for immediates.. this is a hack to work
251 if (shader
&& ((base
- start_base
) >= (shader
->first_immediate
* 4)))
254 if (constbuf
->dirty_mask
& (1 << index
)) {
255 const uint32_t *dwords
;
257 if (cb
->user_buffer
) {
258 dwords
= cb
->user_buffer
;
260 struct fd_resource
*rsc
= fd_resource(cb
->buffer
);
261 dwords
= fd_bo_map(rsc
->bo
);
264 dwords
= (uint32_t *)(((uint8_t *)dwords
) + cb
->buffer_offset
);
266 OUT_PKT3(ring
, CP_SET_CONSTANT
, size
+ 1);
267 OUT_RING(ring
, base
);
268 for (i
= 0; i
< size
; i
++)
269 OUT_RING(ring
, *(dwords
++));
271 constbuf
->dirty_mask
&= ~(1 << index
);
275 enabled_mask
&= ~(1 << index
);
278 /* emit shader immediates: */
280 for (i
= 0; i
< shader
->num_immediates
; i
++) {
281 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
282 OUT_RING(ring
, base
);
283 OUT_RING(ring
, shader
->immediates
[i
].val
[0]);
284 OUT_RING(ring
, shader
->immediates
[i
].val
[1]);
285 OUT_RING(ring
, shader
->immediates
[i
].val
[2]);
286 OUT_RING(ring
, shader
->immediates
[i
].val
[3]);
292 /* this works at least for a220 and earlier.. if later gpu's gain more than
293 * 32 texture units, might need to bump this up to uint64_t
295 typedef uint32_t texmask
;
298 emit_texture(struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
299 struct fd_texture_stateobj
*tex
, unsigned samp_id
, texmask emitted
)
301 unsigned const_idx
= fd_get_const_idx(ctx
, tex
, samp_id
);
302 struct fd_sampler_stateobj
*sampler
;
303 struct fd_pipe_sampler_view
*view
;
305 if (emitted
& (1 << const_idx
))
308 sampler
= tex
->samplers
[samp_id
];
309 view
= fd_pipe_sampler_view(tex
->textures
[samp_id
]);
311 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
312 OUT_RING(ring
, 0x00010000 + (0x6 * const_idx
));
314 OUT_RING(ring
, sampler
->tex0
| view
->tex0
);
315 OUT_RELOC(ring
, view
->tex_resource
->bo
, 0, view
->fmt
);
316 OUT_RING(ring
, view
->tex2
);
317 OUT_RING(ring
, sampler
->tex3
| view
->tex3
);
318 OUT_RING(ring
, sampler
->tex4
);
319 OUT_RING(ring
, sampler
->tex5
);
321 return (1 << const_idx
);
325 emit_textures(struct fd_ringbuffer
*ring
, struct fd_context
*ctx
)
330 for (i
= 0; i
< ctx
->verttex
.num_samplers
; i
++)
331 if (ctx
->verttex
.samplers
[i
])
332 emitted
|= emit_texture(ring
, ctx
, &ctx
->verttex
, i
, emitted
);
334 for (i
= 0; i
< ctx
->fragtex
.num_samplers
; i
++)
335 if (ctx
->fragtex
.samplers
[i
])
336 emitted
|= emit_texture(ring
, ctx
, &ctx
->fragtex
, i
, emitted
);
340 fd_emit_vertex_bufs(struct fd_ringbuffer
*ring
, uint32_t val
,
341 struct fd_vertex_buf
*vbufs
, uint32_t n
)
345 OUT_PKT3(ring
, CP_SET_CONSTANT
, 1 + (2 * n
));
346 OUT_RING(ring
, (0x1 << 16) | (val
& 0xffff));
347 for (i
= 0; i
< n
; i
++) {
348 struct fd_resource
*rsc
= fd_resource(vbufs
[i
].prsc
);
349 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 3);
350 OUT_RING (ring
, vbufs
[i
].size
);
355 fd_state_emit(struct pipe_context
*pctx
, uint32_t dirty
)
357 struct fd_context
*ctx
= fd_context(pctx
);
358 struct fd_ringbuffer
*ring
= ctx
->ring
;
360 /* NOTE: we probably want to eventually refactor this so each state
361 * object handles emitting it's own state.. although the mapping of
362 * state to registers is not always orthogonal, sometimes a single
363 * register contains bitfields coming from multiple state objects,
364 * so not sure the best way to deal with that yet.
367 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
368 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
369 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
370 OUT_RING(ring
, ctx
->sample_mask
);
373 if (dirty
& FD_DIRTY_ZSA
) {
374 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
376 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
377 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
378 OUT_RING(ring
, ctx
->zsa
->rb_depthcontrol
);
380 OUT_PKT3(ring
, CP_SET_CONSTANT
, 4);
381 OUT_RING(ring
, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF
));
382 OUT_RING(ring
, ctx
->zsa
->rb_stencilrefmask_bf
|
383 A2XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[1]));
384 OUT_RING(ring
, ctx
->zsa
->rb_stencilrefmask
|
385 A2XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
386 OUT_RING(ring
, ctx
->zsa
->rb_alpha_ref
);
389 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
390 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
391 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
392 OUT_RING(ring
, ctx
->rasterizer
->pa_cl_clip_cntl
);
393 OUT_RING(ring
, ctx
->rasterizer
->pa_su_sc_mode_cntl
|
394 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE
);
396 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
397 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_POINT_SIZE
));
398 OUT_RING(ring
, ctx
->rasterizer
->pa_su_point_size
);
399 OUT_RING(ring
, ctx
->rasterizer
->pa_su_point_minmax
);
400 OUT_RING(ring
, ctx
->rasterizer
->pa_su_line_cntl
);
401 OUT_RING(ring
, ctx
->rasterizer
->pa_sc_line_stipple
);
403 OUT_PKT3(ring
, CP_SET_CONSTANT
, 6);
404 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_VTX_CNTL
));
405 OUT_RING(ring
, ctx
->rasterizer
->pa_su_vtx_cntl
);
406 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
407 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
408 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
409 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
412 if (dirty
& FD_DIRTY_SCISSOR
) {
413 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
414 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
415 OUT_RING(ring
, xy2d(ctx
->scissor
.minx
, /* PA_SC_WINDOW_SCISSOR_TL */
417 OUT_RING(ring
, xy2d(ctx
->scissor
.maxx
, /* PA_SC_WINDOW_SCISSOR_BR */
420 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, ctx
->scissor
.minx
);
421 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, ctx
->scissor
.miny
);
422 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, ctx
->scissor
.maxx
);
423 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, ctx
->scissor
.maxy
);
426 if (dirty
& FD_DIRTY_VIEWPORT
) {
427 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
428 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE
));
429 OUT_RING(ring
, fui(ctx
->viewport
.scale
[0])); /* PA_CL_VPORT_XSCALE */
430 OUT_RING(ring
, fui(ctx
->viewport
.translate
[0])); /* PA_CL_VPORT_XOFFSET */
431 OUT_RING(ring
, fui(ctx
->viewport
.scale
[1])); /* PA_CL_VPORT_YSCALE */
432 OUT_RING(ring
, fui(ctx
->viewport
.translate
[1])); /* PA_CL_VPORT_YOFFSET */
433 OUT_RING(ring
, fui(ctx
->viewport
.scale
[2])); /* PA_CL_VPORT_ZSCALE */
434 OUT_RING(ring
, fui(ctx
->viewport
.translate
[2])); /* PA_CL_VPORT_ZOFFSET */
436 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
437 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
438 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT
|
439 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
440 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
441 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
442 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
|
443 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA
|
444 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA
);
447 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_VTX
| FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
)) {
448 fd_program_validate(ctx
);
449 fd_program_emit(ring
, &ctx
->prog
);
452 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
453 emit_constants(ring
, VS_CONST_BASE
* 4,
454 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
455 (dirty
& FD_DIRTY_PROG
) ? ctx
->prog
.vp
: NULL
);
456 emit_constants(ring
, PS_CONST_BASE
* 4,
457 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
458 (dirty
& FD_DIRTY_PROG
) ? ctx
->prog
.fp
: NULL
);
461 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_ZSA
)) {
462 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
463 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLORCONTROL
));
464 OUT_RING(ring
, ctx
->zsa
->rb_colorcontrol
| ctx
->blend
->rb_colorcontrol
);
467 if (dirty
& FD_DIRTY_BLEND
) {
468 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
469 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_CONTROL
));
470 OUT_RING(ring
, ctx
->blend
->rb_blendcontrol
);
472 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
473 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
474 OUT_RING(ring
, ctx
->blend
->rb_colormask
);
477 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
| FD_DIRTY_PROG
))
478 emit_textures(ring
, ctx
);
480 ctx
->dirty
&= ~dirty
;
483 /* emit per-context initialization:
486 fd_state_emit_setup(struct pipe_context
*pctx
)
488 struct fd_context
*ctx
= fd_context(pctx
);
489 struct fd_ringbuffer
*ring
= ctx
->ring
;
491 OUT_PKT0(ring
, REG_A2XX_TP0_CHICKEN
, 1);
492 OUT_RING(ring
, 0x00000002);
494 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
495 OUT_RING(ring
, 0x00007fff);
497 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
498 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_VS_CONST
));
499 OUT_RING(ring
, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE
) |
500 A2XX_SQ_VS_CONST_SIZE(0x100));
502 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
503 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_PS_CONST
));
504 OUT_RING(ring
, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE
) |
505 A2XX_SQ_PS_CONST_SIZE(0xe0));
507 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
508 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX
));
509 OUT_RING(ring
, 0xffffffff); /* VGT_MAX_VTX_INDX */
510 OUT_RING(ring
, 0x00000000); /* VGT_MIN_VTX_INDX */
512 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
513 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
514 OUT_RING(ring
, 0x00000000);
516 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
517 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
518 OUT_RING(ring
, 0x0000003b);
520 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
521 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_CONTEXT_MISC
));
522 OUT_RING(ring
, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY
));
524 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
525 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL
));
526 OUT_RING(ring
, 0xffffffff);
528 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
529 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_CONFIG
));
530 OUT_RING(ring
, 0x00000000);
532 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
533 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_LINE_CNTL
));
534 OUT_RING(ring
, 0x00000000);
536 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
537 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
538 OUT_RING(ring
, 0x00000000);
540 // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
541 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
542 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
543 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH
));
545 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
546 OUT_RING(ring
, CP_REG(REG_A2XX_RB_SAMPLE_POS
));
547 OUT_RING(ring
, 0x88888888);
549 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
550 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK
));
551 OUT_RING(ring
, 0xffffffff);
553 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
554 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_DEST_INFO
));
555 OUT_RING(ring
, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4
) |
556 A2XX_RB_COPY_DEST_INFO_WRITE_RED
|
557 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN
|
558 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE
|
559 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA
);
561 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
562 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_WRAPPING_0
));
563 OUT_RING(ring
, 0x00000000); /* SQ_WRAPPING_0 */
564 OUT_RING(ring
, 0x00000000); /* SQ_WRAPPING_1 */
566 OUT_PKT3(ring
, CP_SET_DRAW_INIT_FLAGS
, 1);
567 OUT_RING(ring
, 0x00000000);
569 OUT_PKT3(ring
, CP_WAIT_REG_EQ
, 4);
570 OUT_RING(ring
, 0x000005d0);
571 OUT_RING(ring
, 0x00000000);
572 OUT_RING(ring
, 0x5f601000);
573 OUT_RING(ring
, 0x00000001);
575 OUT_PKT0(ring
, REG_A2XX_SQ_INST_STORE_MANAGMENT
, 1);
576 OUT_RING(ring
, 0x00000180);
578 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
579 OUT_RING(ring
, 0x00000300);
581 OUT_PKT3(ring
, CP_SET_SHADER_BASES
, 1);
582 OUT_RING(ring
, 0x80000180);
584 /* not sure what this form of CP_SET_CONSTANT is.. */
585 OUT_PKT3(ring
, CP_SET_CONSTANT
, 13);
586 OUT_RING(ring
, 0x00000000);
587 OUT_RING(ring
, 0x00000000);
588 OUT_RING(ring
, 0x00000000);
589 OUT_RING(ring
, 0x00000000);
590 OUT_RING(ring
, 0x00000000);
591 OUT_RING(ring
, 0x469c4000);
592 OUT_RING(ring
, 0x3f800000);
593 OUT_RING(ring
, 0x3f000000);
594 OUT_RING(ring
, 0x00000000);
595 OUT_RING(ring
, 0x40000000);
596 OUT_RING(ring
, 0x3f400000);
597 OUT_RING(ring
, 0x3ec00000);
598 OUT_RING(ring
, 0x3e800000);
600 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
601 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
602 OUT_RING(ring
, A2XX_RB_COLOR_MASK_WRITE_RED
|
603 A2XX_RB_COLOR_MASK_WRITE_GREEN
|
604 A2XX_RB_COLOR_MASK_WRITE_BLUE
|
605 A2XX_RB_COLOR_MASK_WRITE_ALPHA
);
607 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
608 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_RED
));
609 OUT_RING(ring
, 0x00000000); /* RB_BLEND_RED */
610 OUT_RING(ring
, 0x00000000); /* RB_BLEND_GREEN */
611 OUT_RING(ring
, 0x00000000); /* RB_BLEND_BLUE */
612 OUT_RING(ring
, 0x000000ff); /* RB_BLEND_ALPHA */
614 fd_ringbuffer_flush(ring
);
615 fd_ringmarker_mark(ctx
->draw_start
);